From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48287) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c0gbA-0008Ue-Rg for qemu-devel@nongnu.org; Sat, 29 Oct 2016 23:15:56 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1c0gb7-0005iC-BN for qemu-devel@nongnu.org; Sat, 29 Oct 2016 23:15:52 -0400 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:53909) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1c0gb7-0005h2-1m for qemu-devel@nongnu.org; Sat, 29 Oct 2016 23:15:49 -0400 Received: from pps.filterd (m0098396.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.17/8.16.0.17) with SMTP id u9U3DOZB063938 for ; Sat, 29 Oct 2016 23:15:48 -0400 Received: from e28smtp04.in.ibm.com (e28smtp04.in.ibm.com [125.16.236.4]) by mx0a-001b2d01.pphosted.com with ESMTP id 26cp3ehksm-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Sat, 29 Oct 2016 23:15:47 -0400 Received: from localhost by e28smtp04.in.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Sun, 30 Oct 2016 08:45:39 +0530 From: Nikunj A Dadhania Date: Sun, 30 Oct 2016 08:44:54 +0530 Message-Id: <1477797298-8577-1-git-send-email-nikunj@linux.vnet.ibm.com> Subject: [Qemu-devel] [PATCH v3 0/4] POWER9 TCG enablements - part7 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, rth@twiddle.net Cc: qemu-devel@nongnu.org, nikunj@linux.vnet.ibm.com, bharata@linux.vnet.ibm.com, ego@linux.vnet.ibm.com This series contains 7 new instructions for POWER9 ISA3.0 Vector Rotate Left Dword Vector Rotate Left Word Vector Parity Byte Changelog: v2: * added internal.h with MASK definition (David/Richard) * simplified vparity without recursion (Richard) v1: * Simplify extract routines (Richard) * Added ror/rol fix (Richard) * Added vector parity and vector compare instructions v0: * Use extract32 and extract64 helper (Richard) * Use rol32 and rol64 helper (Richard) Patches: 01: Fix ror[8,16,32,64] and rol[8,16,32,64] 02: vrldmi: Vector Rotate Left Dword then Mask Insert vrlwmi: Vector Rotate Left Word then Mask Insert 03: vrldnm: Vector Rotate Left Doubleword then AND with Mask vrlwnm: Vector Rotate Left Word then AND with Mask 04: vprtybw: Vector Parity Byte Word vprtybd: Vector Parity Byte Double Word vprtybq: Vector Parity Byte Quad Word Ankit Kumar (1): target-ppc: add vprtyb[w/d/q] instructions Bharata B Rao (1): target-ppc: add vrldnm and vrlwnm instructions Gautham R. Shenoy (1): target-ppc: add vrldnmi and vrlwmi instructions Nikunj A Dadhania (1): bitops: fix rol/ror when shift is zero disas/ppc.c | 4 +++ include/qemu/bitops.h | 16 +++++----- target-ppc/helper.h | 7 +++++ target-ppc/int_helper.c | 63 +++++++++++++++++++++++++++++++++++++ target-ppc/internal.h | 50 +++++++++++++++++++++++++++++ target-ppc/translate.c | 29 +---------------- target-ppc/translate/vmx-impl.inc.c | 15 +++++++++ target-ppc/translate/vmx-ops.inc.c | 12 ++++--- 8 files changed, 156 insertions(+), 40 deletions(-) create mode 100644 target-ppc/internal.h -- 2.7.4