From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58490) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c1Eth-0001cO-Jn for qemu-devel@nongnu.org; Mon, 31 Oct 2016 11:53:19 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1c1Etg-0000op-Jx for qemu-devel@nongnu.org; Mon, 31 Oct 2016 11:53:17 -0400 Received: from mail-qk0-x244.google.com ([2607:f8b0:400d:c09::244]:34425) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1c1Etg-0000oU-Ew for qemu-devel@nongnu.org; Mon, 31 Oct 2016 11:53:16 -0400 Received: by mail-qk0-x244.google.com with SMTP id o68so7244488qkf.1 for ; Mon, 31 Oct 2016 08:53:16 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Mon, 31 Oct 2016 09:52:47 -0600 Message-Id: <1477929173-2006-10-git-send-email-rth@twiddle.net> In-Reply-To: <1477929173-2006-1-git-send-email-rth@twiddle.net> References: <1477929173-2006-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PULL for-2.8 09/15] target-sparc: Implement BCOPY/BFILL inline List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org Tested-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target-sparc/translate.c | 63 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 63 insertions(+) diff --git a/target-sparc/translate.c b/target-sparc/translate.c index 0fb361a..3b3389c 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -2036,6 +2036,8 @@ typedef enum { GET_ASI_DTWINX, GET_ASI_BLOCK, GET_ASI_SHORT, + GET_ASI_BCOPY, + GET_ASI_BFILL, } ASIType; typedef struct { @@ -2077,6 +2079,14 @@ static DisasASI get_asi(DisasContext *dc, int insn, TCGMemOp memop) mem_idx = MMU_PHYS_IDX; type = GET_ASI_DIRECT; break; + case ASI_M_BCOPY: /* Block copy, sta access */ + mem_idx = MMU_KERNEL_IDX; + type = GET_ASI_BCOPY; + break; + case ASI_M_BFILL: /* Block fill, stda access */ + mem_idx = MMU_KERNEL_IDX; + type = GET_ASI_BFILL; + break; } } else { gen_exception(dc, TT_PRIV_INSN); @@ -2294,6 +2304,38 @@ static void gen_st_asi(DisasContext *dc, TCGv src, TCGv addr, gen_address_mask(dc, addr); tcg_gen_qemu_st_tl(src, addr, da.mem_idx, da.memop); break; +#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) + case GET_ASI_BCOPY: + /* Copy 32 bytes from the address in SRC to ADDR. */ + /* ??? The original qemu code suggests 4-byte alignment, dropping + the low bits, but the only place I can see this used is in the + Linux kernel with 32 byte alignment, which would make more sense + as a cacheline-style operation. */ + { + TCGv s_addr = tcg_temp_new(); + TCGv d_addr = tcg_temp_new(); + TCGv four = tcg_const_tl(4); + TCGv_i32 tmp = tcg_temp_new_i32(); + int i; + + tcg_gen_andi_tl(s_addr, src, -4); + tcg_gen_andi_tl(d_addr, addr, -4); + for (i = 0; i < 32; i += 4) { + /* Since the loads and stores are paired, allow the + copy to happen in the host endianness. */ + tcg_gen_qemu_ld_i32(tmp, s_addr, da.mem_idx, MO_UL); + tcg_gen_qemu_st_i32(tmp, d_addr, da.mem_idx, MO_UL); + tcg_gen_add_tl(s_addr, s_addr, four); + tcg_gen_add_tl(d_addr, d_addr, four); + } + + tcg_temp_free(s_addr); + tcg_temp_free(d_addr); + tcg_temp_free(four); + tcg_temp_free_i32(tmp); + } + break; +#endif default: { TCGv_i32 r_asi = tcg_const_i32(da.asi); @@ -2766,6 +2808,27 @@ static void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr, gen_address_mask(dc, addr); tcg_gen_qemu_st_i64(t64, addr, da.mem_idx, da.memop); break; + case GET_ASI_BFILL: + /* Store 32 bytes of T64 to ADDR. */ + /* ??? The original qemu code suggests 8-byte alignment, dropping + the low bits, but the only place I can see this used is in the + Linux kernel with 32 byte alignment, which would make more sense + as a cacheline-style operation. */ + { + TCGv d_addr = tcg_temp_new(); + TCGv eight = tcg_const_tl(8); + int i; + + tcg_gen_andi_tl(d_addr, addr, -8); + for (i = 0; i < 32; i += 8) { + tcg_gen_qemu_st_i64(t64, d_addr, da.mem_idx, da.memop); + tcg_gen_add_tl(d_addr, d_addr, eight); + } + + tcg_temp_free(d_addr); + tcg_temp_free(eight); + } + break; default: { TCGv_i32 r_asi = tcg_const_i32(da.asi); -- 2.7.4