* [Qemu-devel] [PATCH v3 0/4] POWER9 TCG enablements - BCD functions part I
@ 2016-10-31 17:34 Jose Ricardo Ziviani
2016-10-31 17:34 ` [Qemu-devel] [PATCH v3 1/4] target-ppc: Implement bcdcfn. instruction Jose Ricardo Ziviani
` (3 more replies)
0 siblings, 4 replies; 8+ messages in thread
From: Jose Ricardo Ziviani @ 2016-10-31 17:34 UTC (permalink / raw)
To: qemu-ppc; +Cc: qemu-devel, david, nikunj, bharata
v3:
- generates invalid instruction excpetion when opc4 is not handled/invalid
- changes get_national ret. type to uint16_t to handle invalid encoding
- small improvements
v2:
- implements all fixes and suggestions
This serie contains 4 new instructions for POWER9 ISA3.0
bcdcfn.: Decimal Convert From National
bcdctn.: Decimal Convert To National
bcdcfz.: Decimal Convert From Zoned
bcdctz.: Decimal Convert to Zoned
Jose Ricardo Ziviani (4):
target-ppc: Implement bcdcfn. instruction
target-ppc: Implement bcdctn. instruction
target-ppc: Implement bcdcfz. instruction
target-ppc: Implement bcdctz. instruction
target-ppc/helper.h | 4 +
target-ppc/int_helper.c | 199 ++++++++++++++++++++++++++++++++++++
target-ppc/translate/vmx-impl.inc.c | 85 +++++++++++++++
target-ppc/translate/vmx-ops.inc.c | 4 +-
4 files changed, 290 insertions(+), 2 deletions(-)
--
2.7.4
^ permalink raw reply [flat|nested] 8+ messages in thread* [Qemu-devel] [PATCH v3 1/4] target-ppc: Implement bcdcfn. instruction 2016-10-31 17:34 [Qemu-devel] [PATCH v3 0/4] POWER9 TCG enablements - BCD functions part I Jose Ricardo Ziviani @ 2016-10-31 17:34 ` Jose Ricardo Ziviani 2016-11-01 0:30 ` David Gibson 2016-10-31 17:34 ` [Qemu-devel] [PATCH v3 2/4] target-ppc: Implement bcdctn. instruction Jose Ricardo Ziviani ` (2 subsequent siblings) 3 siblings, 1 reply; 8+ messages in thread From: Jose Ricardo Ziviani @ 2016-10-31 17:34 UTC (permalink / raw) To: qemu-ppc; +Cc: qemu-devel, david, nikunj, bharata bcdcfn. converts from National numeric format to BCD. National format uses a byte to represent a digit where the most significant nibble is always 0x3 and the least sign. nibbles is the digit itself. Signed-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com> --- target-ppc/helper.h | 1 + target-ppc/int_helper.c | 54 ++++++++++++++++++++++++++ target-ppc/translate/vmx-impl.inc.c | 77 +++++++++++++++++++++++++++++++++++++ target-ppc/translate/vmx-ops.inc.c | 4 +- 4 files changed, 134 insertions(+), 2 deletions(-) diff --git a/target-ppc/helper.h b/target-ppc/helper.h index 3916b2e..3b23eed 100644 --- a/target-ppc/helper.h +++ b/target-ppc/helper.h @@ -371,6 +371,7 @@ DEF_HELPER_4(vpermxor, void, avr, avr, avr, avr) DEF_HELPER_4(bcdadd, i32, avr, avr, avr, i32) DEF_HELPER_4(bcdsub, i32, avr, avr, avr, i32) +DEF_HELPER_3(bcdcfn, i32, avr, avr, i32) DEF_HELPER_2(xsadddp, void, env, i32) DEF_HELPER_2(xssubdp, void, env, i32) diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c index dca4798..dc7a429 100644 --- a/target-ppc/int_helper.c +++ b/target-ppc/int_helper.c @@ -2429,6 +2429,8 @@ void helper_vsubecuq(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c) #define BCD_NEG_PREF 0xD #define BCD_NEG_ALT 0xB #define BCD_PLUS_ALT_2 0xE +#define NATIONAL_PLUS 0x2B +#define NATIONAL_NEG 0x2D #if defined(HOST_WORDS_BIGENDIAN) #define BCD_DIG_BYTE(n) (15 - (n/2)) @@ -2495,6 +2497,15 @@ static void bcd_put_digit(ppc_avr_t *bcd, uint8_t digit, int n) } } +static uint16_t get_national_digit(ppc_avr_t *reg, int n) +{ +#if defined(HOST_WORDS_BIGENDIAN) + return reg->u16[8 - n]; +#else + return reg->u16[n]; +#endif +} + static int bcd_cmp_mag(ppc_avr_t *a, ppc_avr_t *b) { int i; @@ -2625,6 +2636,49 @@ uint32_t helper_bcdsub(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t ps) return helper_bcdadd(r, a, &bcopy, ps); } +uint32_t helper_bcdcfn(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps) +{ + int i; + int neq_flag = 0; + int cr = 0; + uint16_t national = 0; + uint16_t sgnb = get_national_digit(b, 0); + ppc_avr_t ret = { .u64 = { 0, 0 } }; + int invalid = (sgnb != NATIONAL_PLUS && sgnb != NATIONAL_NEG); + + for (i = 1; i < 8; i++) { + national = get_national_digit(b, i); + + neq_flag += (national != 0x30); + if (unlikely(national < 0x30 || national > 0x39)) { + invalid = 1; + break; + } + + bcd_put_digit(&ret, national & 0xf, i); + } + + if (sgnb == NATIONAL_PLUS) { + bcd_put_digit(&ret, (ps == 0) ? BCD_PLUS_PREF_1 : BCD_PLUS_PREF_2, 0); + } else { + bcd_put_digit(&ret, BCD_NEG_PREF, 0); + } + + if (neq_flag) { + cr = (sgnb == NATIONAL_PLUS) ? 1 << CRF_GT : 1 << CRF_LT; + } else { + cr = 1 << CRF_EQ; + } + + if (unlikely(invalid)) { + cr = 1 << CRF_SO; + } + + *r = ret; + + return cr; +} + void helper_vsbox(ppc_avr_t *r, ppc_avr_t *a) { int i; diff --git a/target-ppc/translate/vmx-impl.inc.c b/target-ppc/translate/vmx-impl.inc.c index fc612d9..38fea3f 100644 --- a/target-ppc/translate/vmx-impl.inc.c +++ b/target-ppc/translate/vmx-impl.inc.c @@ -945,8 +945,83 @@ static void gen_##op(DisasContext *ctx) \ tcg_temp_free_i32(ps); \ } +#define GEN_BCD2(op) \ +static void gen_##op(DisasContext *ctx) \ +{ \ + TCGv_ptr rd, rb; \ + TCGv_i32 ps; \ + \ + if (unlikely(!ctx->altivec_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_VPU); \ + return; \ + } \ + \ + rb = gen_avr_ptr(rB(ctx->opcode)); \ + rd = gen_avr_ptr(rD(ctx->opcode)); \ + \ + ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \ + \ + gen_helper_##op(cpu_crf[6], rd, rb, ps); \ + \ + tcg_temp_free_ptr(rb); \ + tcg_temp_free_ptr(rd); \ + tcg_temp_free_i32(ps); \ +} + GEN_BCD(bcdadd) GEN_BCD(bcdsub) +GEN_BCD2(bcdcfn) + +static void gen_xpnd04_1(DisasContext *ctx) +{ + switch (opc4(ctx->opcode)) { + case 0: + break; /* bcdctsq. */ + case 2: + break; /* bcdcfsq. */ + case 4: + break; /* bcdctz. */ + case 5: + break; /* bcdctn. */ + case 6: + break; /* bcdcfz. */ + case 7: + gen_bcdcfn(ctx); + break; + case 31: + break; /* bcdsetsgn. */ + default: + gen_invalid(ctx); + break; + } +} + +static void gen_xpnd04_2(DisasContext *ctx) +{ + switch (opc4(ctx->opcode)) { + case 0: + break; /* bcdctsq. */ + case 2: + break; /* bcdcfsq. */ + case 4: + break; /* bcdctz. */ + case 6: + break; /* bcdcfz. */ + case 7: + gen_bcdcfn(ctx); + break; + case 31: + break; /* bcdsetsgn. */ + default: + gen_invalid(ctx); + break; + } +} + +GEN_VXFORM_DUAL(vsubcuw, PPC_ALTIVEC, PPC_NONE, \ + xpnd04_1, PPC_NONE, PPC2_ISA300) +GEN_VXFORM_DUAL(vsubsws, PPC_ALTIVEC, PPC_NONE, \ + xpnd04_2, PPC_NONE, PPC2_ISA300) GEN_VXFORM_DUAL(vsububm, PPC_ALTIVEC, PPC_NONE, \ bcdadd, PPC_NONE, PPC2_ALTIVEC_207) @@ -1023,3 +1098,5 @@ GEN_VXFORM_DUAL(vsldoi, PPC_ALTIVEC, PPC_NONE, #undef GEN_VXFORM_NOA #undef GEN_VXFORM_UIMM #undef GEN_VAFORM_PAIRED + +#undef GEN_BCD2 diff --git a/target-ppc/translate/vmx-ops.inc.c b/target-ppc/translate/vmx-ops.inc.c index cc7ed7e..637b43c 100644 --- a/target-ppc/translate/vmx-ops.inc.c +++ b/target-ppc/translate/vmx-ops.inc.c @@ -122,7 +122,7 @@ GEN_VXFORM_300(vslv, 2, 29), GEN_VXFORM(vslo, 6, 16), GEN_VXFORM(vsro, 6, 17), GEN_VXFORM(vaddcuw, 0, 6), -GEN_VXFORM(vsubcuw, 0, 22), +GEN_VXFORM_DUAL(vsubcuw, xpnd04_1, 0, 22, PPC_ALTIVEC, PPC_NONE), GEN_VXFORM_DUAL(vaddubs, vmul10uq, 0, 8, PPC_ALTIVEC, PPC_NONE), GEN_VXFORM_DUAL(vadduhs, vmul10euq, 0, 9, PPC_ALTIVEC, PPC_NONE), GEN_VXFORM(vadduws, 0, 10), @@ -134,7 +134,7 @@ GEN_VXFORM_DUAL(vsubuhs, bcdsub, 0, 25, PPC_ALTIVEC, PPC_NONE), GEN_VXFORM(vsubuws, 0, 26), GEN_VXFORM(vsubsbs, 0, 28), GEN_VXFORM(vsubshs, 0, 29), -GEN_VXFORM(vsubsws, 0, 30), +GEN_VXFORM_DUAL(vsubsws, xpnd04_2, 0, 30, PPC_ALTIVEC, PPC_NONE), GEN_VXFORM_207(vadduqm, 0, 4), GEN_VXFORM_207(vaddcuq, 0, 5), GEN_VXFORM_DUAL(vaddeuqm, vaddecuq, 30, 0xFF, PPC_NONE, PPC2_ALTIVEC_207), -- 2.7.4 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [Qemu-devel] [PATCH v3 1/4] target-ppc: Implement bcdcfn. instruction 2016-10-31 17:34 ` [Qemu-devel] [PATCH v3 1/4] target-ppc: Implement bcdcfn. instruction Jose Ricardo Ziviani @ 2016-11-01 0:30 ` David Gibson 0 siblings, 0 replies; 8+ messages in thread From: David Gibson @ 2016-11-01 0:30 UTC (permalink / raw) To: Jose Ricardo Ziviani; +Cc: qemu-ppc, qemu-devel, nikunj, bharata [-- Attachment #1: Type: text/plain, Size: 8552 bytes --] On Mon, Oct 31, 2016 at 03:34:46PM -0200, Jose Ricardo Ziviani wrote: > bcdcfn. converts from National numeric format to BCD. National format > uses a byte to represent a digit where the most significant nibble is > always 0x3 and the least sign. nibbles is the digit itself. > > Signed-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com> Sorry, couple more tweaks I've thought of. > --- > target-ppc/helper.h | 1 + > target-ppc/int_helper.c | 54 ++++++++++++++++++++++++++ > target-ppc/translate/vmx-impl.inc.c | 77 +++++++++++++++++++++++++++++++++++++ > target-ppc/translate/vmx-ops.inc.c | 4 +- > 4 files changed, 134 insertions(+), 2 deletions(-) > > diff --git a/target-ppc/helper.h b/target-ppc/helper.h > index 3916b2e..3b23eed 100644 > --- a/target-ppc/helper.h > +++ b/target-ppc/helper.h > @@ -371,6 +371,7 @@ DEF_HELPER_4(vpermxor, void, avr, avr, avr, avr) > > DEF_HELPER_4(bcdadd, i32, avr, avr, avr, i32) > DEF_HELPER_4(bcdsub, i32, avr, avr, avr, i32) > +DEF_HELPER_3(bcdcfn, i32, avr, avr, i32) > > DEF_HELPER_2(xsadddp, void, env, i32) > DEF_HELPER_2(xssubdp, void, env, i32) > diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c > index dca4798..dc7a429 100644 > --- a/target-ppc/int_helper.c > +++ b/target-ppc/int_helper.c > @@ -2429,6 +2429,8 @@ void helper_vsubecuq(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c) > #define BCD_NEG_PREF 0xD > #define BCD_NEG_ALT 0xB > #define BCD_PLUS_ALT_2 0xE > +#define NATIONAL_PLUS 0x2B > +#define NATIONAL_NEG 0x2D > > #if defined(HOST_WORDS_BIGENDIAN) > #define BCD_DIG_BYTE(n) (15 - (n/2)) > @@ -2495,6 +2497,15 @@ static void bcd_put_digit(ppc_avr_t *bcd, uint8_t digit, int n) > } > } > > +static uint16_t get_national_digit(ppc_avr_t *reg, int n) > +{ > +#if defined(HOST_WORDS_BIGENDIAN) > + return reg->u16[8 - n]; > +#else > + return reg->u16[n]; > +#endif > +} > + > static int bcd_cmp_mag(ppc_avr_t *a, ppc_avr_t *b) > { > int i; > @@ -2625,6 +2636,49 @@ uint32_t helper_bcdsub(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t ps) > return helper_bcdadd(r, a, &bcopy, ps); > } > > +uint32_t helper_bcdcfn(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps) > +{ > + int i; > + int neq_flag = 0; > + int cr = 0; > + uint16_t national = 0; > + uint16_t sgnb = get_national_digit(b, 0); > + ppc_avr_t ret = { .u64 = { 0, 0 } }; > + int invalid = (sgnb != NATIONAL_PLUS && sgnb != NATIONAL_NEG); > + > + for (i = 1; i < 8; i++) { > + national = get_national_digit(b, i); > + > + neq_flag += (national != 0x30); Specifically adding up the non-zero digits is a bit clunky. You're already converting the value to BCD, so you could... > + if (unlikely(national < 0x30 || national > 0x39)) { > + invalid = 1; > + break; > + } > + > + bcd_put_digit(&ret, national & 0xf, i); > + } > + > + if (sgnb == NATIONAL_PLUS) { > + bcd_put_digit(&ret, (ps == 0) ? BCD_PLUS_PREF_1 : BCD_PLUS_PREF_2, 0); > + } else { > + bcd_put_digit(&ret, BCD_NEG_PREF, 0); > + } > + > + if (neq_flag) { ... just check if the BCD output is zero here. I think that will amount to ((ret.u64[1] >> 4) != 0), but it's probably worth adding a bcd_is_zero() helper for this. > + cr = (sgnb == NATIONAL_PLUS) ? 1 << CRF_GT : 1 << CRF_LT; > + } else { > + cr = 1 << CRF_EQ; > + } > + > + if (unlikely(invalid)) { > + cr = 1 << CRF_SO; > + } > + > + *r = ret; > + > + return cr; > +} > + > void helper_vsbox(ppc_avr_t *r, ppc_avr_t *a) > { > int i; > diff --git a/target-ppc/translate/vmx-impl.inc.c b/target-ppc/translate/vmx-impl.inc.c > index fc612d9..38fea3f 100644 > --- a/target-ppc/translate/vmx-impl.inc.c > +++ b/target-ppc/translate/vmx-impl.inc.c > @@ -945,8 +945,83 @@ static void gen_##op(DisasContext *ctx) \ > tcg_temp_free_i32(ps); \ > } > > +#define GEN_BCD2(op) \ > +static void gen_##op(DisasContext *ctx) \ > +{ \ > + TCGv_ptr rd, rb; \ > + TCGv_i32 ps; \ > + \ > + if (unlikely(!ctx->altivec_enabled)) { \ > + gen_exception(ctx, POWERPC_EXCP_VPU); \ > + return; \ > + } \ > + \ > + rb = gen_avr_ptr(rB(ctx->opcode)); \ > + rd = gen_avr_ptr(rD(ctx->opcode)); \ > + \ > + ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \ > + \ > + gen_helper_##op(cpu_crf[6], rd, rb, ps); \ > + \ > + tcg_temp_free_ptr(rb); \ > + tcg_temp_free_ptr(rd); \ > + tcg_temp_free_i32(ps); \ > +} > + > GEN_BCD(bcdadd) > GEN_BCD(bcdsub) > +GEN_BCD2(bcdcfn) > + > +static void gen_xpnd04_1(DisasContext *ctx) > +{ > + switch (opc4(ctx->opcode)) { > + case 0: > + break; /* bcdctsq. */ > + case 2: > + break; /* bcdcfsq. */ > + case 4: > + break; /* bcdctz. */ > + case 5: > + break; /* bcdctn. */ > + case 6: > + break; /* bcdcfz. */ > + case 7: > + gen_bcdcfn(ctx); > + break; > + case 31: > + break; /* bcdsetsgn. */ > + default: > + gen_invalid(ctx); > + break; More important change here. I think you need to leave out the cases you haven't implemented yet, and have them all cause an invalid instruction exception. That's not correct to the ISA, obviously, but neither is treating them as a no-op. Better to have the guest get a fault, so that you know something has gone wrong. > + } > +} > + > +static void gen_xpnd04_2(DisasContext *ctx) > +{ > + switch (opc4(ctx->opcode)) { > + case 0: > + break; /* bcdctsq. */ > + case 2: > + break; /* bcdcfsq. */ > + case 4: > + break; /* bcdctz. */ > + case 6: > + break; /* bcdcfz. */ > + case 7: > + gen_bcdcfn(ctx); > + break; > + case 31: > + break; /* bcdsetsgn. */ > + default: > + gen_invalid(ctx); > + break; > + } > +} > + > +GEN_VXFORM_DUAL(vsubcuw, PPC_ALTIVEC, PPC_NONE, \ > + xpnd04_1, PPC_NONE, PPC2_ISA300) > +GEN_VXFORM_DUAL(vsubsws, PPC_ALTIVEC, PPC_NONE, \ > + xpnd04_2, PPC_NONE, PPC2_ISA300) > > GEN_VXFORM_DUAL(vsububm, PPC_ALTIVEC, PPC_NONE, \ > bcdadd, PPC_NONE, PPC2_ALTIVEC_207) > @@ -1023,3 +1098,5 @@ GEN_VXFORM_DUAL(vsldoi, PPC_ALTIVEC, PPC_NONE, > #undef GEN_VXFORM_NOA > #undef GEN_VXFORM_UIMM > #undef GEN_VAFORM_PAIRED > + > +#undef GEN_BCD2 > diff --git a/target-ppc/translate/vmx-ops.inc.c b/target-ppc/translate/vmx-ops.inc.c > index cc7ed7e..637b43c 100644 > --- a/target-ppc/translate/vmx-ops.inc.c > +++ b/target-ppc/translate/vmx-ops.inc.c > @@ -122,7 +122,7 @@ GEN_VXFORM_300(vslv, 2, 29), > GEN_VXFORM(vslo, 6, 16), > GEN_VXFORM(vsro, 6, 17), > GEN_VXFORM(vaddcuw, 0, 6), > -GEN_VXFORM(vsubcuw, 0, 22), > +GEN_VXFORM_DUAL(vsubcuw, xpnd04_1, 0, 22, PPC_ALTIVEC, PPC_NONE), > GEN_VXFORM_DUAL(vaddubs, vmul10uq, 0, 8, PPC_ALTIVEC, PPC_NONE), > GEN_VXFORM_DUAL(vadduhs, vmul10euq, 0, 9, PPC_ALTIVEC, PPC_NONE), > GEN_VXFORM(vadduws, 0, 10), > @@ -134,7 +134,7 @@ GEN_VXFORM_DUAL(vsubuhs, bcdsub, 0, 25, PPC_ALTIVEC, PPC_NONE), > GEN_VXFORM(vsubuws, 0, 26), > GEN_VXFORM(vsubsbs, 0, 28), > GEN_VXFORM(vsubshs, 0, 29), > -GEN_VXFORM(vsubsws, 0, 30), > +GEN_VXFORM_DUAL(vsubsws, xpnd04_2, 0, 30, PPC_ALTIVEC, PPC_NONE), > GEN_VXFORM_207(vadduqm, 0, 4), > GEN_VXFORM_207(vaddcuq, 0, 5), > GEN_VXFORM_DUAL(vaddeuqm, vaddecuq, 30, 0xFF, PPC_NONE, PPC2_ALTIVEC_207), -- David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 819 bytes --] ^ permalink raw reply [flat|nested] 8+ messages in thread
* [Qemu-devel] [PATCH v3 2/4] target-ppc: Implement bcdctn. instruction 2016-10-31 17:34 [Qemu-devel] [PATCH v3 0/4] POWER9 TCG enablements - BCD functions part I Jose Ricardo Ziviani 2016-10-31 17:34 ` [Qemu-devel] [PATCH v3 1/4] target-ppc: Implement bcdcfn. instruction Jose Ricardo Ziviani @ 2016-10-31 17:34 ` Jose Ricardo Ziviani 2016-11-01 0:33 ` David Gibson 2016-10-31 17:34 ` [Qemu-devel] [PATCH v3 3/4] target-ppc: Implement bcdcfz. instruction Jose Ricardo Ziviani 2016-10-31 17:34 ` [Qemu-devel] [PATCH v3 4/4] target-ppc: Implement bcdctz. instruction Jose Ricardo Ziviani 3 siblings, 1 reply; 8+ messages in thread From: Jose Ricardo Ziviani @ 2016-10-31 17:34 UTC (permalink / raw) To: qemu-ppc; +Cc: qemu-devel, david, nikunj, bharata bcdctn. converts from BCD to National numeric format. National format uses a byte to represent a digit where the most significant nibble is always 0x3 and the least sign. nibbles is the digit itself. Signed-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com> --- target-ppc/helper.h | 1 + target-ppc/int_helper.c | 48 +++++++++++++++++++++++++++++++++++++ target-ppc/translate/vmx-impl.inc.c | 4 +++- 3 files changed, 52 insertions(+), 1 deletion(-) diff --git a/target-ppc/helper.h b/target-ppc/helper.h index 3b23eed..33286c6 100644 --- a/target-ppc/helper.h +++ b/target-ppc/helper.h @@ -372,6 +372,7 @@ DEF_HELPER_4(vpermxor, void, avr, avr, avr, avr) DEF_HELPER_4(bcdadd, i32, avr, avr, avr, i32) DEF_HELPER_4(bcdsub, i32, avr, avr, avr, i32) DEF_HELPER_3(bcdcfn, i32, avr, avr, i32) +DEF_HELPER_3(bcdctn, i32, avr, avr, i32) DEF_HELPER_2(xsadddp, void, env, i32) DEF_HELPER_2(xssubdp, void, env, i32) diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c index dc7a429..aaaf642 100644 --- a/target-ppc/int_helper.c +++ b/target-ppc/int_helper.c @@ -2506,6 +2506,15 @@ static uint16_t get_national_digit(ppc_avr_t *reg, int n) #endif } +static void set_national_digit(ppc_avr_t *reg, uint8_t val, int n) +{ +#if defined(HOST_WORDS_BIGENDIAN) + reg->u16[8 - n] = val; +#else + reg->u16[n] = val; +#endif +} + static int bcd_cmp_mag(ppc_avr_t *a, ppc_avr_t *b) { int i; @@ -2679,6 +2688,45 @@ uint32_t helper_bcdcfn(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps) return cr; } +uint32_t helper_bcdctn(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps) +{ + int i; + int cr = 0; + int sgnb = bcd_get_sgn(b); + int invalid = (sgnb == 0); + ppc_avr_t ret = { .u64 = { 0, 0 } }; + + int eq_flag = (b->u64[HI_IDX] == 0) && ((b->u64[LO_IDX] >> 4) == 0); + int ox_flag = (b->u64[HI_IDX] != 0) || ((b->u64[LO_IDX] >> 32) != 0); + + for (i = 1; i < 8; i++) { + set_national_digit(&ret, 0x30 + bcd_get_digit(b, i, &invalid), i); + + if (unlikely(invalid)) { + break; + } + } + set_national_digit(&ret, (sgnb == -1) ? NATIONAL_NEG : NATIONAL_PLUS, 0); + + if (!eq_flag) { + cr = (sgnb == -1) ? 1 << CRF_LT : 1 << CRF_GT; + } else { + cr = 1 << CRF_EQ; + } + + if (ox_flag) { + cr |= 1 << CRF_SO; + } + + if (unlikely(invalid)) { + cr = 1 << CRF_SO; + } + + *r = ret; + + return cr; +} + void helper_vsbox(ppc_avr_t *r, ppc_avr_t *a) { int i; diff --git a/target-ppc/translate/vmx-impl.inc.c b/target-ppc/translate/vmx-impl.inc.c index 38fea3f..301088e 100644 --- a/target-ppc/translate/vmx-impl.inc.c +++ b/target-ppc/translate/vmx-impl.inc.c @@ -971,6 +971,7 @@ static void gen_##op(DisasContext *ctx) \ GEN_BCD(bcdadd) GEN_BCD(bcdsub) GEN_BCD2(bcdcfn) +GEN_BCD2(bcdctn) static void gen_xpnd04_1(DisasContext *ctx) { @@ -982,7 +983,8 @@ static void gen_xpnd04_1(DisasContext *ctx) case 4: break; /* bcdctz. */ case 5: - break; /* bcdctn. */ + gen_bcdctn(ctx); + break; case 6: break; /* bcdcfz. */ case 7: -- 2.7.4 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [Qemu-devel] [PATCH v3 2/4] target-ppc: Implement bcdctn. instruction 2016-10-31 17:34 ` [Qemu-devel] [PATCH v3 2/4] target-ppc: Implement bcdctn. instruction Jose Ricardo Ziviani @ 2016-11-01 0:33 ` David Gibson 0 siblings, 0 replies; 8+ messages in thread From: David Gibson @ 2016-11-01 0:33 UTC (permalink / raw) To: Jose Ricardo Ziviani; +Cc: qemu-ppc, qemu-devel, nikunj, bharata [-- Attachment #1: Type: text/plain, Size: 3827 bytes --] On Mon, Oct 31, 2016 at 03:34:47PM -0200, Jose Ricardo Ziviani wrote: > bcdctn. converts from BCD to National numeric format. National format > uses a byte to represent a digit where the most significant nibble is > always 0x3 and the least sign. nibbles is the digit itself. > > Signed-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> > --- > target-ppc/helper.h | 1 + > target-ppc/int_helper.c | 48 +++++++++++++++++++++++++++++++++++++ > target-ppc/translate/vmx-impl.inc.c | 4 +++- > 3 files changed, 52 insertions(+), 1 deletion(-) > > diff --git a/target-ppc/helper.h b/target-ppc/helper.h > index 3b23eed..33286c6 100644 > --- a/target-ppc/helper.h > +++ b/target-ppc/helper.h > @@ -372,6 +372,7 @@ DEF_HELPER_4(vpermxor, void, avr, avr, avr, avr) > DEF_HELPER_4(bcdadd, i32, avr, avr, avr, i32) > DEF_HELPER_4(bcdsub, i32, avr, avr, avr, i32) > DEF_HELPER_3(bcdcfn, i32, avr, avr, i32) > +DEF_HELPER_3(bcdctn, i32, avr, avr, i32) > > DEF_HELPER_2(xsadddp, void, env, i32) > DEF_HELPER_2(xssubdp, void, env, i32) > diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c > index dc7a429..aaaf642 100644 > --- a/target-ppc/int_helper.c > +++ b/target-ppc/int_helper.c > @@ -2506,6 +2506,15 @@ static uint16_t get_national_digit(ppc_avr_t *reg, int n) > #endif > } > > +static void set_national_digit(ppc_avr_t *reg, uint8_t val, int n) > +{ > +#if defined(HOST_WORDS_BIGENDIAN) > + reg->u16[8 - n] = val; > +#else > + reg->u16[n] = val; > +#endif > +} > + > static int bcd_cmp_mag(ppc_avr_t *a, ppc_avr_t *b) > { > int i; > @@ -2679,6 +2688,45 @@ uint32_t helper_bcdcfn(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps) > return cr; > } > > +uint32_t helper_bcdctn(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps) > +{ > + int i; > + int cr = 0; > + int sgnb = bcd_get_sgn(b); > + int invalid = (sgnb == 0); > + ppc_avr_t ret = { .u64 = { 0, 0 } }; > + > + int eq_flag = (b->u64[HI_IDX] == 0) && ((b->u64[LO_IDX] >> 4) == 0); > + int ox_flag = (b->u64[HI_IDX] != 0) || ((b->u64[LO_IDX] >> 32) != 0); > + > + for (i = 1; i < 8; i++) { > + set_national_digit(&ret, 0x30 + bcd_get_digit(b, i, &invalid), i); > + > + if (unlikely(invalid)) { > + break; > + } > + } > + set_national_digit(&ret, (sgnb == -1) ? NATIONAL_NEG : NATIONAL_PLUS, 0); > + > + if (!eq_flag) { > + cr = (sgnb == -1) ? 1 << CRF_LT : 1 << CRF_GT; > + } else { > + cr = 1 << CRF_EQ; > + } > + > + if (ox_flag) { > + cr |= 1 << CRF_SO; > + } > + > + if (unlikely(invalid)) { > + cr = 1 << CRF_SO; > + } > + > + *r = ret; > + > + return cr; > +} > + > void helper_vsbox(ppc_avr_t *r, ppc_avr_t *a) > { > int i; > diff --git a/target-ppc/translate/vmx-impl.inc.c b/target-ppc/translate/vmx-impl.inc.c > index 38fea3f..301088e 100644 > --- a/target-ppc/translate/vmx-impl.inc.c > +++ b/target-ppc/translate/vmx-impl.inc.c > @@ -971,6 +971,7 @@ static void gen_##op(DisasContext *ctx) \ > GEN_BCD(bcdadd) > GEN_BCD(bcdsub) > GEN_BCD2(bcdcfn) > +GEN_BCD2(bcdctn) > > static void gen_xpnd04_1(DisasContext *ctx) > { > @@ -982,7 +983,8 @@ static void gen_xpnd04_1(DisasContext *ctx) > case 4: > break; /* bcdctz. */ > case 5: > - break; /* bcdctn. */ > + gen_bcdctn(ctx); > + break; > case 6: > break; /* bcdcfz. */ > case 7: -- David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 819 bytes --] ^ permalink raw reply [flat|nested] 8+ messages in thread
* [Qemu-devel] [PATCH v3 3/4] target-ppc: Implement bcdcfz. instruction 2016-10-31 17:34 [Qemu-devel] [PATCH v3 0/4] POWER9 TCG enablements - BCD functions part I Jose Ricardo Ziviani 2016-10-31 17:34 ` [Qemu-devel] [PATCH v3 1/4] target-ppc: Implement bcdcfn. instruction Jose Ricardo Ziviani 2016-10-31 17:34 ` [Qemu-devel] [PATCH v3 2/4] target-ppc: Implement bcdctn. instruction Jose Ricardo Ziviani @ 2016-10-31 17:34 ` Jose Ricardo Ziviani 2016-11-01 0:39 ` David Gibson 2016-10-31 17:34 ` [Qemu-devel] [PATCH v3 4/4] target-ppc: Implement bcdctz. instruction Jose Ricardo Ziviani 3 siblings, 1 reply; 8+ messages in thread From: Jose Ricardo Ziviani @ 2016-10-31 17:34 UTC (permalink / raw) To: qemu-ppc; +Cc: qemu-devel, david, nikunj, bharata bcdcfz. converts from Zoned numeric format to BCD. Zoned format uses a byte to represent a digit where the most significant nibble is 0x3 or 0xf, depending on the preferred signal. Signed-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com> --- target-ppc/helper.h | 1 + target-ppc/int_helper.c | 48 +++++++++++++++++++++++++++++++++++++ target-ppc/translate/vmx-impl.inc.c | 7 ++++-- 3 files changed, 54 insertions(+), 2 deletions(-) diff --git a/target-ppc/helper.h b/target-ppc/helper.h index 33286c6..8546bb9 100644 --- a/target-ppc/helper.h +++ b/target-ppc/helper.h @@ -373,6 +373,7 @@ DEF_HELPER_4(bcdadd, i32, avr, avr, avr, i32) DEF_HELPER_4(bcdsub, i32, avr, avr, avr, i32) DEF_HELPER_3(bcdcfn, i32, avr, avr, i32) DEF_HELPER_3(bcdctn, i32, avr, avr, i32) +DEF_HELPER_3(bcdcfz, i32, avr, avr, i32) DEF_HELPER_2(xsadddp, void, env, i32) DEF_HELPER_2(xssubdp, void, env, i32) diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c index aaaf642..6581887 100644 --- a/target-ppc/int_helper.c +++ b/target-ppc/int_helper.c @@ -2727,6 +2727,54 @@ uint32_t helper_bcdctn(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps) return cr; } +uint32_t helper_bcdcfz(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps) +{ + int i; + int j; + int cr = 0; + int invalid = 0; + int neq_flag = 0; + int zone_digit = 0; + int zone_lead = ps ? 0xF : 0x3; + int digit = 0; + ppc_avr_t ret = { .u64 = { 0, 0 } }; + int sgnb = b->u8[BCD_DIG_BYTE(0)] >> 4; + + if (unlikely((sgnb < 0xA) && ps)) { + invalid = 1; + } + + for (i = 0, j = 1; i < 31; i += 2, j++) { + zone_digit = (i) ? b->u8[BCD_DIG_BYTE(i)] >> 4 : zone_lead; + digit = b->u8[BCD_DIG_BYTE(i)] & 0xF; + + if (unlikely(zone_digit != zone_lead || digit > 0x9)) { + invalid = 1; + break; + } + + neq_flag += (digit != 0); + bcd_put_digit(&ret, digit, j); + } + + if ((ps && (sgnb == 0xB || sgnb == 0xD)) || + (!ps && (sgnb & 0x4))) { + bcd_put_digit(&ret, BCD_NEG_PREF, 0); + cr = (neq_flag) ? 1 << CRF_LT : 1 << CRF_EQ; + } else { + bcd_put_digit(&ret, BCD_PLUS_PREF_1, 0); + cr = (neq_flag) ? 1 << CRF_GT : 1 << CRF_EQ; + } + + if (unlikely(invalid)) { + cr = 1 << CRF_SO; + } + + *r = ret; + + return cr; +} + void helper_vsbox(ppc_avr_t *r, ppc_avr_t *a) { int i; diff --git a/target-ppc/translate/vmx-impl.inc.c b/target-ppc/translate/vmx-impl.inc.c index 301088e..ecf0e54 100644 --- a/target-ppc/translate/vmx-impl.inc.c +++ b/target-ppc/translate/vmx-impl.inc.c @@ -972,6 +972,7 @@ GEN_BCD(bcdadd) GEN_BCD(bcdsub) GEN_BCD2(bcdcfn) GEN_BCD2(bcdctn) +GEN_BCD2(bcdcfz) static void gen_xpnd04_1(DisasContext *ctx) { @@ -986,7 +987,8 @@ static void gen_xpnd04_1(DisasContext *ctx) gen_bcdctn(ctx); break; case 6: - break; /* bcdcfz. */ + gen_bcdcfz(ctx); + break; case 7: gen_bcdcfn(ctx); break; @@ -1008,7 +1010,8 @@ static void gen_xpnd04_2(DisasContext *ctx) case 4: break; /* bcdctz. */ case 6: - break; /* bcdcfz. */ + gen_bcdcfz(ctx); + break; case 7: gen_bcdcfn(ctx); break; -- 2.7.4 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [Qemu-devel] [PATCH v3 3/4] target-ppc: Implement bcdcfz. instruction 2016-10-31 17:34 ` [Qemu-devel] [PATCH v3 3/4] target-ppc: Implement bcdcfz. instruction Jose Ricardo Ziviani @ 2016-11-01 0:39 ` David Gibson 0 siblings, 0 replies; 8+ messages in thread From: David Gibson @ 2016-11-01 0:39 UTC (permalink / raw) To: Jose Ricardo Ziviani; +Cc: qemu-ppc, qemu-devel, nikunj, bharata [-- Attachment #1: Type: text/plain, Size: 4389 bytes --] On Mon, Oct 31, 2016 at 03:34:48PM -0200, Jose Ricardo Ziviani wrote: > bcdcfz. converts from Zoned numeric format to BCD. Zoned format uses > a byte to represent a digit where the most significant nibble is 0x3 > or 0xf, depending on the preferred signal. > > Signed-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com> > --- > target-ppc/helper.h | 1 + > target-ppc/int_helper.c | 48 +++++++++++++++++++++++++++++++++++++ > target-ppc/translate/vmx-impl.inc.c | 7 ++++-- > 3 files changed, 54 insertions(+), 2 deletions(-) > > diff --git a/target-ppc/helper.h b/target-ppc/helper.h > index 33286c6..8546bb9 100644 > --- a/target-ppc/helper.h > +++ b/target-ppc/helper.h > @@ -373,6 +373,7 @@ DEF_HELPER_4(bcdadd, i32, avr, avr, avr, i32) > DEF_HELPER_4(bcdsub, i32, avr, avr, avr, i32) > DEF_HELPER_3(bcdcfn, i32, avr, avr, i32) > DEF_HELPER_3(bcdctn, i32, avr, avr, i32) > +DEF_HELPER_3(bcdcfz, i32, avr, avr, i32) > > DEF_HELPER_2(xsadddp, void, env, i32) > DEF_HELPER_2(xssubdp, void, env, i32) > diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c > index aaaf642..6581887 100644 > --- a/target-ppc/int_helper.c > +++ b/target-ppc/int_helper.c > @@ -2727,6 +2727,54 @@ uint32_t helper_bcdctn(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps) > return cr; > } > > +uint32_t helper_bcdcfz(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps) > +{ > + int i; > + int j; > + int cr = 0; > + int invalid = 0; > + int neq_flag = 0; > + int zone_digit = 0; > + int zone_lead = ps ? 0xF : 0x3; > + int digit = 0; > + ppc_avr_t ret = { .u64 = { 0, 0 } }; > + int sgnb = b->u8[BCD_DIG_BYTE(0)] >> 4; > + > + if (unlikely((sgnb < 0xA) && ps)) { > + invalid = 1; > + } > + > + for (i = 0, j = 1; i < 31; i += 2, j++) { > + zone_digit = (i) ? b->u8[BCD_DIG_BYTE(i)] >> 4 : zone_lead; > + digit = b->u8[BCD_DIG_BYTE(i)] & 0xF; > + > + if (unlikely(zone_digit != zone_lead || digit > 0x9)) { > + invalid = 1; > + break; > + } > + > + neq_flag += (digit != 0); > + bcd_put_digit(&ret, digit, j); > + } > + > + if ((ps && (sgnb == 0xB || sgnb == 0xD)) || > + (!ps && (sgnb & 0x4))) { > + bcd_put_digit(&ret, BCD_NEG_PREF, 0); > + cr = (neq_flag) ? 1 << CRF_LT : 1 << CRF_EQ; > + } else { > + bcd_put_digit(&ret, BCD_PLUS_PREF_1, 0); > + cr = (neq_flag) ? 1 << CRF_GT : 1 << CRF_EQ; > + } As with bcdcfn., you can test for zero on the final result more easily than building up the neq_flag as you go. Actually.. rather than having a bcd_is_zero() as I suggested on the other patch, you could have a helper that returns all the EQ, LT, GT flags for a given BCD input. You should be able to use that in all these instructions (except for the invalid case, obviously) - on the output value for bcdcfn. and bcdcfz. and on the input value for bcdctn. and bcdctz. > + > + if (unlikely(invalid)) { > + cr = 1 << CRF_SO; > + } > + > + *r = ret; > + > + return cr; > +} > + > void helper_vsbox(ppc_avr_t *r, ppc_avr_t *a) > { > int i; > diff --git a/target-ppc/translate/vmx-impl.inc.c b/target-ppc/translate/vmx-impl.inc.c > index 301088e..ecf0e54 100644 > --- a/target-ppc/translate/vmx-impl.inc.c > +++ b/target-ppc/translate/vmx-impl.inc.c > @@ -972,6 +972,7 @@ GEN_BCD(bcdadd) > GEN_BCD(bcdsub) > GEN_BCD2(bcdcfn) > GEN_BCD2(bcdctn) > +GEN_BCD2(bcdcfz) > > static void gen_xpnd04_1(DisasContext *ctx) > { > @@ -986,7 +987,8 @@ static void gen_xpnd04_1(DisasContext *ctx) > gen_bcdctn(ctx); > break; > case 6: > - break; /* bcdcfz. */ > + gen_bcdcfz(ctx); > + break; > case 7: > gen_bcdcfn(ctx); > break; > @@ -1008,7 +1010,8 @@ static void gen_xpnd04_2(DisasContext *ctx) > case 4: > break; /* bcdctz. */ > case 6: > - break; /* bcdcfz. */ > + gen_bcdcfz(ctx); > + break; > case 7: > gen_bcdcfn(ctx); > break; -- David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 819 bytes --] ^ permalink raw reply [flat|nested] 8+ messages in thread
* [Qemu-devel] [PATCH v3 4/4] target-ppc: Implement bcdctz. instruction 2016-10-31 17:34 [Qemu-devel] [PATCH v3 0/4] POWER9 TCG enablements - BCD functions part I Jose Ricardo Ziviani ` (2 preceding siblings ...) 2016-10-31 17:34 ` [Qemu-devel] [PATCH v3 3/4] target-ppc: Implement bcdcfz. instruction Jose Ricardo Ziviani @ 2016-10-31 17:34 ` Jose Ricardo Ziviani 3 siblings, 0 replies; 8+ messages in thread From: Jose Ricardo Ziviani @ 2016-10-31 17:34 UTC (permalink / raw) To: qemu-ppc; +Cc: qemu-devel, david, nikunj, bharata bcdctz. converts from BCD to Zoned numeric format. Zoned format uses a byte to represent a digit where the most significant nibble is 0x3 or 0xf, depending on the preferred signal. Signed-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com> --- target-ppc/helper.h | 1 + target-ppc/int_helper.c | 49 +++++++++++++++++++++++++++++++++++++ target-ppc/translate/vmx-impl.inc.c | 7 ++++-- 3 files changed, 55 insertions(+), 2 deletions(-) diff --git a/target-ppc/helper.h b/target-ppc/helper.h index 8546bb9..5412da5 100644 --- a/target-ppc/helper.h +++ b/target-ppc/helper.h @@ -374,6 +374,7 @@ DEF_HELPER_4(bcdsub, i32, avr, avr, avr, i32) DEF_HELPER_3(bcdcfn, i32, avr, avr, i32) DEF_HELPER_3(bcdctn, i32, avr, avr, i32) DEF_HELPER_3(bcdcfz, i32, avr, avr, i32) +DEF_HELPER_3(bcdctz, i32, avr, avr, i32) DEF_HELPER_2(xsadddp, void, env, i32) DEF_HELPER_2(xssubdp, void, env, i32) diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c index 6581887..2494f1f 100644 --- a/target-ppc/int_helper.c +++ b/target-ppc/int_helper.c @@ -2775,6 +2775,55 @@ uint32_t helper_bcdcfz(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps) return cr; } +uint32_t helper_bcdctz(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps) +{ + int i; + int j; + int cr = 0; + uint8_t digit = 0; + int sgnb = bcd_get_sgn(b); + int zone_lead = (ps) ? 0xF0 : 0x30; + int invalid = (sgnb == 0); + ppc_avr_t ret = { .u64 = { 0, 0 } }; + + int eq_flag = (b->u64[HI_IDX] == 0) && ((b->u64[LO_IDX] >> 4) == 0); + int ox_flag = ((b->u64[HI_IDX] >> 4) != 0); + + for (i = 0, j = 1; i < 32; i += 2, j++) { + digit = bcd_get_digit(b, j, &invalid); + + if (unlikely(invalid)) { + break; + } + + ret.u8[BCD_DIG_BYTE(i)] = zone_lead + digit; + } + + if (ps) { + bcd_put_digit(&ret, (sgnb == 1) ? 0xC : 0xD, 1); + } else { + bcd_put_digit(&ret, (sgnb == 1) ? 0x3 : 0x7, 1); + } + + if (!eq_flag) { + cr = (sgnb == 1) ? 1 << CRF_GT : 1 << CRF_LT; + } else { + cr = 1 << CRF_EQ; + } + + if (ox_flag) { + cr |= 1 << CRF_SO; + } + + if (unlikely(invalid)) { + cr = 1 << CRF_SO; + } + + *r = ret; + + return cr; +} + void helper_vsbox(ppc_avr_t *r, ppc_avr_t *a) { int i; diff --git a/target-ppc/translate/vmx-impl.inc.c b/target-ppc/translate/vmx-impl.inc.c index ecf0e54..d88d685 100644 --- a/target-ppc/translate/vmx-impl.inc.c +++ b/target-ppc/translate/vmx-impl.inc.c @@ -973,6 +973,7 @@ GEN_BCD(bcdsub) GEN_BCD2(bcdcfn) GEN_BCD2(bcdctn) GEN_BCD2(bcdcfz) +GEN_BCD2(bcdctz) static void gen_xpnd04_1(DisasContext *ctx) { @@ -982,7 +983,8 @@ static void gen_xpnd04_1(DisasContext *ctx) case 2: break; /* bcdcfsq. */ case 4: - break; /* bcdctz. */ + gen_bcdctz(ctx); + break; case 5: gen_bcdctn(ctx); break; @@ -1008,7 +1010,8 @@ static void gen_xpnd04_2(DisasContext *ctx) case 2: break; /* bcdcfsq. */ case 4: - break; /* bcdctz. */ + gen_bcdctz(ctx); + break; case 6: gen_bcdcfz(ctx); break; -- 2.7.4 ^ permalink raw reply related [flat|nested] 8+ messages in thread
end of thread, other threads:[~2016-11-01 0:41 UTC | newest] Thread overview: 8+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2016-10-31 17:34 [Qemu-devel] [PATCH v3 0/4] POWER9 TCG enablements - BCD functions part I Jose Ricardo Ziviani 2016-10-31 17:34 ` [Qemu-devel] [PATCH v3 1/4] target-ppc: Implement bcdcfn. instruction Jose Ricardo Ziviani 2016-11-01 0:30 ` David Gibson 2016-10-31 17:34 ` [Qemu-devel] [PATCH v3 2/4] target-ppc: Implement bcdctn. instruction Jose Ricardo Ziviani 2016-11-01 0:33 ` David Gibson 2016-10-31 17:34 ` [Qemu-devel] [PATCH v3 3/4] target-ppc: Implement bcdcfz. instruction Jose Ricardo Ziviani 2016-11-01 0:39 ` David Gibson 2016-10-31 17:34 ` [Qemu-devel] [PATCH v3 4/4] target-ppc: Implement bcdctz. instruction Jose Ricardo Ziviani
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