[Qemu-devel] [PULL v2 for-2.8 00/15] target-sparc updates

[Qemu-devel] [PULL v2 for-2.8 00/15] target-sparc updates

[Richard Henderson]

V2 with a workaround for win32 namespace pollution.  Whee!
Only resending patch 09/15, wherein the change lies.


r~


The following changes since commit 4178c782f85530d261058abdccc734aa9b7c89ca:

  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20161028' into staging (2016-10-31 11:12:02 +0000)

are available in the git repository at:

  git://github.com/rth7680/qemu.git tags/pull-sparc-20161031-2

for you to fetch changes up to 5a7267b6a9e94c264ca77a7ca5a239e70dac81da:

  target-sparc: Use tcg_gen_atomic_cmpxchg_tl (2016-10-31 14:46:48 -0600)

----------------------------------------------------------------
target-sparc updates for atomics and alignment

----------------------------------------------------------------
Richard Henderson (15):
      target-sparc: Use overalignment flags for twinx and block asis
      target-sparc: Introduce cpu_raise_exception_ra
      target-sparc: Add MMU_PHYS_IDX
      target-sparc: Use MMU_PHYS_IDX for bypass asis
      target-sparc: Handle more twinx asis
      target-sparc: Implement swap_asi inline
      target-sparc: Implement ldstub_asi inline
      target-sparc: Implement cas_asi/casx_asi inline
      target-sparc: Implement BCOPY/BFILL inline
      target-sparc: Remove asi helper code handled inline
      target-sparc: Implement ldqf and stqf inline
      target-sparc: Allow 4-byte alignment on fp mem ops
      target-sparc: Remove MMU_MODE*_SUFFIX
      target-sparc: Use tcg_gen_atomic_xchg_tl
      target-sparc: Use tcg_gen_atomic_cmpxchg_tl

 target-sparc/cpu.h         |   34 +-
 target-sparc/helper.c      |   52 +--
 target-sparc/helper.h      |    7 -
 target-sparc/ldst_helper.c | 1021 ++++++++------------------------------------
 target-sparc/mmu_helper.c  |   47 +-
 target-sparc/translate.c   |  434 ++++++++++++-------
 target-sparc/win_helper.c  |   37 +-
 7 files changed, 540 insertions(+), 1092 deletions(-)

[Qemu-devel] [PULL v2 for-2.8 09/15] target-sparc: Implement BCOPY/BFILL inline

[Richard Henderson]

Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 target-sparc/translate.c | 63 ++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 63 insertions(+)

diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 0fb361a..7950458 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -2036,6 +2036,8 @@ typedef enum {
     GET_ASI_DTWINX,
     GET_ASI_BLOCK,
     GET_ASI_SHORT,
+    GET_ASI_BCOPY,
+    GET_ASI_BFILL,
 } ASIType;
 
 typedef struct {
@@ -2077,6 +2079,14 @@ static DisasASI get_asi(DisasContext *dc, int insn, TCGMemOp memop)
             mem_idx = MMU_PHYS_IDX;
             type = GET_ASI_DIRECT;
             break;
+        case ASI_M_BCOPY: /* Block copy, sta access */
+            mem_idx = MMU_KERNEL_IDX;
+            type = GET_ASI_BCOPY;
+            break;
+        case ASI_M_BFILL: /* Block fill, stda access */
+            mem_idx = MMU_KERNEL_IDX;
+            type = GET_ASI_BFILL;
+            break;
         }
     } else {
         gen_exception(dc, TT_PRIV_INSN);
@@ -2294,6 +2304,38 @@ static void gen_st_asi(DisasContext *dc, TCGv src, TCGv addr,
         gen_address_mask(dc, addr);
         tcg_gen_qemu_st_tl(src, addr, da.mem_idx, da.memop);
         break;
+#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
+    case GET_ASI_BCOPY:
+        /* Copy 32 bytes from the address in SRC to ADDR.  */
+        /* ??? The original qemu code suggests 4-byte alignment, dropping
+           the low bits, but the only place I can see this used is in the
+           Linux kernel with 32 byte alignment, which would make more sense
+           as a cacheline-style operation.  */
+        {
+            TCGv saddr = tcg_temp_new();
+            TCGv daddr = tcg_temp_new();
+            TCGv four = tcg_const_tl(4);
+            TCGv_i32 tmp = tcg_temp_new_i32();
+            int i;
+
+            tcg_gen_andi_tl(saddr, src, -4);
+            tcg_gen_andi_tl(daddr, addr, -4);
+            for (i = 0; i < 32; i += 4) {
+                /* Since the loads and stores are paired, allow the
+                   copy to happen in the host endianness.  */
+                tcg_gen_qemu_ld_i32(tmp, saddr, da.mem_idx, MO_UL);
+                tcg_gen_qemu_st_i32(tmp, daddr, da.mem_idx, MO_UL);
+                tcg_gen_add_tl(saddr, saddr, four);
+                tcg_gen_add_tl(daddr, daddr, four);
+            }
+
+            tcg_temp_free(saddr);
+            tcg_temp_free(daddr);
+            tcg_temp_free(four);
+            tcg_temp_free_i32(tmp);
+        }
+        break;
+#endif
     default:
         {
             TCGv_i32 r_asi = tcg_const_i32(da.asi);
@@ -2766,6 +2808,27 @@ static void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr,
         gen_address_mask(dc, addr);
         tcg_gen_qemu_st_i64(t64, addr, da.mem_idx, da.memop);
         break;
+    case GET_ASI_BFILL:
+        /* Store 32 bytes of T64 to ADDR.  */
+        /* ??? The original qemu code suggests 8-byte alignment, dropping
+           the low bits, but the only place I can see this used is in the
+           Linux kernel with 32 byte alignment, which would make more sense
+           as a cacheline-style operation.  */
+        {
+            TCGv d_addr = tcg_temp_new();
+            TCGv eight = tcg_const_tl(8);
+            int i;
+
+            tcg_gen_andi_tl(d_addr, addr, -8);
+            for (i = 0; i < 32; i += 8) {
+                tcg_gen_qemu_st_i64(t64, d_addr, da.mem_idx, da.memop);
+                tcg_gen_add_tl(d_addr, d_addr, eight);
+            }
+
+            tcg_temp_free(d_addr);
+            tcg_temp_free(eight);
+        }
+        break;
     default:
         {
             TCGv_i32 r_asi = tcg_const_i32(da.asi);
-- 
2.7.4

Re: [Qemu-devel] [PULL v2 for-2.8 00/15] target-sparc updates

[Peter Maydell]

On 31 October 2016 at 20:50, Richard Henderson <rth@twiddle.net> wrote:
> V2 with a workaround for win32 namespace pollution.  Whee!
> Only resending patch 09/15, wherein the change lies.
>
>
> r~
>
>
> The following changes since commit 4178c782f85530d261058abdccc734aa9b7c89ca:
>
>   Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20161028' into staging (2016-10-31 11:12:02 +0000)
>
> are available in the git repository at:
>
>   git://github.com/rth7680/qemu.git tags/pull-sparc-20161031-2
>
> for you to fetch changes up to 5a7267b6a9e94c264ca77a7ca5a239e70dac81da:
>
>   target-sparc: Use tcg_gen_atomic_cmpxchg_tl (2016-10-31 14:46:48 -0600)
>
> ----------------------------------------------------------------
> target-sparc updates for atomics and alignment
>

Applied, thanks.

-- PMM