From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57941) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c1bOh-0006b7-PG for qemu-devel@nongnu.org; Tue, 01 Nov 2016 11:54:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1c1bOd-0004A3-Ju for qemu-devel@nongnu.org; Tue, 01 Nov 2016 11:54:47 -0400 Received: from mail-sn1nam01on0063.outbound.protection.outlook.com ([104.47.32.63]:39824 helo=NAM01-SN1-obe.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1c1bOd-00049v-Cv for qemu-devel@nongnu.org; Tue, 01 Nov 2016 11:54:43 -0400 From: Brijesh Singh Date: Tue, 1 Nov 2016 11:54:34 -0400 Message-ID: <147801567435.18237.5589304835385835946.stgit@brijesh-build-machine> In-Reply-To: <147801550845.18237.12915616525154608660.stgit@brijesh-build-machine> References: <147801550845.18237.12915616525154608660.stgit@brijesh-build-machine> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Subject: [Qemu-devel] [RFC PATCH v3 16/18] target-i386: add cpuid Fn8000_001f List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Thomas.Lendacky@amd.com, ehabkost@redhat.com, crosthwaite.peter@gmail.com, armbru@redhat.com, mst@redhat.com, p.fedin@samsung.com, qemu-devel@nongnu.org, lcapitulino@redhat.com, pbonzini@redhat.com, rth@twiddle.net Cc: brijesh.ksingh@gmail.com Fn8000_001f cpuid provides the memory encryption (aka C-bit) location in a page table for the SEV-enabled guest. Signed-off-by: Brijesh Singh --- target-i386/cpu.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target-i386/cpu.c b/target-i386/cpu.c index 83998a8..9dc7b4f 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -34,6 +34,7 @@ #include "qapi-visit.h" #include "qapi/visitor.h" #include "sysemu/arch_init.h" +#include "sysemu/sev.h" #if defined(CONFIG_KVM) #include @@ -2733,6 +2734,11 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, *edx = 0; } break; + case 0x8000001F: + if (sev_enabled()) { + host_cpuid(index, 0, eax, ebx, ecx, edx); + } + break; case 0xC0000000: *eax = env->cpuid_xlevel2; *ebx = 0;