From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33074) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c2Igq-0003RM-KW for qemu-devel@nongnu.org; Thu, 03 Nov 2016 10:08:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1c2Igl-0002ZE-LW for qemu-devel@nongnu.org; Thu, 03 Nov 2016 10:08:24 -0400 Received: from mout.kundenserver.de ([217.72.192.75]:56926) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1c2Igl-0002Ys-CM for qemu-devel@nongnu.org; Thu, 03 Nov 2016 10:08:19 -0400 From: Laurent Vivier Date: Thu, 3 Nov 2016 15:07:48 +0100 Message-Id: <1478182068-14082-1-git-send-email-laurent@vivier.eu> Subject: [Qemu-devel] [PATCH v2] target-sh4: add atomic tas List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Aurelien Jarno Cc: qemu-devel@nongnu.org, Richard Henderson , John Paul Adrian Glaubitz , Paolo Bonzini , Laurent Vivier Implement real atomic tas: When (Rn) = 0, 1 -> T Otherwise, 0 -> T In both cases, 1 -> MSB of (Rn) using atomic_fetch_or_i32() and setcondi_i32(). Tested with image from: http://wiki.qemu.org/download/sh-test-0.2.tar.bz2 This image contains a "tas_test" that runs without error with this change. Signed-off-by: Laurent Vivier --- v2: - don't use helper but atomic_fetch_or_i32 Thank you Paolo! target-sh4/translate.c | 19 ++++++++----------- 1 file changed, 8 insertions(+), 11 deletions(-) diff --git a/target-sh4/translate.c b/target-sh4/translate.c index c89a147..1b83d59 100644 --- a/target-sh4/translate.c +++ b/target-sh4/translate.c @@ -1640,18 +1640,15 @@ static void _decode_opc(DisasContext * ctx) tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 16); return; case 0x401b: /* tas.b @Rn */ - { - TCGv addr, val; - addr = tcg_temp_local_new(); - tcg_gen_mov_i32(addr, REG(B11_8)); - val = tcg_temp_local_new(); - tcg_gen_qemu_ld_i32(val, addr, ctx->memidx, MO_UB); + { + TCGv val = tcg_temp_new(); + TCGv msb = tcg_const_i32(0x80); + tcg_gen_atomic_fetch_or_i32(val, REG(B11_8), msb, + ctx->memidx, MO_UB); + tcg_temp_free(msb); tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_sr_t, val, 0); - tcg_gen_ori_i32(val, val, 0x80); - tcg_gen_qemu_st_i32(val, addr, ctx->memidx, MO_UB); - tcg_temp_free(val); - tcg_temp_free(addr); - } + tcg_temp_free(val); + } return; case 0xf00d: /* fsts FPUL,FRn - FPSCR: Nothing */ CHECK_FPU_ENABLED -- 2.7.4