* [Qemu-devel] [PATCH 0/5] ARM BE8/BE32 big-endian system-mode fixes (semihosting, gdbstub)
@ 2016-11-03 17:30 Julian Brown
2016-11-03 17:30 ` [Qemu-devel] [PATCH 1/5] ARM BE8/BE32 semihosting and gdbstub support Julian Brown
` (6 more replies)
0 siblings, 7 replies; 28+ messages in thread
From: Julian Brown @ 2016-11-03 17:30 UTC (permalink / raw)
To: qemu-devel
This patch series contains a few fixes for ARM big-endian system mode
that appear beneficial for our use case of running bare-metal code with
semihosting (for toolchain testing), and running code via the built-in
gdbstub (for debugger testing). The patches are mostly relevant to BE32
mode, but contain some BE8 mode fixes also.
I haven't been following QEMU development terribly closely, so apologies
in advance if these patches are moving along the wrong trajectory! I
hope they're useful as a starting point though, at least.
I have tested (modulo formatting cleanups suggested by checkpatch.pl)
these patches against GCC (in particular ARMv7 LE, BE8 multilibs and
ARMv5te LE, BE32 multilibs), and GDB, with Mentor's internal test
infrastructure (though I needed some other minor local patches to make
QEMU work better with that). Let me know if there's other testing I
should do.
Thank you,
Julian
Julian Brown (5):
ARM BE8/BE32 semihosting and gdbstub support.
Fix Thumb-1 BE32 execution and disassembly.
Fix arm_semi_flen_cb for BE32 system mode.
ARM BE32 watchpoint fix.
Fix typo in arm_cpu_do_interrupt_aarch32.
disas/arm.c | 46 ++++++++++---
exec.c | 13 ++++
hw/arm/boot.c | 16 ++++-
include/disas/bfd.h | 1 +
include/exec/softmmu-arm-semi.h | 148 ++++++++++++++++++++++++++++++++++++++++
target-arm/arm-semi.c | 12 +++-
target-arm/arm_ldst.h | 10 ++-
target-arm/cpu.c | 53 ++++++++++++++
target-arm/gdbstub.c | 42 ++++++++++++
target-arm/helper.c | 2 +-
10 files changed, 328 insertions(+), 15 deletions(-)
create mode 100644 include/exec/softmmu-arm-semi.h
--
1.9.1
^ permalink raw reply [flat|nested] 28+ messages in thread
* [Qemu-devel] [PATCH 1/5] ARM BE8/BE32 semihosting and gdbstub support.
2016-11-03 17:30 [Qemu-devel] [PATCH 0/5] ARM BE8/BE32 big-endian system-mode fixes (semihosting, gdbstub) Julian Brown
@ 2016-11-03 17:30 ` Julian Brown
2016-11-03 22:23 ` Peter Maydell
2016-11-03 17:30 ` [Qemu-devel] [PATCH 2/5] Fix Thumb-1 BE32 execution and disassembly Julian Brown
` (5 subsequent siblings)
6 siblings, 1 reply; 28+ messages in thread
From: Julian Brown @ 2016-11-03 17:30 UTC (permalink / raw)
To: qemu-devel
This patch improves support for semihosting and debugging with the
in-built gdbstub for ARM system-mode emulation in big-endian mode (either
BE8 or BE32), after the fairly recent changes to allow a single QEMU
binary to deal with each of LE, BE8 and BE32 modes in one. It's only
currently good for little-endian host systems. The relevant use case
is using QEMU as a "bare metal" instruction-set simulator, e.g. for
toolchain testing.
For semihosting, the softmmu-semi.h file is overridden with an
ARM-specific version that knows about byte-swapping target memory into
host order -- including that which has been byte-swapped at load time
for BE32 mode.
For the gdbstub, we'd like to be able to invoke QEMU from GDB like:
(gdb) target remote | arm-qemu-system -cpu=foo [options] /dev/null
(gdb) load
(gdb) ...
which unfortunately bypasses the probing of the loaded ELF file (since
it's just /dev/null) to determine whether to use BE8/BE32 mode. So,
I added some "virtual" CPUs to set the endian type instead (arm926-be,
cortex-a15-be for BE32/BE8 mode respectively), from the reset value
of the SCTLR. This is kind of like having a configuration input to the
CPU on some hardware board to select endianness, which is a completely
legitimate thing to have, even if the implementation as-is is not really
ideal from a software-engineering standpoint. It suffices for our current
use-case though.
Signed-off-by: Julian Brown <julian@codesourcery.com>
---
hw/arm/boot.c | 16 ++++-
include/exec/softmmu-arm-semi.h | 148 ++++++++++++++++++++++++++++++++++++++++
target-arm/arm-semi.c | 2 +-
target-arm/cpu.c | 49 +++++++++++++
target-arm/gdbstub.c | 42 ++++++++++++
5 files changed, 255 insertions(+), 2 deletions(-)
create mode 100644 include/exec/softmmu-arm-semi.h
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index 942416d..644fdaf 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -894,7 +894,21 @@ static void arm_load_kernel_notify(Notifier *notifier, void *data)
entry = info->loader_start + kernel_load_offset;
kernel_size = load_image_targphys(info->kernel_filename, entry,
info->ram_size - kernel_load_offset);
- is_linux = 1;
+ if (kernel_size > 0) {
+ is_linux = 1;
+ } else {
+ /* We've been launched with a kernel of /dev/null or similar.
+ * Infer endianness from the reset value of the SCTLR for this
+ * CPU/board (FIXME: a way of configuring this more nicely).
+ */
+ if (!arm_feature(&cpu->env, ARM_FEATURE_V7) &&
+ (cpu->reset_sctlr & SCTLR_B) != 0)
+ info->endianness = ARM_ENDIANNESS_BE32;
+ else if ((cpu->reset_sctlr & SCTLR_EE) != 0)
+ info->endianness = ARM_ENDIANNESS_BE8;
+ else
+ info->endianness = ARM_ENDIANNESS_LE;
+ }
}
if (kernel_size < 0) {
fprintf(stderr, "qemu: could not load kernel '%s'\n",
diff --git a/include/exec/softmmu-arm-semi.h b/include/exec/softmmu-arm-semi.h
new file mode 100644
index 0000000..e9ddb21
--- /dev/null
+++ b/include/exec/softmmu-arm-semi.h
@@ -0,0 +1,148 @@
+/*
+ * Helper routines to provide target memory access for ARM semihosting
+ * syscalls in system emulation mode.
+ *
+ * Copyright (c) 2007 CodeSourcery, (c) 2016 Mentor Graphics
+ *
+ * This code is licensed under the GPL
+ */
+
+#ifndef SOFTMMU_ARM_SEMI_H
+#define SOFTMMU_ARM_SEMI_H 1
+
+/* In BE32 system mode, the CPU-specific memory_rw_debug method will arrange to
+ * perform byteswapping on the target memory, so that it appears to the host as
+ * it appears to the emulated CPU. Memory is read verbatim in BE8 mode. (In
+ * other words, this function arranges so that BUF has the same format in both
+ * BE8 and BE32 system mode.)
+ */
+
+static inline int armsemi_memory_rw_debug(CPUState *cpu, target_ulong addr,
+ uint8_t *buf, int len, bool is_write)
+{
+ CPUClass *cc = CPU_GET_CLASS(cpu);
+
+ if (cc->memory_rw_debug) {
+ return cc->memory_rw_debug(cpu, addr, buf, len, is_write);
+ }
+ return cpu_memory_rw_debug(cpu, addr, buf, len, is_write);
+}
+
+/* In big-endian mode (either BE8 or BE32), values larger than a byte will be
+ * transferred to/from memory in big-endian format. Assuming we're on a
+ * little-endian host machine, such values will need to be byteswapped before
+ * and after the host processes them.
+ *
+ * This means that byteswapping will occur *twice* in BE32 mode for
+ * halfword/word reads/writes.
+ */
+
+static inline bool arm_bswap_needed(CPUARMState *env)
+{
+#ifdef HOST_WORDS_BIGENDIAN
+#error HOST_WORDS_BIGENDIAN is not supported for ARM semihosting at the moment.
+#else
+ return arm_sctlr_b(env) || (env->uncached_cpsr & CPSR_E) != 0;
+#endif
+}
+
+static inline uint64_t softmmu_tget64(CPUArchState *env, target_ulong addr)
+{
+ uint64_t val;
+
+ armsemi_memory_rw_debug(ENV_GET_CPU(env), addr, (uint8_t *)&val, 8, 0);
+ if (arm_bswap_needed(env)) {
+ return bswap64(val);
+ } else {
+ return val;
+ }
+}
+
+static inline uint32_t softmmu_tget32(CPUArchState *env, target_ulong addr)
+{
+ uint32_t val;
+
+ armsemi_memory_rw_debug(ENV_GET_CPU(env), addr, (uint8_t *)&val, 4, 0);
+ if (arm_bswap_needed(env)) {
+ return bswap32(val);
+ } else {
+ return val;
+ }
+}
+
+static inline uint32_t softmmu_tget8(CPUArchState *env, target_ulong addr)
+{
+ uint8_t val;
+ armsemi_memory_rw_debug(ENV_GET_CPU(env), addr, &val, 1, 0);
+ return val;
+}
+
+#define get_user_u64(arg, p) ({ arg = softmmu_tget64(env, p); 0; })
+#define get_user_u32(arg, p) ({ arg = softmmu_tget32(env, p) ; 0; })
+#define get_user_u8(arg, p) ({ arg = softmmu_tget8(env, p) ; 0; })
+#define get_user_ual(arg, p) get_user_u32(arg, p)
+
+static inline void softmmu_tput64(CPUArchState *env,
+ target_ulong addr, uint64_t val)
+{
+ if (arm_bswap_needed(env)) {
+ val = bswap64(val);
+ }
+ cpu_memory_rw_debug(ENV_GET_CPU(env), addr, (uint8_t *)&val, 8, 1);
+}
+
+static inline void softmmu_tput32(CPUArchState *env,
+ target_ulong addr, uint32_t val)
+{
+ if (arm_bswap_needed(env)) {
+ val = bswap32(val);
+ }
+ armsemi_memory_rw_debug(ENV_GET_CPU(env), addr, (uint8_t *)&val, 4, 1);
+}
+#define put_user_u64(arg, p) ({ softmmu_tput64(env, p, arg) ; 0; })
+#define put_user_u32(arg, p) ({ softmmu_tput32(env, p, arg) ; 0; })
+#define put_user_ual(arg, p) put_user_u32(arg, p)
+
+static void *softmmu_lock_user(CPUArchState *env,
+ target_ulong addr, target_ulong len, int copy)
+{
+ uint8_t *p;
+ /* TODO: Make this something that isn't fixed size. */
+ p = malloc(len);
+ if (p && copy) {
+ armsemi_memory_rw_debug(ENV_GET_CPU(env), addr, p, len, 0);
+ }
+ return p;
+}
+#define lock_user(type, p, len, copy) softmmu_lock_user(env, p, len, copy)
+static char *softmmu_lock_user_string(CPUArchState *env, target_ulong addr)
+{
+ char *p;
+ char *s;
+ uint8_t c;
+ /* TODO: Make this something that isn't fixed size. */
+ s = p = malloc(1024);
+ if (!s) {
+ return NULL;
+ }
+ do {
+ armsemi_memory_rw_debug(ENV_GET_CPU(env), addr, &c, 1, 0);
+ addr++;
+ *(p++) = c;
+ } while (c);
+ return s;
+}
+#define lock_user_string(p) softmmu_lock_user_string(env, p)
+static void softmmu_unlock_user(CPUArchState *env, void *p, target_ulong addr,
+ target_ulong len)
+{
+ uint8_t *pc = p;
+ if (len) {
+ armsemi_memory_rw_debug(ENV_GET_CPU(env), addr, p, len, 1);
+ }
+ free(p);
+}
+
+#define unlock_user(s, args, len) softmmu_unlock_user(env, s, args, len)
+
+#endif
diff --git a/target-arm/arm-semi.c b/target-arm/arm-semi.c
index 7cac873..a9cf5f2 100644
--- a/target-arm/arm-semi.c
+++ b/target-arm/arm-semi.c
@@ -114,7 +114,7 @@ static inline uint32_t set_swi_errno(CPUARMState *env, uint32_t code)
return code;
}
-#include "exec/softmmu-semi.h"
+#include "exec/softmmu-arm-semi.h"
#endif
static target_ulong arm_semi_syscall_len;
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 15a174f..2918b24 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -32,6 +32,7 @@
#include "sysemu/sysemu.h"
#include "sysemu/kvm.h"
#include "kvm_arm.h"
+#include "exec/cpu-common.h"
static void arm_cpu_set_pc(CPUState *cs, vaddr value)
{
@@ -780,6 +781,17 @@ static void arm926_initfn(Object *obj)
cpu->reset_sctlr = 0x00090078;
}
+/* FIXME: This is likely not the best way to override or specify endianness
+ * for a CPU/board.
+ */
+static void arm926_be_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ arm926_initfn(obj);
+ cpu->reset_sctlr |= SCTLR_B;
+}
+
static void arm946_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
@@ -1248,6 +1260,17 @@ static void cortex_a15_initfn(Object *obj)
define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
}
+/* FIXME: As arm926_be_initfn, this is likely not the best way to override or
+ * specify endianness for a CPU/board.
+ */
+static void cortex_a15_be_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ cortex_a15_initfn(obj);
+ cpu->reset_sctlr |= SCTLR_EE;
+}
+
static void ti925t_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
@@ -1442,6 +1465,7 @@ typedef struct ARMCPUInfo {
static const ARMCPUInfo arm_cpus[] = {
#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
{ .name = "arm926", .initfn = arm926_initfn },
+ { .name = "arm926-be", .initfn = arm926_be_initfn },
{ .name = "arm946", .initfn = arm946_initfn },
{ .name = "arm1026", .initfn = arm1026_initfn },
/* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
@@ -1461,6 +1485,7 @@ static const ARMCPUInfo arm_cpus[] = {
{ .name = "cortex-a8", .initfn = cortex_a8_initfn },
{ .name = "cortex-a9", .initfn = cortex_a9_initfn },
{ .name = "cortex-a15", .initfn = cortex_a15_initfn },
+ { .name = "cortex-a15-be", .initfn = cortex_a15_be_initfn },
{ .name = "ti925t", .initfn = ti925t_initfn },
{ .name = "sa1100", .initfn = sa1100_initfn },
{ .name = "sa1110", .initfn = sa1110_initfn },
@@ -1519,6 +1544,27 @@ static gchar *arm_gdb_arch_name(CPUState *cs)
return g_strdup("arm");
}
+#ifndef CONFIG_USER_ONLY
+static int arm_cpu_memory_rw_debug(CPUState *cpu, vaddr address,
+ uint8_t *buf, int len, bool is_write)
+{
+ target_ulong addr = address;
+ ARMCPU *armcpu = ARM_CPU(cpu);
+ CPUARMState *env = &armcpu->env;
+
+ if (arm_sctlr_b(env)) {
+ target_ulong i;
+ for (i = 0; i < len; i++) {
+ cpu_memory_rw_debug(cpu, (addr + i) ^ 3, &buf[i], 1, is_write);
+ }
+ } else {
+ cpu_memory_rw_debug(cpu, addr, buf, len, is_write);
+ }
+
+ return 0;
+}
+#endif
+
static void arm_cpu_class_init(ObjectClass *oc, void *data)
{
ARMCPUClass *acc = ARM_CPU_CLASS(oc);
@@ -1536,6 +1582,9 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
cc->has_work = arm_cpu_has_work;
cc->cpu_exec_interrupt = arm_cpu_exec_interrupt;
cc->dump_state = arm_cpu_dump_state;
+#if !defined(CONFIG_USER_ONLY)
+ cc->memory_rw_debug = arm_cpu_memory_rw_debug;
+#endif
cc->set_pc = arm_cpu_set_pc;
cc->gdb_read_register = arm_cpu_gdb_read_register;
cc->gdb_write_register = arm_cpu_gdb_write_register;
diff --git a/target-arm/gdbstub.c b/target-arm/gdbstub.c
index 04c1208..1e9fe68 100644
--- a/target-arm/gdbstub.c
+++ b/target-arm/gdbstub.c
@@ -21,6 +21,7 @@
#include "qemu-common.h"
#include "cpu.h"
#include "exec/gdbstub.h"
+#include "exec/softmmu-arm-semi.h"
/* Old gdb always expect FPA registers. Newer (xml-aware) gdb only expect
whatever the target description contains. Due to a historical mishap
@@ -32,10 +33,22 @@ int arm_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
{
ARMCPU *cpu = ARM_CPU(cs);
CPUARMState *env = &cpu->env;
+#ifndef CONFIG_USER_ONLY
+ bool targ_bigendian = arm_bswap_needed(env);
+#endif
if (n < 16) {
/* Core integer register. */
+#ifdef CONFIG_USER_ONLY
return gdb_get_reg32(mem_buf, env->regs[n]);
+#else
+ if (targ_bigendian) {
+ stl_be_p(mem_buf, env->regs[n]);
+ } else {
+ stl_le_p(mem_buf, env->regs[n]);
+ }
+ return 4;
+#endif
}
if (n < 24) {
/* FPA registers. */
@@ -51,10 +64,28 @@ int arm_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
if (gdb_has_xml) {
return 0;
}
+#ifdef CONFIG_USER_ONLY
return gdb_get_reg32(mem_buf, 0);
+#else
+ if (targ_bigendian) {
+ stl_be_p(mem_buf, 0);
+ } else {
+ stl_le_p(mem_buf, 0);
+ }
+ return 4;
+#endif
case 25:
/* CPSR */
+#ifdef CONFIG_USER_ONLY
return gdb_get_reg32(mem_buf, cpsr_read(env));
+#else
+ if (targ_bigendian) {
+ stl_be_p(mem_buf, cpsr_read(env));
+ } else {
+ stl_le_p(mem_buf, cpsr_read(env));
+ }
+ return 4;
+#endif
}
/* Unknown register. */
return 0;
@@ -65,8 +96,19 @@ int arm_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
ARMCPU *cpu = ARM_CPU(cs);
CPUARMState *env = &cpu->env;
uint32_t tmp;
+#ifndef CONFIG_USER_ONLY
+ bool targ_bigendian = arm_bswap_needed(env);
+#endif
+#ifdef CONFIG_USER_ONLY
tmp = ldl_p(mem_buf);
+#else
+ if (targ_bigendian) {
+ tmp = ldl_be_p(mem_buf);
+ } else {
+ tmp = ldl_le_p(mem_buf);
+ }
+#endif
/* Mask out low bit of PC to workaround gdb bugs. This will probably
cause problems if we ever implement the Jazelle DBX extensions. */
--
1.9.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [Qemu-devel] [PATCH 2/5] Fix Thumb-1 BE32 execution and disassembly.
2016-11-03 17:30 [Qemu-devel] [PATCH 0/5] ARM BE8/BE32 big-endian system-mode fixes (semihosting, gdbstub) Julian Brown
2016-11-03 17:30 ` [Qemu-devel] [PATCH 1/5] ARM BE8/BE32 semihosting and gdbstub support Julian Brown
@ 2016-11-03 17:30 ` Julian Brown
2016-11-04 13:30 ` Peter Maydell
2016-11-03 17:30 ` [Qemu-devel] [PATCH 3/5] Fix arm_semi_flen_cb for BE32 system mode Julian Brown
` (4 subsequent siblings)
6 siblings, 1 reply; 28+ messages in thread
From: Julian Brown @ 2016-11-03 17:30 UTC (permalink / raw)
To: qemu-devel
Thumb-1 code has some issues in BE32 mode (as currently implemented). In
short, since bytes are swapped within words at load time for BE32
executables, this also swaps pairs of adjacent Thumb-1 instructions.
This patch un-swaps those pairs of instructions again, both for execution,
and for disassembly.
Signed-off-by: Julian Brown <julian@codesourcery.com>
---
disas/arm.c | 46 +++++++++++++++++++++++++++++++++++-----------
include/disas/bfd.h | 1 +
target-arm/arm_ldst.h | 10 +++++++++-
target-arm/cpu.c | 4 ++++
4 files changed, 49 insertions(+), 12 deletions(-)
diff --git a/disas/arm.c b/disas/arm.c
index 93c6503..4807ba3 100644
--- a/disas/arm.c
+++ b/disas/arm.c
@@ -3863,10 +3863,11 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info)
int is_data = false;
unsigned int size = 4;
void (*printer) (bfd_vma, struct disassemble_info *, long);
- int little;
+ int little, is_thumb1_be32 = false;
little = (info->endian == BFD_ENDIAN_LITTLE);
is_thumb |= (pc & 1);
+ is_thumb1_be32 = (info->flags & INSN_ARM_THUMB1_BE32) != 0;
pc &= ~(bfd_vma)1;
if (force_thumb)
@@ -3915,11 +3916,22 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info)
info->bytes_per_chunk = 2;
size = 2;
- status = info->read_memory_func (pc, (bfd_byte *)b, 2, info);
- if (little)
- given = (b[0]) | (b[1] << 8);
- else
- given = (b[1]) | (b[0] << 8);
+ if (is_thumb1_be32) {
+ status = info->read_memory_func(pc & ~3, (bfd_byte *)b, 4, info);
+ assert(little);
+ if ((pc & 2) == 0) {
+ given = b[2] | (b[3] << 8);
+ } else {
+ given = b[0] | (b[1] << 8);
+ }
+ } else {
+ status = info->read_memory_func(pc, (bfd_byte *)b, 2, info);
+ if (little) {
+ given = (b[0]) | (b[1] << 8);
+ } else {
+ given = (b[1]) | (b[0] << 8);
+ }
+ }
if (!status)
{
@@ -3929,11 +3941,23 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info)
|| (given & 0xF800) == 0xF000
|| (given & 0xF800) == 0xE800)
{
- status = info->read_memory_func (pc + 2, (bfd_byte *)b, 2, info);
- if (little)
- given = (b[0]) | (b[1] << 8) | (given << 16);
- else
- given = (b[1]) | (b[0] << 8) | (given << 16);
+ if (is_thumb1_be32) {
+ status = info->read_memory_func((pc + 2) & ~3,
+ (bfd_byte *)b, 4, info);
+ if (((pc + 2) & 2) == 0) {
+ given = b[2] | (b[3] << 8) | (given << 16);
+ } else {
+ given = b[0] | (b[1] << 8) | (given << 16);
+ }
+ } else {
+ status = info->read_memory_func(pc + 2, (bfd_byte *)b, 2,
+ info);
+ if (little) {
+ given = (b[0]) | (b[1] << 8) | (given << 16);
+ } else {
+ given = (b[1]) | (b[0] << 8) | (given << 16);
+ }
+ }
printer = print_insn_thumb32;
size = 4;
diff --git a/include/disas/bfd.h b/include/disas/bfd.h
index 8a3488c..76ff6a0 100644
--- a/include/disas/bfd.h
+++ b/include/disas/bfd.h
@@ -291,6 +291,7 @@ typedef struct disassemble_info {
The bottom 16 bits are for the internal use of the disassembler. */
unsigned long flags;
#define INSN_HAS_RELOC 0x80000000
+#define INSN_ARM_THUMB1_BE32 0x00010000
PTR private_data;
/* Function used to get bytes to disassemble. MEMADDR is the
diff --git a/target-arm/arm_ldst.h b/target-arm/arm_ldst.h
index a76d89f..01587b3 100644
--- a/target-arm/arm_ldst.h
+++ b/target-arm/arm_ldst.h
@@ -39,7 +39,15 @@ static inline uint32_t arm_ldl_code(CPUARMState *env, target_ulong addr,
static inline uint16_t arm_lduw_code(CPUARMState *env, target_ulong addr,
bool sctlr_b)
{
- uint16_t insn = cpu_lduw_code(env, addr);
+ uint16_t insn;
+#ifndef CONFIG_USER_ONLY
+ /* In big-endian (BE32) mode, adjacent Thumb instructions have been swapped
+ within each word. Undo that now. */
+ if (sctlr_b) {
+ addr ^= 2;
+ }
+#endif
+ insn = cpu_lduw_code(env, addr);
if (bswap_code(sctlr_b)) {
return bswap16(insn);
}
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 2918b24..b9d7393 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -423,6 +423,10 @@ static void arm_disas_set_info(CPUState *cpu, disassemble_info *info)
#endif
} else if (env->thumb) {
info->print_insn = print_insn_thumb1;
+ info->flags &= ~INSN_ARM_THUMB1_BE32;
+ if (arm_sctlr_b(env)) {
+ info->flags |= INSN_ARM_THUMB1_BE32;
+ }
} else {
info->print_insn = print_insn_arm;
}
--
1.9.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [Qemu-devel] [PATCH 3/5] Fix arm_semi_flen_cb for BE32 system mode.
2016-11-03 17:30 [Qemu-devel] [PATCH 0/5] ARM BE8/BE32 big-endian system-mode fixes (semihosting, gdbstub) Julian Brown
2016-11-03 17:30 ` [Qemu-devel] [PATCH 1/5] ARM BE8/BE32 semihosting and gdbstub support Julian Brown
2016-11-03 17:30 ` [Qemu-devel] [PATCH 2/5] Fix Thumb-1 BE32 execution and disassembly Julian Brown
@ 2016-11-03 17:30 ` Julian Brown
2016-11-04 9:00 ` Paolo Bonzini
2016-11-03 17:30 ` [Qemu-devel] [PATCH 4/5] ARM BE32 watchpoint fix Julian Brown
` (3 subsequent siblings)
6 siblings, 1 reply; 28+ messages in thread
From: Julian Brown @ 2016-11-03 17:30 UTC (permalink / raw)
To: qemu-devel
This patch fixes the arm_semi_flen_cb callback so that it doesn't return
a byte-swapped size in BE32 system mode.
Signed-off-by: Julian Brown <julian@codesourcery.com>
---
target-arm/arm-semi.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/target-arm/arm-semi.c b/target-arm/arm-semi.c
index a9cf5f2..6c550d0 100644
--- a/target-arm/arm-semi.c
+++ b/target-arm/arm-semi.c
@@ -188,7 +188,17 @@ static void arm_semi_flen_cb(CPUState *cs, target_ulong ret, target_ulong err)
the value. We assume the size always fit in 32 bits. */
uint32_t size;
cpu_memory_rw_debug(cs, arm_flen_buf(cpu) + 32, (uint8_t *)&size, 4, 0);
+#ifdef CONFIG_USER_ONLY
size = be32_to_cpu(size);
+#else
+ /* If we're running in BE32 system mode, we don't need to do an explicit
+ * byte swap, because (I think) target memory is already stored in
+ * byte-swapped format.
+ */
+ if (!arm_sctlr_b(env)) {
+ size = be32_to_cpu(size);
+ }
+#endif
if (is_a64(env)) {
env->xregs[0] = size;
} else {
--
1.9.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [Qemu-devel] [PATCH 4/5] ARM BE32 watchpoint fix.
2016-11-03 17:30 [Qemu-devel] [PATCH 0/5] ARM BE8/BE32 big-endian system-mode fixes (semihosting, gdbstub) Julian Brown
` (2 preceding siblings ...)
2016-11-03 17:30 ` [Qemu-devel] [PATCH 3/5] Fix arm_semi_flen_cb for BE32 system mode Julian Brown
@ 2016-11-03 17:30 ` Julian Brown
2016-11-03 23:14 ` Peter Maydell
2016-11-03 21:26 ` [Qemu-devel] [PATCH 5/5] Fix typo in arm_cpu_do_interrupt_aarch32 Julian Brown
` (2 subsequent siblings)
6 siblings, 1 reply; 28+ messages in thread
From: Julian Brown @ 2016-11-03 17:30 UTC (permalink / raw)
To: qemu-devel
In BE32 mode, sub-word size watchpoints can fail to trigger because the
address of the access is adjusted in the opcode helpers before being
compared with the watchpoint registers. This patch reversed the address
adjustment before performing the comparison.
Signed-off-by: Julian Brown <julian@codesourcery.com>
---
exec.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/exec.c b/exec.c
index 4c84389..eadab54 100644
--- a/exec.c
+++ b/exec.c
@@ -2047,6 +2047,19 @@ static void check_watchpoint(int offset, int len, MemTxAttrs attrs, int flags)
return;
}
vaddr = (cpu->mem_io_vaddr & TARGET_PAGE_MASK) + offset;
+#if defined(TARGET_ARM) && !defined(CONFIG_USER_ONLY)
+ /* In BE32 system mode, target memory is stored byteswapped (FIXME:
+ relative to a little-endian host system), and by the time we reach here
+ (via an opcode helper) the addresses of subword accesses have been
+ adjusted to account for that, which means that watchpoints will not
+ match. Undo the adjustment here. */
+ if (arm_sctlr_b(env)) {
+ if (len == 1)
+ vaddr ^= 3;
+ else if (len == 2)
+ vaddr ^= 2;
+ }
+#endif
QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
if (cpu_watchpoint_address_matches(wp, vaddr, len)
&& (wp->flags & flags)) {
--
1.9.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [Qemu-devel] [PATCH 5/5] Fix typo in arm_cpu_do_interrupt_aarch32.
2016-11-03 17:30 [Qemu-devel] [PATCH 0/5] ARM BE8/BE32 big-endian system-mode fixes (semihosting, gdbstub) Julian Brown
` (3 preceding siblings ...)
2016-11-03 17:30 ` [Qemu-devel] [PATCH 4/5] ARM BE32 watchpoint fix Julian Brown
@ 2016-11-03 21:26 ` Julian Brown
2016-11-04 13:02 ` Peter Maydell
2016-11-03 21:29 ` [Qemu-devel] [PATCH 0/5] ARM BE8/BE32 big-endian system-mode fixes (semihosting, gdbstub) no-reply
2016-11-03 21:37 ` no-reply
6 siblings, 1 reply; 28+ messages in thread
From: Julian Brown @ 2016-11-03 21:26 UTC (permalink / raw)
To: qemu-devel
This appears to be a typo in arm_cpu_do_interrupt_aarch32 (OR'ing with ~CPSR_E
instead of CPSR_E).
Signed-off-by: Julian Brown <julian@codesourcery.com>
---
target-arm/helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 25b15dc..b5b65ca 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -6438,7 +6438,7 @@ static void arm_cpu_do_interrupt_aarch32(CPUState *cs)
/* Set new mode endianness */
env->uncached_cpsr &= ~CPSR_E;
if (env->cp15.sctlr_el[arm_current_el(env)] & SCTLR_EE) {
- env->uncached_cpsr |= ~CPSR_E;
+ env->uncached_cpsr |= CPSR_E;
}
env->daif |= mask;
/* this is a lie, as the was no c1_sys on V4T/V5, but who cares
--
1.9.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* Re: [Qemu-devel] [PATCH 0/5] ARM BE8/BE32 big-endian system-mode fixes (semihosting, gdbstub)
2016-11-03 17:30 [Qemu-devel] [PATCH 0/5] ARM BE8/BE32 big-endian system-mode fixes (semihosting, gdbstub) Julian Brown
` (4 preceding siblings ...)
2016-11-03 21:26 ` [Qemu-devel] [PATCH 5/5] Fix typo in arm_cpu_do_interrupt_aarch32 Julian Brown
@ 2016-11-03 21:29 ` no-reply
2016-11-03 21:37 ` no-reply
6 siblings, 0 replies; 28+ messages in thread
From: no-reply @ 2016-11-03 21:29 UTC (permalink / raw)
To: julian; +Cc: famz, qemu-devel
Hi,
Your series seems to have some coding style problems. See output below for
more information:
Type: series
Subject: [Qemu-devel] [PATCH 0/5] ARM BE8/BE32 big-endian system-mode fixes (semihosting, gdbstub)
Message-id: 1478194258-75276-1-git-send-email-julian@codesourcery.com
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
n=1
total=$(git log --oneline $BASE.. | wc -l)
failed=0
# Useful git options
git config --local diff.renamelimit 0
git config --local diff.renames True
commits="$(git log --format=%H --reverse $BASE..)"
for c in $commits; do
echo "Checking PATCH $n/$total: $(git show --no-patch --format=%s $c)..."
if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; then
failed=1
echo
fi
n=$((n+1))
done
exit $failed
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
* [new tag] patchew/1478194258-75276-1-git-send-email-julian@codesourcery.com -> patchew/1478194258-75276-1-git-send-email-julian@codesourcery.com
Switched to a new branch 'test'
fed6fdc Fix typo in arm_cpu_do_interrupt_aarch32.
8e8228b ARM BE32 watchpoint fix.
c35a16c Fix arm_semi_flen_cb for BE32 system mode.
34c88b7 Fix Thumb-1 BE32 execution and disassembly.
23bc6c4 ARM BE8/BE32 semihosting and gdbstub support.
=== OUTPUT BEGIN ===
fatal: unrecognized argument: --no-patch
Checking PATCH 1/5: ...
fatal: unrecognized argument: --no-patch
Checking PATCH 2/5: ...
ERROR: suspect code indent for conditional statements (6, 10)
#42: FILE: disas/arm.c:3919:
+ if (is_thumb1_be32) {
+ status = info->read_memory_func(pc & ~3, (bfd_byte *)b, 4, info);
ERROR: suspect code indent for conditional statements (10, 14)
#45: FILE: disas/arm.c:3922:
+ if ((pc & 2) == 0) {
+ given = b[2] | (b[3] << 8);
ERROR: suspect code indent for conditional statements (10, 14)
#52: FILE: disas/arm.c:3929:
+ if (little) {
+ given = (b[0]) | (b[1] << 8);
ERROR: suspect code indent for conditional statements (14, 18)
#70: FILE: disas/arm.c:3944:
+ if (is_thumb1_be32) {
+ status = info->read_memory_func((pc + 2) & ~3,
ERROR: suspect code indent for conditional statements (18, 22)
#73: FILE: disas/arm.c:3947:
+ if (((pc + 2) & 2) == 0) {
+ given = b[2] | (b[3] << 8) | (given << 16);
ERROR: suspect code indent for conditional statements (18, 22)
#81: FILE: disas/arm.c:3955:
+ if (little) {
+ given = (b[0]) | (b[1] << 8) | (given << 16);
total: 6 errors, 0 warnings, 100 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
fatal: unrecognized argument: --no-patch
Checking PATCH 3/5: ...
fatal: unrecognized argument: --no-patch
Checking PATCH 4/5: ...
fatal: unrecognized argument: --no-patch
Checking PATCH 5/5: ...
=== OUTPUT END ===
Test command exited with code: 1
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@freelists.org
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [Qemu-devel] [PATCH 0/5] ARM BE8/BE32 big-endian system-mode fixes (semihosting, gdbstub)
2016-11-03 17:30 [Qemu-devel] [PATCH 0/5] ARM BE8/BE32 big-endian system-mode fixes (semihosting, gdbstub) Julian Brown
` (5 preceding siblings ...)
2016-11-03 21:29 ` [Qemu-devel] [PATCH 0/5] ARM BE8/BE32 big-endian system-mode fixes (semihosting, gdbstub) no-reply
@ 2016-11-03 21:37 ` no-reply
6 siblings, 0 replies; 28+ messages in thread
From: no-reply @ 2016-11-03 21:37 UTC (permalink / raw)
To: julian; +Cc: famz, qemu-devel
Hi,
Your series failed automatic build test. Please find the testing commands and
their output below. If you have docker installed, you can probably reproduce it
locally.
Type: series
Subject: [Qemu-devel] [PATCH 0/5] ARM BE8/BE32 big-endian system-mode fixes (semihosting, gdbstub)
Message-id: 1478194258-75276-1-git-send-email-julian@codesourcery.com
=== TEST SCRIPT BEGIN ===
#!/bin/bash
set -e
git submodule update --init dtc
# Let docker tests dump environment info
export SHOW_ENV=1
export J=16
make docker-test-quick@centos6
make docker-test-mingw@fedora
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
Switched to a new branch 'test'
fed6fdc Fix typo in arm_cpu_do_interrupt_aarch32.
8e8228b ARM BE32 watchpoint fix.
c35a16c Fix arm_semi_flen_cb for BE32 system mode.
34c88b7 Fix Thumb-1 BE32 execution and disassembly.
23bc6c4 ARM BE8/BE32 semihosting and gdbstub support.
=== OUTPUT BEGIN ===
Submodule 'dtc' (git://git.qemu-project.org/dtc.git) registered for path 'dtc'
Cloning into 'dtc'...
Submodule path 'dtc': checked out '65cc4d2748a2c2e6f27f1cf39e07a5dbabd80ebf'
BUILD centos6
make[1]: Entering directory `/var/tmp/patchew-tester-tmp-pb3qxzah/src'
ARCHIVE qemu.tgz
ARCHIVE dtc.tgz
COPY RUNNER
RUN test-quick in qemu:centos6
Packages installed:
SDL-devel-1.2.14-7.el6_7.1.x86_64
ccache-3.1.6-2.el6.x86_64
epel-release-6-8.noarch
gcc-4.4.7-17.el6.x86_64
git-1.7.1-4.el6_7.1.x86_64
glib2-devel-2.28.8-5.el6.x86_64
libfdt-devel-1.4.0-1.el6.x86_64
make-3.81-23.el6.x86_64
package g++ is not installed
pixman-devel-0.32.8-1.el6.x86_64
tar-1.23-15.el6_8.x86_64
zlib-devel-1.2.3-29.el6.x86_64
Environment variables:
PACKAGES=libfdt-devel ccache tar git make gcc g++ zlib-devel glib2-devel SDL-devel pixman-devel epel-release
HOSTNAME=3aa916f573da
TERM=xterm
MAKEFLAGS= -j16
HISTSIZE=1000
J=16
USER=root
CCACHE_DIR=/var/tmp/ccache
EXTRA_CONFIGURE_OPTS=
V=
SHOW_ENV=1
MAIL=/var/spool/mail/root
PATH=/usr/lib/ccache:/usr/lib64/ccache:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin
PWD=/
LANG=en_US.UTF-8
TARGET_LIST=
HISTCONTROL=ignoredups
SHLVL=1
HOME=/root
TEST_DIR=/tmp/qemu-test
LOGNAME=root
LESSOPEN=||/usr/bin/lesspipe.sh %s
FEATURES= dtc
DEBUG=
G_BROKEN_FILENAMES=1
CCACHE_HASHDIR=
_=/usr/bin/env
Configure options:
--enable-werror --target-list=x86_64-softmmu,aarch64-softmmu --prefix=/var/tmp/qemu-build/install
No C++ compiler available; disabling C++ specific optional code
Install prefix /var/tmp/qemu-build/install
BIOS directory /var/tmp/qemu-build/install/share/qemu
binary directory /var/tmp/qemu-build/install/bin
library directory /var/tmp/qemu-build/install/lib
module directory /var/tmp/qemu-build/install/lib/qemu
libexec directory /var/tmp/qemu-build/install/libexec
include directory /var/tmp/qemu-build/install/include
config directory /var/tmp/qemu-build/install/etc
local state directory /var/tmp/qemu-build/install/var
Manual directory /var/tmp/qemu-build/install/share/man
ELF interp prefix /usr/gnemul/qemu-%M
Source path /tmp/qemu-test/src
C compiler cc
Host C compiler cc
C++ compiler
Objective-C compiler cc
ARFLAGS rv
CFLAGS -O2 -U_FORTIFY_SOURCE -D_FORTIFY_SOURCE=2 -g
QEMU_CFLAGS -I/usr/include/pixman-1 -pthread -I/usr/include/glib-2.0 -I/usr/lib64/glib-2.0/include -fPIE -DPIE -m64 -mcx16 -D_GNU_SOURCE -D_FILE_OFFSET_BITS=64 -D_LARGEFILE_SOURCE -Wstrict-prototypes -Wredundant-decls -Wall -Wundef -Wwrite-strings -Wmissing-prototypes -fno-strict-aliasing -fno-common -fwrapv -Wendif-labels -Wmissing-include-dirs -Wempty-body -Wnested-externs -Wformat-security -Wformat-y2k -Winit-self -Wignored-qualifiers -Wold-style-declaration -Wold-style-definition -Wtype-limits -fstack-protector-all
LDFLAGS -Wl,--warn-common -Wl,-z,relro -Wl,-z,now -pie -m64 -g
make make
install install
python python -B
smbd /usr/sbin/smbd
module support no
host CPU x86_64
host big endian no
target list x86_64-softmmu aarch64-softmmu
tcg debug enabled no
gprof enabled no
sparse enabled no
strip binaries yes
profiler no
static build no
pixman system
SDL support yes (1.2.14)
GTK support no
GTK GL support no
VTE support no
TLS priority NORMAL
GNUTLS support no
GNUTLS rnd no
libgcrypt no
libgcrypt kdf no
nettle no
nettle kdf no
libtasn1 no
curses support no
virgl support no
curl support no
mingw32 support no
Audio drivers oss
Block whitelist (rw)
Block whitelist (ro)
VirtFS support no
VNC support yes
VNC SASL support no
VNC JPEG support no
VNC PNG support no
xen support no
brlapi support no
bluez support no
Documentation no
PIE yes
vde support no
netmap support no
Linux AIO support no
ATTR/XATTR support yes
Install blobs yes
KVM support yes
COLO support yes
RDMA support no
TCG interpreter no
fdt support yes
preadv support yes
fdatasync yes
madvise yes
posix_madvise yes
libcap-ng support no
vhost-net support yes
vhost-scsi support yes
vhost-vsock support yes
Trace backends log
spice support no
rbd support no
xfsctl support no
smartcard support no
libusb no
usb net redir no
OpenGL support no
OpenGL dmabufs no
libiscsi support no
libnfs support no
build guest agent yes
QGA VSS support no
QGA w32 disk info no
QGA MSI support no
seccomp support no
coroutine backend ucontext
coroutine pool yes
debug stack usage no
GlusterFS support no
Archipelago support no
gcov gcov
gcov enabled no
TPM support yes
libssh2 support no
TPM passthrough yes
QOM debugging yes
lzo support no
snappy support no
bzip2 support no
NUMA host support no
tcmalloc support no
jemalloc support no
avx2 optimization no
replication support yes
GEN x86_64-softmmu/config-devices.mak.tmp
GEN aarch64-softmmu/config-devices.mak.tmp
GEN config-host.h
GEN qemu-options.def
GEN qmp-commands.h
GEN qapi-types.h
GEN qapi-visit.h
GEN qapi-event.h
GEN qmp-introspect.h
GEN x86_64-softmmu/config-devices.mak
GEN aarch64-softmmu/config-devices.mak
GEN module_block.h
GEN tests/test-qapi-types.h
GEN tests/test-qapi-visit.h
GEN tests/test-qmp-commands.h
GEN tests/test-qapi-event.h
GEN tests/test-qmp-introspect.h
GEN config-all-devices.mak
GEN trace/generated-tracers.h
GEN trace/generated-tcg-tracers.h
GEN trace/generated-helpers-wrappers.h
GEN trace/generated-helpers.h
CC tests/qemu-iotests/socket_scm_helper.o
GEN qga/qapi-generated/qga-qapi-types.h
GEN qga/qapi-generated/qga-qapi-visit.h
GEN qga/qapi-generated/qga-qmp-commands.h
GEN qga/qapi-generated/qga-qapi-types.c
GEN qga/qapi-generated/qga-qapi-visit.c
GEN qga/qapi-generated/qga-qmp-marshal.c
GEN qmp-introspect.c
GEN qapi-types.c
GEN qapi-visit.c
GEN qapi-event.c
CC qapi/qapi-visit-core.o
CC qapi/qapi-dealloc-visitor.o
CC qapi/qobject-input-visitor.o
CC qapi/qobject-output-visitor.o
CC qapi/qmp-registry.o
CC qapi/qmp-dispatch.o
CC qapi/string-input-visitor.o
CC qapi/string-output-visitor.o
CC qapi/opts-visitor.o
CC qapi/qapi-clone-visitor.o
CC qapi/qmp-event.o
CC qapi/qapi-util.o
CC qobject/qnull.o
CC qobject/qint.o
CC qobject/qstring.o
CC qobject/qdict.o
CC qobject/qlist.o
CC qobject/qfloat.o
CC qobject/qbool.o
CC qobject/qjson.o
CC qobject/qobject.o
CC qobject/json-lexer.o
CC qobject/json-streamer.o
CC qobject/json-parser.o
GEN trace/generated-tracers.c
CC trace/control.o
CC trace/qmp.o
CC util/osdep.o
CC util/cutils.o
CC util/unicode.o
CC util/qemu-timer-common.o
CC util/bufferiszero.o
CC util/compatfd.o
CC util/event_notifier-posix.o
CC util/mmap-alloc.o
CC util/oslib-posix.o
CC util/qemu-openpty.o
CC util/qemu-thread-posix.o
CC util/memfd.o
CC util/envlist.o
CC util/path.o
CC util/module.o
CC util/bitmap.o
CC util/bitops.o
CC util/hbitmap.o
CC util/fifo8.o
CC util/acl.o
CC util/error.o
CC util/qemu-error.o
CC util/id.o
CC util/iov.o
CC util/qemu-config.o
CC util/qemu-sockets.o
CC util/uri.o
CC util/notify.o
CC util/qemu-option.o
CC util/qemu-progress.o
CC util/hexdump.o
CC util/crc32c.o
CC util/uuid.o
CC util/throttle.o
CC util/getauxval.o
CC util/readline.o
CC util/rcu.o
CC util/qemu-coroutine.o
CC util/qemu-coroutine-lock.o
CC util/qemu-coroutine-io.o
CC util/qemu-coroutine-sleep.o
CC util/coroutine-ucontext.o
CC util/buffer.o
CC util/timed-average.o
CC util/base64.o
CC util/log.o
CC util/qdist.o
CC util/qht.o
CC util/range.o
CC crypto/pbkdf-stub.o
CC stubs/arch-query-cpu-def.o
CC stubs/arch-query-cpu-model-comparison.o
CC stubs/arch-query-cpu-model-expansion.o
CC stubs/arch-query-cpu-model-baseline.o
CC stubs/bdrv-next-monitor-owned.o
CC stubs/blk-commit-all.o
CC stubs/blockdev-close-all-bdrv-states.o
CC stubs/clock-warp.o
CC stubs/cpu-get-clock.o
CC stubs/cpu-get-icount.o
CC stubs/dump.o
CC stubs/fdset-add-fd.o
CC stubs/fdset-find-fd.o
CC stubs/fdset-get-fd.o
CC stubs/fdset-remove-fd.o
CC stubs/gdbstub.o
CC stubs/get-fd.o
CC stubs/get-next-serial.o
CC stubs/get-vm-name.o
CC stubs/iothread.o
CC stubs/iothread-lock.o
CC stubs/is-daemonized.o
CC stubs/machine-init-done.o
CC stubs/migr-blocker.o
CC stubs/mon-is-qmp.o
CC stubs/mon-printf.o
CC stubs/monitor-init.o
CC stubs/notify-event.o
CC stubs/qtest.o
CC stubs/replay.o
CC stubs/replay-user.o
CC stubs/reset.o
CC stubs/runstate-check.o
CC stubs/set-fd-handler.o
CC stubs/slirp.o
CC stubs/sysbus.o
CC stubs/trace-control.o
CC stubs/uuid.o
CC stubs/vm-stop.o
CC stubs/vmstate.o
CC stubs/cpus.o
CC stubs/kvm.o
CC stubs/qmp_pc_dimm_device_list.o
CC stubs/target-monitor-defs.o
CC stubs/vhost.o
CC stubs/target-get-monitor-def.o
CC stubs/iohandler.o
CC stubs/smbios_type_38.o
CC stubs/ipmi.o
CC stubs/pc_madt_cpu_entry.o
CC stubs/migration-colo.o
CC contrib/ivshmem-client/ivshmem-client.o
CC contrib/ivshmem-client/main.o
CC contrib/ivshmem-server/ivshmem-server.o
CC contrib/ivshmem-server/main.o
CC qemu-nbd.o
CC async.o
CC thread-pool.o
CC block.o
CC blockjob.o
CC main-loop.o
CC iohandler.o
CC qemu-timer.o
CC aio-posix.o
CC qemu-io-cmds.o
CC replication.o
CC block/raw_bsd.o
CC block/qcow.o
CC block/vdi.o
CC block/vmdk.o
CC block/cloop.o
CC block/bochs.o
CC block/vpc.o
CC block/vvfat.o
CC block/dmg.o
CC block/qcow2.o
CC block/qcow2-refcount.o
CC block/qcow2-cluster.o
CC block/qcow2-snapshot.o
CC block/qcow2-cache.o
CC block/qed.o
CC block/qed-gencb.o
CC block/qed-l2-cache.o
CC block/qed-table.o
CC block/qed-cluster.o
CC block/qed-check.o
CC block/vhdx.o
CC block/vhdx-endian.o
CC block/vhdx-log.o
CC block/quorum.o
CC block/parallels.o
CC block/blkdebug.o
CC block/blkverify.o
CC block/blkreplay.o
CC block/block-backend.o
CC block/snapshot.o
CC block/qapi.o
CC block/raw-posix.o
CC block/null.o
CC block/mirror.o
CC block/commit.o
CC block/io.o
CC block/throttle-groups.o
CC block/nbd.o
CC block/nbd-client.o
CC block/sheepdog.o
CC block/accounting.o
CC block/dirty-bitmap.o
CC block/write-threshold.o
CC block/backup.o
CC block/replication.o
CC block/crypto.o
CC nbd/server.o
CC nbd/client.o
CC nbd/common.o
CC crypto/init.o
CC crypto/hash.o
CC crypto/hash-glib.o
CC crypto/aes.o
CC crypto/desrfb.o
CC crypto/cipher.o
CC crypto/tlscreds.o
CC crypto/tlscredsanon.o
CC crypto/tlscredsx509.o
CC crypto/tlssession.o
CC crypto/secret.o
CC crypto/random-platform.o
CC crypto/pbkdf.o
CC crypto/ivgen.o
CC crypto/ivgen-essiv.o
CC crypto/ivgen-plain.o
CC crypto/ivgen-plain64.o
CC crypto/afsplit.o
CC crypto/xts.o
CC crypto/block.o
CC crypto/block-qcow.o
CC crypto/block-luks.o
CC io/channel.o
CC io/channel-buffer.o
CC io/channel-command.o
CC io/channel-file.o
CC io/channel-socket.o
CC io/channel-tls.o
CC io/channel-watch.o
CC io/channel-websock.o
CC io/channel-util.o
CC io/task.o
CC qom/object.o
CC qom/container.o
CC qom/qom-qobject.o
CC qom/object_interfaces.o
CC qemu-io.o
GEN qemu-img-cmds.h
CC qemu-bridge-helper.o
CC blockdev.o
CC blockdev-nbd.o
CC iothread.o
CC qdev-monitor.o
CC device-hotplug.o
CC os-posix.o
CC qemu-char.o
CC page_cache.o
CC accel.o
CC bt-host.o
CC bt-vhci.o
CC dma-helpers.o
CC vl.o
CC tpm.o
CC device_tree.o
GEN qmp-marshal.c
CC qmp.o
CC hmp.o
CC cpus-common.o
CC audio/audio.o
CC audio/noaudio.o
CC audio/wavaudio.o
CC audio/mixeng.o
CC audio/sdlaudio.o
CC audio/ossaudio.o
CC audio/wavcapture.o
CC backends/rng.o
CC backends/rng-egd.o
CC backends/rng-random.o
CC backends/msmouse.o
CC backends/testdev.o
CC backends/tpm.o
CC backends/hostmem.o
CC backends/hostmem-ram.o
CC backends/hostmem-file.o
CC block/stream.o
CC disas/arm.o
CC disas/i386.o
CC fsdev/qemu-fsdev-dummy.o
CC fsdev/qemu-fsdev-opts.o
CC hw/acpi/core.o
CC hw/acpi/piix4.o
CC hw/acpi/pcihp.o
CC hw/acpi/ich9.o
CC hw/acpi/tco.o
CC hw/acpi/cpu_hotplug.o
CC hw/acpi/memory_hotplug.o
CC hw/acpi/memory_hotplug_acpi_table.o
CC hw/acpi/cpu.o
CC hw/acpi/acpi_interface.o
CC hw/acpi/bios-linker-loader.o
CC hw/acpi/aml-build.o
CC hw/acpi/ipmi.o
CC hw/audio/sb16.o
CC hw/audio/es1370.o
CC hw/audio/ac97.o
CC hw/audio/fmopl.o
CC hw/audio/adlib.o
CC hw/audio/gus.o
CC hw/audio/gusemu_hal.o
CC hw/audio/gusemu_mixer.o
CC hw/audio/cs4231a.o
CC hw/audio/intel-hda.o
CC hw/audio/hda-codec.o
CC hw/audio/pcspk.o
CC hw/audio/wm8750.o
CC hw/audio/pl041.o
CC hw/audio/lm4549.o
CC hw/audio/marvell_88w8618.o
CC hw/block/block.o
CC hw/block/cdrom.o
CC hw/block/hd-geometry.o
CC hw/block/fdc.o
CC hw/block/m25p80.o
CC hw/block/nand.o
CC hw/block/pflash_cfi01.o
CC hw/block/pflash_cfi02.o
CC hw/block/ecc.o
CC hw/block/onenand.o
CC hw/block/nvme.o
CC hw/bt/core.o
CC hw/bt/l2cap.o
CC hw/bt/sdp.o
CC hw/bt/hci.o
CC hw/bt/hid.o
CC hw/bt/hci-csr.o
CC hw/char/ipoctal232.o
CC hw/char/parallel.o
CC hw/char/pl011.o
CC hw/char/serial.o
CC hw/char/serial-isa.o
CC hw/char/serial-pci.o
CC hw/char/virtio-console.o
CC hw/char/cadence_uart.o
CC hw/char/debugcon.o
CC hw/char/imx_serial.o
CC hw/core/qdev.o
CC hw/core/qdev-properties.o
CC hw/core/bus.o
CC hw/core/fw-path-provider.o
CC hw/core/irq.o
CC hw/core/hotplug.o
CC hw/core/ptimer.o
CC hw/core/sysbus.o
CC hw/core/machine.o
CC hw/core/null-machine.o
CC hw/core/loader.o
CC hw/core/qdev-properties-system.o
CC hw/core/register.o
CC hw/core/or-irq.o
CC hw/core/platform-bus.o
CC hw/display/ads7846.o
CC hw/display/cirrus_vga.o
CC hw/display/pl110.o
CC hw/display/ssd0303.o
CC hw/display/ssd0323.o
CC hw/display/vga-pci.o
CC hw/display/vga-isa.o
CC hw/display/vmware_vga.o
CC hw/display/blizzard.o
CC hw/display/exynos4210_fimd.o
CC hw/display/framebuffer.o
CC hw/display/tc6393xb.o
CC hw/dma/pl080.o
CC hw/dma/pl330.o
CC hw/dma/i8257.o
CC hw/dma/xlnx-zynq-devcfg.o
CC hw/gpio/max7310.o
CC hw/gpio/pl061.o
CC hw/gpio/zaurus.o
CC hw/gpio/gpio_key.o
CC hw/i2c/core.o
CC hw/i2c/smbus.o
CC hw/i2c/smbus_eeprom.o
CC hw/i2c/i2c-ddc.o
CC hw/i2c/versatile_i2c.o
CC hw/i2c/smbus_ich9.o
CC hw/i2c/pm_smbus.o
CC hw/i2c/bitbang_i2c.o
CC hw/i2c/exynos4210_i2c.o
CC hw/i2c/imx_i2c.o
CC hw/i2c/aspeed_i2c.o
CC hw/ide/core.o
CC hw/ide/atapi.o
CC hw/ide/qdev.o
CC hw/ide/pci.o
CC hw/ide/isa.o
CC hw/ide/piix.o
CC hw/ide/microdrive.o
CC hw/ide/ahci.o
CC hw/ide/ich.o
CC hw/input/hid.o
CC hw/input/lm832x.o
CC hw/input/pckbd.o
CC hw/input/pl050.o
CC hw/input/stellaris_input.o
CC hw/input/ps2.o
CC hw/input/tsc2005.o
CC hw/input/vmmouse.o
CC hw/input/virtio-input.o
CC hw/input/virtio-input-hid.o
CC hw/input/virtio-input-host.o
CC hw/intc/i8259_common.o
CC hw/intc/i8259.o
CC hw/intc/pl190.o
CC hw/intc/imx_avic.o
CC hw/intc/realview_gic.o
CC hw/intc/ioapic_common.o
CC hw/intc/arm_gic_common.o
CC hw/intc/arm_gic.o
CC hw/intc/arm_gicv2m.o
CC hw/intc/arm_gicv3_common.o
CC hw/intc/arm_gicv3.o
CC hw/intc/arm_gicv3_dist.o
CC hw/intc/arm_gicv3_redist.o
CC hw/intc/arm_gicv3_its_common.o
CC hw/intc/intc.o
CC hw/ipack/ipack.o
CC hw/ipack/tpci200.o
CC hw/ipmi/ipmi.o
CC hw/ipmi/ipmi_bmc_sim.o
CC hw/ipmi/ipmi_bmc_extern.o
CC hw/ipmi/isa_ipmi_kcs.o
CC hw/ipmi/isa_ipmi_bt.o
CC hw/isa/isa-bus.o
CC hw/isa/apm.o
CC hw/mem/pc-dimm.o
CC hw/mem/nvdimm.o
CC hw/misc/applesmc.o
CC hw/misc/max111x.o
CC hw/misc/tmp105.o
CC hw/misc/debugexit.o
CC hw/misc/sga.o
CC hw/misc/pc-testdev.o
CC hw/misc/pci-testdev.o
CC hw/misc/arm_l2x0.o
CC hw/misc/arm_integrator_debug.o
CC hw/misc/a9scu.o
CC hw/misc/arm11scu.o
CC hw/net/ne2000.o
CC hw/net/eepro100.o
CC hw/net/pcnet-pci.o
CC hw/net/pcnet.o
CC hw/net/e1000.o
CC hw/net/e1000x_common.o
CC hw/net/net_tx_pkt.o
CC hw/net/net_rx_pkt.o
CC hw/net/e1000e.o
CC hw/net/e1000e_core.o
CC hw/net/rtl8139.o
CC hw/net/vmxnet3.o
CC hw/net/smc91c111.o
CC hw/net/lan9118.o
CC hw/net/ne2000-isa.o
CC hw/net/xgmac.o
CC hw/net/allwinner_emac.o
CC hw/net/imx_fec.o
CC hw/net/cadence_gem.o
CC hw/net/stellaris_enet.o
CC hw/net/rocker/rocker.o
CC hw/net/rocker/rocker_fp.o
CC hw/net/rocker/rocker_desc.o
CC hw/net/rocker/rocker_world.o
CC hw/net/rocker/rocker_of_dpa.o
CC hw/nvram/eeprom93xx.o
CC hw/nvram/chrp_nvram.o
CC hw/nvram/fw_cfg.o
CC hw/pci-bridge/pci_expander_bridge.o
CC hw/pci-bridge/pci_bridge_dev.o
CC hw/pci-bridge/xio3130_upstream.o
CC hw/pci-bridge/xio3130_downstream.o
CC hw/pci-bridge/ioh3420.o
CC hw/pci-bridge/i82801b11.o
CC hw/pci-host/pam.o
CC hw/pci-host/versatile.o
CC hw/pci-host/piix.o
CC hw/pci-host/q35.o
CC hw/pci-host/gpex.o
CC hw/pci/pci.o
CC hw/pci/pci_bridge.o
CC hw/pci/msix.o
CC hw/pci/msi.o
CC hw/pci/shpc.o
CC hw/pci/slotid_cap.o
CC hw/pci/pci_host.o
CC hw/pci/pcie_host.o
CC hw/pci/pcie.o
CC hw/pci/pcie_aer.o
CC hw/pci/pcie_port.o
CC hw/pci/pci-stub.o
CC hw/pcmcia/pcmcia.o
CC hw/scsi/scsi-generic.o
CC hw/scsi/scsi-disk.o
CC hw/scsi/scsi-bus.o
CC hw/scsi/lsi53c895a.o
CC hw/scsi/mptsas.o
CC hw/scsi/mptconfig.o
CC hw/scsi/mptendian.o
CC hw/scsi/megasas.o
CC hw/scsi/vmw_pvscsi.o
CC hw/scsi/esp.o
CC hw/scsi/esp-pci.o
CC hw/sd/pl181.o
CC hw/sd/ssi-sd.o
CC hw/sd/sd.o
CC hw/sd/core.o
CC hw/sd/sdhci.o
CC hw/smbios/smbios.o
CC hw/smbios/smbios_type_38.o
CC hw/ssi/ssi.o
CC hw/ssi/pl022.o
CC hw/ssi/xilinx_spips.o
CC hw/ssi/aspeed_smc.o
CC hw/ssi/stm32f2xx_spi.o
CC hw/timer/arm_timer.o
CC hw/timer/arm_mptimer.o
CC hw/timer/a9gtimer.o
CC hw/timer/cadence_ttc.o
CC hw/timer/ds1338.o
CC hw/timer/hpet.o
CC hw/timer/i8254_common.o
/tmp/qemu-test/src/hw/nvram/fw_cfg.c: In function ‘fw_cfg_dma_transfer’:
/tmp/qemu-test/src/hw/nvram/fw_cfg.c:329: warning: ‘read’ may be used uninitialized in this function
CC hw/timer/i8254.o
CC hw/timer/pl031.o
CC hw/timer/twl92230.o
CC hw/timer/imx_epit.o
CC hw/timer/imx_gpt.o
CC hw/timer/stm32f2xx_timer.o
CC hw/timer/aspeed_timer.o
CC hw/tpm/tpm_tis.o
CC hw/tpm/tpm_passthrough.o
CC hw/tpm/tpm_util.o
CC hw/usb/core.o
CC hw/usb/combined-packet.o
CC hw/usb/bus.o
CC hw/usb/libhw.o
CC hw/usb/desc.o
CC hw/usb/desc-msos.o
CC hw/usb/hcd-uhci.o
CC hw/usb/hcd-ohci.o
CC hw/usb/hcd-ehci.o
CC hw/usb/hcd-ehci-pci.o
CC hw/usb/hcd-ehci-sysbus.o
CC hw/usb/hcd-xhci.o
CC hw/usb/hcd-musb.o
CC hw/usb/dev-hid.o
CC hw/usb/dev-hub.o
CC hw/usb/dev-wacom.o
CC hw/usb/dev-storage.o
CC hw/usb/dev-uas.o
CC hw/usb/dev-audio.o
CC hw/usb/dev-serial.o
CC hw/usb/dev-network.o
CC hw/usb/dev-bluetooth.o
CC hw/usb/dev-smartcard-reader.o
CC hw/usb/dev-mtp.o
CC hw/usb/host-stub.o
CC hw/virtio/virtio-rng.o
CC hw/virtio/virtio-pci.o
CC hw/virtio/virtio-bus.o
CC hw/virtio/virtio-mmio.o
CC hw/watchdog/watchdog.o
CC hw/watchdog/wdt_i6300esb.o
CC hw/watchdog/wdt_ib700.o
CC migration/migration.o
CC migration/socket.o
CC migration/fd.o
CC migration/exec.o
CC migration/tls.o
CC migration/colo-comm.o
CC migration/colo.o
CC migration/colo-failover.o
CC migration/vmstate.o
CC migration/qemu-file.o
CC migration/qemu-file-channel.o
CC migration/xbzrle.o
CC migration/postcopy-ram.o
CC migration/qjson.o
CC migration/block.o
CC net/net.o
CC net/queue.o
CC net/checksum.o
CC net/util.o
CC net/hub.o
CC net/socket.o
CC net/dump.o
CC net/eth.o
CC net/l2tpv3.o
CC net/vhost-user.o
CC net/tap.o
CC net/tap-linux.o
CC net/slirp.o
CC net/filter.o
CC net/filter-buffer.o
CC net/filter-mirror.o
CC net/colo-compare.o
CC net/colo.o
CC net/filter-rewriter.o
CC qom/cpu.o
CC replay/replay.o
CC replay/replay-internal.o
CC replay/replay-events.o
CC replay/replay-time.o
/tmp/qemu-test/src/replay/replay-internal.c: In function ‘replay_put_array’:
/tmp/qemu-test/src/replay/replay-internal.c:65: warning: ignoring return value of ‘fwrite’, declared with attribute warn_unused_result
CC replay/replay-input.o
CC replay/replay-char.o
CC replay/replay-snapshot.o
CC slirp/cksum.o
CC slirp/if.o
CC slirp/ip_icmp.o
CC slirp/ip6_icmp.o
CC slirp/ip6_input.o
CC slirp/ip6_output.o
CC slirp/ip_input.o
CC slirp/ip_output.o
CC slirp/dnssearch.o
CC slirp/dhcpv6.o
CC slirp/slirp.o
CC slirp/mbuf.o
CC slirp/misc.o
CC slirp/sbuf.o
CC slirp/socket.o
CC slirp/tcp_input.o
CC slirp/tcp_output.o
CC slirp/tcp_subr.o
/tmp/qemu-test/src/slirp/tcp_input.c: In function ‘tcp_input’:
/tmp/qemu-test/src/slirp/tcp_input.c:219: warning: ‘save_ip.ip_p’ may be used uninitialized in this function
/tmp/qemu-test/src/slirp/tcp_input.c:219: warning: ‘save_ip.ip_len’ may be used uninitialized in this function
/tmp/qemu-test/src/slirp/tcp_input.c:219: warning: ‘save_ip.ip_tos’ may be used uninitialized in this function
/tmp/qemu-test/src/slirp/tcp_input.c:219: warning: ‘save_ip.ip_id’ may be used uninitialized in this function
/tmp/qemu-test/src/slirp/tcp_input.c:219: warning: ‘save_ip.ip_off’ may be used uninitialized in this function
/tmp/qemu-test/src/slirp/tcp_input.c:219: warning: ‘save_ip.ip_ttl’ may be used uninitialized in this function
/tmp/qemu-test/src/slirp/tcp_input.c:219: warning: ‘save_ip.ip_sum’ may be used uninitialized in this function
/tmp/qemu-test/src/slirp/tcp_input.c:219: warning: ‘save_ip.ip_src.s_addr’ may be used uninitialized in this function
/tmp/qemu-test/src/slirp/tcp_input.c:219: warning: ‘save_ip.ip_dst.s_addr’ may be used uninitialized in this function
/tmp/qemu-test/src/slirp/tcp_input.c:220: warning: ‘save_ip6.ip_nh’ may be used uninitialized in this function
CC slirp/udp.o
CC slirp/tcp_timer.o
CC slirp/udp6.o
CC slirp/tftp.o
CC slirp/bootp.o
CC slirp/ndp_table.o
CC slirp/arp_table.o
CC ui/keymaps.o
CC ui/cursor.o
CC ui/console.o
CC ui/qemu-pixman.o
CC ui/input.o
CC ui/input-keymap.o
CC ui/input-linux.o
CC ui/input-legacy.o
CC ui/sdl.o
CC ui/sdl_zoom.o
CC ui/x_keymap.o
CC ui/vnc.o
CC ui/vnc-enc-zlib.o
CC ui/vnc-enc-hextile.o
CC ui/vnc-enc-tight.o
CC ui/vnc-palette.o
CC ui/vnc-enc-zrle.o
CC ui/vnc-auth-vencrypt.o
CC ui/vnc-jobs.o
CC ui/vnc-ws.o
CC qga/commands.o
CC qga/guest-agent-command-state.o
LINK tests/qemu-iotests/socket_scm_helper
CC qga/commands-posix.o
CC qga/main.o
CC qga/channel-posix.o
CC qga/qapi-generated/qga-qapi-types.o
CC qga/qapi-generated/qga-qapi-visit.o
CC qga/qapi-generated/qga-qmp-marshal.o
CC qmp-introspect.o
CC qapi-types.o
CC qapi-visit.o
CC qapi-event.o
AS optionrom/multiboot.o
AR libqemustub.a
CC qemu-img.o
CC qmp-marshal.o
AS optionrom/linuxboot.o
CC optionrom/linuxboot_dma.o
cc: unrecognized option '-no-integrated-as'
cc: unrecognized option '-no-integrated-as'
CC trace/generated-tracers.o
AS optionrom/kvmvapic.o
BUILD optionrom/multiboot.img
BUILD optionrom/linuxboot.img
BUILD optionrom/linuxboot_dma.img
BUILD optionrom/kvmvapic.img
BUILD optionrom/multiboot.raw
BUILD optionrom/linuxboot.raw
BUILD optionrom/linuxboot_dma.raw
SIGN optionrom/multiboot.bin
BUILD optionrom/kvmvapic.raw
SIGN optionrom/linuxboot.bin
SIGN optionrom/linuxboot_dma.bin
SIGN optionrom/kvmvapic.bin
AR libqemuutil.a
LINK qemu-ga
LINK ivshmem-client
LINK ivshmem-server
LINK qemu-nbd
LINK qemu-img
LINK qemu-io
LINK qemu-bridge-helper
GEN aarch64-softmmu/config-target.h
GEN aarch64-softmmu/hmp-commands.h
GEN aarch64-softmmu/hmp-commands-info.h
GEN x86_64-softmmu/hmp-commands.h
GEN x86_64-softmmu/hmp-commands-info.h
GEN x86_64-softmmu/config-target.h
CC aarch64-softmmu/exec.o
CC aarch64-softmmu/cpu-exec-common.o
CC aarch64-softmmu/translate-all.o
CC aarch64-softmmu/cpu-exec.o
CC aarch64-softmmu/tcg/tcg-op.o
CC aarch64-softmmu/translate-common.o
CC aarch64-softmmu/tcg/tcg.o
CC aarch64-softmmu/tcg/optimize.o
CC aarch64-softmmu/tcg/tcg-common.o
CC aarch64-softmmu/fpu/softfloat.o
CC aarch64-softmmu/disas.o
CC aarch64-softmmu/tcg-runtime.o
GEN aarch64-softmmu/gdbstub-xml.c
CC aarch64-softmmu/arch_init.o
CC aarch64-softmmu/kvm-stub.o
CC aarch64-softmmu/cpus.o
CC x86_64-softmmu/exec.o
CC aarch64-softmmu/monitor.o
CC aarch64-softmmu/gdbstub.o
CC x86_64-softmmu/translate-all.o
CC x86_64-softmmu/cpu-exec.o
CC x86_64-softmmu/translate-common.o
CC aarch64-softmmu/balloon.o
CC x86_64-softmmu/cpu-exec-common.o
CC aarch64-softmmu/ioport.o
CC aarch64-softmmu/numa.o
CC aarch64-softmmu/qtest.o
CC aarch64-softmmu/bootdevice.o
CC x86_64-softmmu/tcg/tcg.o
CC x86_64-softmmu/tcg/tcg-op.o
CC aarch64-softmmu/memory.o
CC aarch64-softmmu/cputlb.o
CC aarch64-softmmu/memory_mapping.o
CC aarch64-softmmu/dump.o
CC aarch64-softmmu/migration/ram.o
CC aarch64-softmmu/migration/savevm.o
CC x86_64-softmmu/tcg/optimize.o
CC x86_64-softmmu/tcg/tcg-common.o
CC aarch64-softmmu/xen-common-stub.o
CC x86_64-softmmu/fpu/softfloat.o
CC aarch64-softmmu/xen-hvm-stub.o
CC aarch64-softmmu/hw/adc/stm32f2xx_adc.o
CC x86_64-softmmu/disas.o
CC x86_64-softmmu/tcg-runtime.o
CC aarch64-softmmu/hw/block/virtio-blk.o
CC x86_64-softmmu/arch_init.o
CC aarch64-softmmu/hw/block/dataplane/virtio-blk.o
CC aarch64-softmmu/hw/char/exynos4210_uart.o
CC x86_64-softmmu/cpus.o
CC x86_64-softmmu/monitor.o
CC x86_64-softmmu/gdbstub.o
CC x86_64-softmmu/balloon.o
CC x86_64-softmmu/ioport.o
CC aarch64-softmmu/hw/char/omap_uart.o
CC aarch64-softmmu/hw/char/digic-uart.o
CC aarch64-softmmu/hw/char/stm32f2xx_usart.o
CC aarch64-softmmu/hw/char/bcm2835_aux.o
CC aarch64-softmmu/hw/char/virtio-serial-bus.o
CC x86_64-softmmu/numa.o
CC x86_64-softmmu/qtest.o
CC aarch64-softmmu/hw/core/nmi.o
CC x86_64-softmmu/bootdevice.o
CC aarch64-softmmu/hw/core/generic-loader.o
CC x86_64-softmmu/kvm-all.o
CC aarch64-softmmu/hw/cpu/arm11mpcore.o
CC aarch64-softmmu/hw/cpu/realview_mpcore.o
CC aarch64-softmmu/hw/cpu/a9mpcore.o
CC aarch64-softmmu/hw/cpu/a15mpcore.o
CC aarch64-softmmu/hw/cpu/core.o
CC x86_64-softmmu/memory.o
CC x86_64-softmmu/cputlb.o
CC aarch64-softmmu/hw/display/omap_dss.o
CC aarch64-softmmu/hw/display/omap_lcdc.o
CC x86_64-softmmu/memory_mapping.o
CC x86_64-softmmu/dump.o
CC aarch64-softmmu/hw/display/pxa2xx_lcd.o
CC aarch64-softmmu/hw/display/bcm2835_fb.o
CC x86_64-softmmu/migration/ram.o
CC aarch64-softmmu/hw/display/vga.o
CC aarch64-softmmu/hw/display/virtio-gpu.o
CC x86_64-softmmu/migration/savevm.o
CC aarch64-softmmu/hw/display/virtio-gpu-3d.o
CC x86_64-softmmu/xen-common-stub.o
CC aarch64-softmmu/hw/display/virtio-gpu-pci.o
CC aarch64-softmmu/hw/display/dpcd.o
CC x86_64-softmmu/xen-hvm-stub.o
CC aarch64-softmmu/hw/display/xlnx_dp.o
CC x86_64-softmmu/hw/acpi/nvdimm.o
CC x86_64-softmmu/hw/block/virtio-blk.o
CC x86_64-softmmu/hw/block/dataplane/virtio-blk.o
CC aarch64-softmmu/hw/dma/xlnx_dpdma.o
CC x86_64-softmmu/hw/char/virtio-serial-bus.o
CC aarch64-softmmu/hw/dma/omap_dma.o
CC x86_64-softmmu/hw/core/nmi.o
CC x86_64-softmmu/hw/core/generic-loader.o
CC aarch64-softmmu/hw/dma/soc_dma.o
CC aarch64-softmmu/hw/dma/pxa2xx_dma.o
CC x86_64-softmmu/hw/cpu/core.o
CC aarch64-softmmu/hw/dma/bcm2835_dma.o
CC x86_64-softmmu/hw/display/vga.o
CC aarch64-softmmu/hw/gpio/omap_gpio.o
CC aarch64-softmmu/hw/gpio/imx_gpio.o
CC aarch64-softmmu/hw/i2c/omap_i2c.o
CC x86_64-softmmu/hw/display/virtio-gpu.o
CC x86_64-softmmu/hw/display/virtio-gpu-3d.o
CC x86_64-softmmu/hw/display/virtio-gpu-pci.o
CC x86_64-softmmu/hw/display/virtio-vga.o
CC aarch64-softmmu/hw/input/pxa2xx_keypad.o
CC aarch64-softmmu/hw/input/tsc210x.o
CC aarch64-softmmu/hw/intc/armv7m_nvic.o
CC x86_64-softmmu/hw/intc/apic.o
CC x86_64-softmmu/hw/intc/apic_common.o
CC x86_64-softmmu/hw/intc/ioapic.o
CC x86_64-softmmu/hw/isa/lpc_ich9.o
CC x86_64-softmmu/hw/misc/vmport.o
CC x86_64-softmmu/hw/misc/ivshmem.o
CC aarch64-softmmu/hw/intc/exynos4210_gic.o
CC aarch64-softmmu/hw/intc/exynos4210_combiner.o
CC aarch64-softmmu/hw/intc/omap_intc.o
CC x86_64-softmmu/hw/misc/pvpanic.o
CC aarch64-softmmu/hw/intc/bcm2835_ic.o
CC aarch64-softmmu/hw/intc/bcm2836_control.o
CC aarch64-softmmu/hw/intc/allwinner-a10-pic.o
CC x86_64-softmmu/hw/misc/edu.o
CC aarch64-softmmu/hw/intc/aspeed_vic.o
CC aarch64-softmmu/hw/misc/ivshmem.o
CC aarch64-softmmu/hw/intc/arm_gicv3_cpuif.o
CC aarch64-softmmu/hw/misc/arm_sysctl.o
CC x86_64-softmmu/hw/misc/hyperv_testdev.o
CC x86_64-softmmu/hw/net/virtio-net.o
CC x86_64-softmmu/hw/scsi/virtio-scsi.o
CC x86_64-softmmu/hw/net/vhost_net.o
CC aarch64-softmmu/hw/misc/cbus.o
CC aarch64-softmmu/hw/misc/exynos4210_pmu.o
CC x86_64-softmmu/hw/scsi/virtio-scsi-dataplane.o
CC aarch64-softmmu/hw/misc/imx_ccm.o
CC aarch64-softmmu/hw/misc/imx31_ccm.o
CC x86_64-softmmu/hw/scsi/vhost-scsi.o
CC aarch64-softmmu/hw/misc/imx25_ccm.o
CC x86_64-softmmu/hw/timer/mc146818rtc.o
CC x86_64-softmmu/hw/vfio/common.o
CC x86_64-softmmu/hw/vfio/pci.o
CC aarch64-softmmu/hw/misc/imx6_src.o
CC aarch64-softmmu/hw/misc/imx6_ccm.o
CC x86_64-softmmu/hw/vfio/pci-quirks.o
CC aarch64-softmmu/hw/misc/mst_fpga.o
CC aarch64-softmmu/hw/misc/omap_clk.o
CC aarch64-softmmu/hw/misc/omap_gpmc.o
CC x86_64-softmmu/hw/vfio/platform.o
CC x86_64-softmmu/hw/vfio/calxeda-xgmac.o
CC x86_64-softmmu/hw/vfio/amd-xgbe.o
CC aarch64-softmmu/hw/misc/omap_l4.o
CC aarch64-softmmu/hw/misc/omap_sdrc.o
CC aarch64-softmmu/hw/misc/omap_tap.o
CC x86_64-softmmu/hw/vfio/spapr.o
CC x86_64-softmmu/hw/virtio/virtio.o
CC aarch64-softmmu/hw/misc/bcm2835_mbox.o
CC aarch64-softmmu/hw/misc/bcm2835_property.o
CC aarch64-softmmu/hw/misc/zynq_slcr.o
CC aarch64-softmmu/hw/misc/zynq-xadc.o
CC aarch64-softmmu/hw/misc/stm32f2xx_syscfg.o
CC aarch64-softmmu/hw/misc/edu.o
CC aarch64-softmmu/hw/misc/auxbus.o
CC aarch64-softmmu/hw/misc/aspeed_scu.o
CC x86_64-softmmu/hw/virtio/virtio-balloon.o
CC aarch64-softmmu/hw/misc/aspeed_sdmc.o
CC x86_64-softmmu/hw/virtio/vhost.o
CC aarch64-softmmu/hw/net/virtio-net.o
CC aarch64-softmmu/hw/net/vhost_net.o
CC x86_64-softmmu/hw/virtio/vhost-backend.o
CC aarch64-softmmu/hw/pcmcia/pxa2xx.o
CC aarch64-softmmu/hw/scsi/virtio-scsi.o
CC aarch64-softmmu/hw/scsi/virtio-scsi-dataplane.o
CC aarch64-softmmu/hw/scsi/vhost-scsi.o
CC x86_64-softmmu/hw/virtio/vhost-user.o
CC aarch64-softmmu/hw/sd/omap_mmc.o
CC x86_64-softmmu/hw/virtio/vhost-vsock.o
CC x86_64-softmmu/hw/i386/multiboot.o
CC aarch64-softmmu/hw/sd/pxa2xx_mmci.o
CC x86_64-softmmu/hw/i386/pc.o
CC x86_64-softmmu/hw/i386/pc_piix.o
CC aarch64-softmmu/hw/ssi/omap_spi.o
CC x86_64-softmmu/hw/i386/pc_q35.o
CC x86_64-softmmu/hw/i386/pc_sysfw.o
CC aarch64-softmmu/hw/ssi/imx_spi.o
CC x86_64-softmmu/hw/i386/x86-iommu.o
CC aarch64-softmmu/hw/timer/exynos4210_mct.o
CC aarch64-softmmu/hw/timer/exynos4210_pwm.o
CC aarch64-softmmu/hw/timer/exynos4210_rtc.o
CC aarch64-softmmu/hw/timer/omap_gptimer.o
CC aarch64-softmmu/hw/timer/omap_synctimer.o
CC x86_64-softmmu/hw/i386/intel_iommu.o
CC x86_64-softmmu/hw/i386/amd_iommu.o
CC aarch64-softmmu/hw/timer/pxa2xx_timer.o
CC aarch64-softmmu/hw/timer/digic-timer.o
CC x86_64-softmmu/hw/i386/kvmvapic.o
CC aarch64-softmmu/hw/timer/allwinner-a10-pit.o
CC x86_64-softmmu/hw/i386/acpi-build.o
CC x86_64-softmmu/hw/i386/pci-assign-load-rom.o
CC x86_64-softmmu/hw/i386/kvm/clock.o
CC aarch64-softmmu/hw/usb/tusb6010.o
CC aarch64-softmmu/hw/vfio/common.o
CC x86_64-softmmu/hw/i386/kvm/apic.o
CC x86_64-softmmu/hw/i386/kvm/i8259.o
CC aarch64-softmmu/hw/vfio/pci.o
CC x86_64-softmmu/hw/i386/kvm/ioapic.o
CC x86_64-softmmu/hw/i386/kvm/i8254.o
CC x86_64-softmmu/hw/i386/kvm/pci-assign.o
CC x86_64-softmmu/target-i386/translate.o
CC x86_64-softmmu/target-i386/helper.o
CC x86_64-softmmu/target-i386/cpu.o
CC x86_64-softmmu/target-i386/bpt_helper.o
/tmp/qemu-test/src/hw/i386/pc_piix.c: In function ‘igd_passthrough_isa_bridge_create’:
/tmp/qemu-test/src/hw/i386/pc_piix.c:1046: warning: ‘pch_rev_id’ may be used uninitialized in this function
CC aarch64-softmmu/hw/vfio/pci-quirks.o
CC x86_64-softmmu/target-i386/excp_helper.o
CC aarch64-softmmu/hw/vfio/platform.o
CC x86_64-softmmu/target-i386/fpu_helper.o
CC aarch64-softmmu/hw/vfio/calxeda-xgmac.o
CC aarch64-softmmu/hw/vfio/amd-xgbe.o
CC aarch64-softmmu/hw/vfio/spapr.o
CC x86_64-softmmu/target-i386/cc_helper.o
CC x86_64-softmmu/target-i386/int_helper.o
CC x86_64-softmmu/target-i386/svm_helper.o
/tmp/qemu-test/src/hw/i386/acpi-build.c: In function ‘build_append_pci_bus_devices’:
/tmp/qemu-test/src/hw/i386/acpi-build.c:501: warning: ‘notify_method’ may be used uninitialized in this function
CC x86_64-softmmu/target-i386/smm_helper.o
CC aarch64-softmmu/hw/virtio/virtio.o
CC aarch64-softmmu/hw/virtio/virtio-balloon.o
CC aarch64-softmmu/hw/virtio/vhost.o
CC aarch64-softmmu/hw/virtio/vhost-backend.o
CC aarch64-softmmu/hw/virtio/vhost-user.o
CC x86_64-softmmu/target-i386/misc_helper.o
CC aarch64-softmmu/hw/virtio/vhost-vsock.o
CC aarch64-softmmu/hw/arm/boot.o
CC x86_64-softmmu/target-i386/mem_helper.o
CC aarch64-softmmu/hw/arm/collie.o
CC x86_64-softmmu/target-i386/seg_helper.o
CC x86_64-softmmu/target-i386/mpx_helper.o
CC x86_64-softmmu/target-i386/gdbstub.o
CC x86_64-softmmu/target-i386/machine.o
CC x86_64-softmmu/target-i386/arch_memory_mapping.o
CC x86_64-softmmu/target-i386/arch_dump.o
CC x86_64-softmmu/target-i386/monitor.o
CC x86_64-softmmu/target-i386/kvm.o
CC x86_64-softmmu/target-i386/hyperv.o
CC aarch64-softmmu/hw/arm/exynos4_boards.o
CC aarch64-softmmu/hw/arm/gumstix.o
CC aarch64-softmmu/hw/arm/highbank.o
CC aarch64-softmmu/hw/arm/digic_boards.o
CC aarch64-softmmu/hw/arm/integratorcp.o
GEN trace/generated-helpers.c
CC x86_64-softmmu/trace/control-target.o
CC aarch64-softmmu/hw/arm/mainstone.o
CC aarch64-softmmu/hw/arm/musicpal.o
CC aarch64-softmmu/hw/arm/nseries.o
CC aarch64-softmmu/hw/arm/omap_sx1.o
CC aarch64-softmmu/hw/arm/palm.o
CC x86_64-softmmu/trace/generated-helpers.o
CC aarch64-softmmu/hw/arm/realview.o
CC aarch64-softmmu/hw/arm/spitz.o
CC aarch64-softmmu/hw/arm/stellaris.o
CC aarch64-softmmu/hw/arm/tosa.o
CC aarch64-softmmu/hw/arm/versatilepb.o
CC aarch64-softmmu/hw/arm/vexpress.o
CC aarch64-softmmu/hw/arm/virt.o
CC aarch64-softmmu/hw/arm/xilinx_zynq.o
CC aarch64-softmmu/hw/arm/z2.o
CC aarch64-softmmu/hw/arm/virt-acpi-build.o
CC aarch64-softmmu/hw/arm/netduino2.o
CC aarch64-softmmu/hw/arm/sysbus-fdt.o
CC aarch64-softmmu/hw/arm/armv7m.o
CC aarch64-softmmu/hw/arm/exynos4210.o
CC aarch64-softmmu/hw/arm/pxa2xx.o
CC aarch64-softmmu/hw/arm/pxa2xx_gpio.o
CC aarch64-softmmu/hw/arm/pxa2xx_pic.o
CC aarch64-softmmu/hw/arm/digic.o
CC aarch64-softmmu/hw/arm/omap1.o
CC aarch64-softmmu/hw/arm/omap2.o
CC aarch64-softmmu/hw/arm/strongarm.o
CC aarch64-softmmu/hw/arm/allwinner-a10.o
CC aarch64-softmmu/hw/arm/cubieboard.o
CC aarch64-softmmu/hw/arm/bcm2835_peripherals.o
CC aarch64-softmmu/hw/arm/bcm2836.o
CC aarch64-softmmu/hw/arm/raspi.o
CC aarch64-softmmu/hw/arm/stm32f205_soc.o
CC aarch64-softmmu/hw/arm/xlnx-zynqmp.o
CC aarch64-softmmu/hw/arm/xlnx-ep108.o
CC aarch64-softmmu/hw/arm/fsl-imx25.o
CC aarch64-softmmu/hw/arm/imx25_pdk.o
CC aarch64-softmmu/hw/arm/fsl-imx31.o
CC aarch64-softmmu/hw/arm/kzm.o
CC aarch64-softmmu/hw/arm/fsl-imx6.o
CC aarch64-softmmu/hw/arm/sabrelite.o
CC aarch64-softmmu/hw/arm/aspeed_soc.o
CC aarch64-softmmu/hw/arm/aspeed.o
CC aarch64-softmmu/target-arm/arm-semi.o
CC aarch64-softmmu/target-arm/machine.o
CC aarch64-softmmu/target-arm/psci.o
CC aarch64-softmmu/target-arm/arch_dump.o
CC aarch64-softmmu/target-arm/monitor.o
CC aarch64-softmmu/target-arm/kvm-stub.o
CC aarch64-softmmu/target-arm/translate.o
CC aarch64-softmmu/target-arm/op_helper.o
CC aarch64-softmmu/target-arm/helper.o
CC aarch64-softmmu/target-arm/cpu.o
CC aarch64-softmmu/target-arm/neon_helper.o
CC aarch64-softmmu/target-arm/iwmmxt_helper.o
CC aarch64-softmmu/target-arm/gdbstub.o
CC aarch64-softmmu/target-arm/cpu64.o
CC aarch64-softmmu/target-arm/translate-a64.o
CC aarch64-softmmu/target-arm/helper-a64.o
In file included from /tmp/qemu-test/src/target-arm/arm-semi.c:118:
/tmp/qemu-test/src/include/exec/softmmu-arm-semi.h: In function ‘softmmu_unlock_user’:
/tmp/qemu-test/src/include/exec/softmmu-arm-semi.h:139: warning: unused variable ‘pc’
CC aarch64-softmmu/target-arm/gdbstub64.o
CC aarch64-softmmu/target-arm/crypto_helper.o
CC aarch64-softmmu/target-arm/arm-powerctl.o
GEN trace/generated-helpers.c
CC aarch64-softmmu/trace/control-target.o
CC aarch64-softmmu/gdbstub-xml.o
CC aarch64-softmmu/trace/generated-helpers.o
In file included from /tmp/qemu-test/src/target-arm/gdbstub.c:25:
/tmp/qemu-test/src/include/exec/softmmu-arm-semi.h: In function ‘softmmu_unlock_user’:
/tmp/qemu-test/src/include/exec/softmmu-arm-semi.h:139: warning: unused variable ‘pc’
/tmp/qemu-test/src/target-arm/gdbstub.c: At top level:
/tmp/qemu-test/src/include/exec/softmmu-arm-semi.h:106: warning: ‘softmmu_lock_user’ defined but not used
/tmp/qemu-test/src/include/exec/softmmu-arm-semi.h:118: warning: ‘softmmu_lock_user_string’ defined but not used
/tmp/qemu-test/src/include/exec/softmmu-arm-semi.h:136: warning: ‘softmmu_unlock_user’ defined but not used
LINK x86_64-softmmu/qemu-system-x86_64
/tmp/qemu-test/src/target-arm/translate-a64.c: In function ‘handle_shri_with_rndacc’:
/tmp/qemu-test/src/target-arm/translate-a64.c:6395: warning: ‘tcg_src_hi’ may be used uninitialized in this function
/tmp/qemu-test/src/target-arm/translate-a64.c: In function ‘disas_simd_scalar_two_reg_misc’:
/tmp/qemu-test/src/target-arm/translate-a64.c:8122: warning: ‘rmode’ may be used uninitialized in this function
LINK aarch64-softmmu/qemu-system-aarch64
TEST tests/qapi-schema/alternate-any.out
TEST tests/qapi-schema/alternate-array.out
TEST tests/qapi-schema/alternate-base.out
TEST tests/qapi-schema/alternate-clash.out
TEST tests/qapi-schema/alternate-conflict-dict.out
TEST tests/qapi-schema/alternate-conflict-string.out
TEST tests/qapi-schema/alternate-empty.out
TEST tests/qapi-schema/alternate-nested.out
TEST tests/qapi-schema/alternate-unknown.out
TEST tests/qapi-schema/args-alternate.out
TEST tests/qapi-schema/args-any.out
TEST tests/qapi-schema/args-array-empty.out
TEST tests/qapi-schema/args-array-unknown.out
TEST tests/qapi-schema/args-bad-boxed.out
TEST tests/qapi-schema/args-boxed-anon.out
TEST tests/qapi-schema/args-boxed-empty.out
TEST tests/qapi-schema/args-boxed-string.out
TEST tests/qapi-schema/args-int.out
TEST tests/qapi-schema/args-invalid.out
TEST tests/qapi-schema/args-member-array-bad.out
TEST tests/qapi-schema/args-member-case.out
TEST tests/qapi-schema/args-member-unknown.out
TEST tests/qapi-schema/args-name-clash.out
TEST tests/qapi-schema/args-union.out
TEST tests/qapi-schema/args-unknown.out
TEST tests/qapi-schema/bad-base.out
TEST tests/qapi-schema/bad-data.out
TEST tests/qapi-schema/bad-ident.out
TEST tests/qapi-schema/bad-type-bool.out
TEST tests/qapi-schema/bad-type-dict.out
TEST tests/qapi-schema/bad-type-int.out
TEST tests/qapi-schema/base-cycle-direct.out
TEST tests/qapi-schema/base-cycle-indirect.out
TEST tests/qapi-schema/command-int.out
TEST tests/qapi-schema/comments.out
TEST tests/qapi-schema/double-data.out
TEST tests/qapi-schema/double-type.out
TEST tests/qapi-schema/duplicate-key.out
TEST tests/qapi-schema/empty.out
TEST tests/qapi-schema/enum-bad-name.out
TEST tests/qapi-schema/enum-bad-prefix.out
TEST tests/qapi-schema/enum-clash-member.out
TEST tests/qapi-schema/enum-dict-member.out
TEST tests/qapi-schema/enum-member-case.out
TEST tests/qapi-schema/enum-int-member.out
TEST tests/qapi-schema/enum-missing-data.out
TEST tests/qapi-schema/enum-wrong-data.out
TEST tests/qapi-schema/escape-outside-string.out
TEST tests/qapi-schema/escape-too-big.out
TEST tests/qapi-schema/escape-too-short.out
TEST tests/qapi-schema/event-boxed-empty.out
TEST tests/qapi-schema/event-case.out
TEST tests/qapi-schema/event-nest-struct.out
TEST tests/qapi-schema/flat-union-array-branch.out
TEST tests/qapi-schema/flat-union-bad-base.out
TEST tests/qapi-schema/flat-union-bad-discriminator.out
TEST tests/qapi-schema/flat-union-base-any.out
TEST tests/qapi-schema/flat-union-base-union.out
TEST tests/qapi-schema/flat-union-clash-member.out
TEST tests/qapi-schema/flat-union-empty.out
TEST tests/qapi-schema/flat-union-incomplete-branch.out
TEST tests/qapi-schema/flat-union-int-branch.out
TEST tests/qapi-schema/flat-union-inline.out
TEST tests/qapi-schema/flat-union-invalid-branch-key.out
TEST tests/qapi-schema/flat-union-invalid-discriminator.out
TEST tests/qapi-schema/flat-union-no-base.out
TEST tests/qapi-schema/flat-union-optional-discriminator.out
TEST tests/qapi-schema/flat-union-string-discriminator.out
TEST tests/qapi-schema/funny-char.out
TEST tests/qapi-schema/ident-with-escape.out
TEST tests/qapi-schema/include-before-err.out
TEST tests/qapi-schema/include-cycle.out
TEST tests/qapi-schema/include-format-err.out
TEST tests/qapi-schema/include-no-file.out
TEST tests/qapi-schema/include-nested-err.out
TEST tests/qapi-schema/include-non-file.out
TEST tests/qapi-schema/include-relpath.out
TEST tests/qapi-schema/include-repetition.out
TEST tests/qapi-schema/include-self-cycle.out
TEST tests/qapi-schema/include-simple.out
TEST tests/qapi-schema/indented-expr.out
TEST tests/qapi-schema/leading-comma-list.out
TEST tests/qapi-schema/leading-comma-object.out
TEST tests/qapi-schema/missing-colon.out
TEST tests/qapi-schema/missing-comma-list.out
TEST tests/qapi-schema/missing-comma-object.out
TEST tests/qapi-schema/missing-type.out
TEST tests/qapi-schema/nested-struct-data.out
TEST tests/qapi-schema/non-objects.out
TEST tests/qapi-schema/qapi-schema-test.out
TEST tests/qapi-schema/quoted-structural-chars.out
TEST tests/qapi-schema/redefined-builtin.out
TEST tests/qapi-schema/redefined-command.out
TEST tests/qapi-schema/redefined-type.out
TEST tests/qapi-schema/redefined-event.out
TEST tests/qapi-schema/reserved-command-q.out
TEST tests/qapi-schema/reserved-enum-q.out
TEST tests/qapi-schema/reserved-member-has.out
TEST tests/qapi-schema/reserved-member-q.out
TEST tests/qapi-schema/reserved-member-u.out
TEST tests/qapi-schema/reserved-member-underscore.out
TEST tests/qapi-schema/reserved-type-kind.out
TEST tests/qapi-schema/reserved-type-list.out
TEST tests/qapi-schema/returns-alternate.out
TEST tests/qapi-schema/returns-array-bad.out
TEST tests/qapi-schema/returns-dict.out
TEST tests/qapi-schema/returns-unknown.out
TEST tests/qapi-schema/returns-whitelist.out
TEST tests/qapi-schema/struct-base-clash-deep.out
TEST tests/qapi-schema/struct-base-clash.out
TEST tests/qapi-schema/struct-data-invalid.out
TEST tests/qapi-schema/struct-member-invalid.out
TEST tests/qapi-schema/trailing-comma-list.out
TEST tests/qapi-schema/trailing-comma-object.out
TEST tests/qapi-schema/type-bypass-bad-gen.out
TEST tests/qapi-schema/unclosed-object.out
TEST tests/qapi-schema/unclosed-list.out
TEST tests/qapi-schema/unclosed-string.out
TEST tests/qapi-schema/unicode-str.out
TEST tests/qapi-schema/union-base-no-discriminator.out
TEST tests/qapi-schema/union-branch-case.out
TEST tests/qapi-schema/union-clash-branches.out
TEST tests/qapi-schema/union-empty.out
TEST tests/qapi-schema/union-invalid-base.out
TEST tests/qapi-schema/union-optional-branch.out
TEST tests/qapi-schema/union-unknown.out
TEST tests/qapi-schema/unknown-escape.out
TEST tests/qapi-schema/unknown-expr-key.out
CC tests/check-qdict.o
CC tests/test-char.o
CC tests/check-qfloat.o
CC tests/check-qlist.o
CC tests/check-qint.o
CC tests/check-qstring.o
CC tests/check-qnull.o
CC tests/check-qjson.o
CC tests/test-qobject-output-visitor.o
GEN tests/test-qapi-types.c
GEN tests/test-qapi-visit.c
GEN tests/test-qmp-introspect.c
GEN tests/test-qapi-event.c
CC tests/test-clone-visitor.o
CC tests/test-qobject-input-visitor.o
CC tests/test-qobject-input-strict.o
CC tests/test-qmp-commands.o
GEN tests/test-qmp-marshal.c
CC tests/test-string-input-visitor.o
CC tests/test-string-output-visitor.o
CC tests/test-qmp-event.o
CC tests/test-opts-visitor.o
CC tests/test-coroutine.o
CC tests/test-visitor-serialization.o
CC tests/test-throttle.o
CC tests/test-iov.o
CC tests/test-aio.o
CC tests/test-thread-pool.o
CC tests/test-hbitmap.o
CC tests/test-blockjob-txn.o
CC tests/test-x86-cpuid.o
CC tests/test-xbzrle.o
CC tests/test-blockjob.o
CC tests/test-vmstate.o
CC tests/test-cutils.o
CC tests/test-mul64.o
CC tests/test-int128.o
CC tests/test-rcu-list.o
CC tests/test-qdist.o
CC tests/rcutorture.o
CC tests/test-qht.o
CC tests/test-qht-par.o
CC tests/qht-bench.o
CC tests/check-qom-interface.o
/tmp/qemu-test/src/tests/test-int128.c:180: warning: ‘__noclone__’ attribute directive ignored
CC tests/test-bitops.o
CC tests/check-qom-proplist.o
CC tests/test-qemu-opts.o
CC tests/test-write-threshold.o
CC tests/test-crypto-hash.o
CC tests/test-crypto-secret.o
CC tests/test-crypto-cipher.o
CC tests/libqtest.o
CC tests/test-qga.o
CC tests/test-timed-average.o
CC tests/test-io-channel-socket.o
CC tests/test-io-task.o
CC tests/io-channel-helpers.o
CC tests/test-io-channel-file.o
CC tests/test-io-channel-command.o
CC tests/test-io-channel-buffer.o
CC tests/test-base64.o
CC tests/test-crypto-ivgen.o
CC tests/test-crypto-afsplit.o
CC tests/test-crypto-xts.o
CC tests/test-crypto-block.o
CC tests/test-replication.o
CC tests/test-logging.o
CC tests/test-bufferiszero.o
CC tests/test-uuid.o
CC tests/ptimer-test.o
CC tests/ptimer-test-stubs.o
CC tests/vhost-user-test.o
CC tests/libqos/pci.o
CC tests/libqos/fw_cfg.o
CC tests/libqos/malloc.o
CC tests/libqos/malloc-spapr.o
CC tests/libqos/libqos.o
CC tests/libqos/i2c.o
CC tests/libqos/libqos-spapr.o
CC tests/libqos/rtas.o
CC tests/libqos/pci-spapr.o
CC tests/libqos/malloc-pc.o
CC tests/libqos/pci-pc.o
CC tests/libqos/libqos-pc.o
CC tests/libqos/ahci.o
CC tests/libqos/virtio-pci.o
CC tests/libqos/virtio.o
CC tests/libqos/virtio-mmio.o
CC tests/libqos/malloc-generic.o
CC tests/endianness-test.o
CC tests/fdc-test.o
CC tests/ide-test.o
CC tests/ahci-test.o
CC tests/boot-order-test.o
CC tests/hd-geo-test.o
CC tests/bios-tables-test.o
CC tests/boot-sector.o
CC tests/pxe-test.o
CC tests/boot-serial-test.o
CC tests/ipmi-bt-test.o
CC tests/ipmi-kcs-test.o
CC tests/rtc-test.o
CC tests/i440fx-test.o
CC tests/fw_cfg-test.o
CC tests/wdt_ib700-test.o
CC tests/drive_del-test.o
CC tests/tco-test.o
/tmp/qemu-test/src/tests/ide-test.c: In function ‘cdrom_pio_impl’:
/tmp/qemu-test/src/tests/ide-test.c:791: warning: ignoring return value of ‘fwrite’, declared with attribute warn_unused_result
/tmp/qemu-test/src/tests/ide-test.c: In function ‘test_cdrom_dma’:
/tmp/qemu-test/src/tests/ide-test.c:886: warning: ignoring return value of ‘fwrite’, declared with attribute warn_unused_result
CC tests/e1000-test.o
CC tests/e1000e-test.o
CC tests/rtl8139-test.o
CC tests/pcnet-test.o
CC tests/eepro100-test.o
CC tests/ne2000-test.o
CC tests/ac97-test.o
CC tests/nvme-test.o
CC tests/virtio-net-test.o
CC tests/es1370-test.o
CC tests/virtio-blk-test.o
CC tests/virtio-balloon-test.o
CC tests/virtio-rng-test.o
CC tests/virtio-scsi-test.o
CC tests/virtio-serial-test.o
CC tests/virtio-console-test.o
CC tests/tpci200-test.o
CC tests/ipoctal232-test.o
CC tests/display-vga-test.o
CC tests/intel-hda-test.o
CC tests/ivshmem-test.o
CC tests/pvpanic-test.o
CC tests/vmxnet3-test.o
CC tests/i82801b11-test.o
CC tests/ioh3420-test.o
CC tests/usb-hcd-ohci-test.o
CC tests/libqos/usb.o
CC tests/usb-hcd-ehci-test.o
CC tests/usb-hcd-uhci-test.o
CC tests/usb-hcd-xhci-test.o
CC tests/pc-cpu-test.o
CC tests/q35-test.o
CC tests/test-netfilter.o
CC tests/test-filter-mirror.o
CC tests/test-filter-redirector.o
CC tests/postcopy-test.o
CC tests/test-x86-cpuid-compat.o
CC tests/device-introspect-test.o
CC tests/qom-test.o
LINK tests/check-qdict
LINK tests/test-char
LINK tests/check-qfloat
LINK tests/check-qint
LINK tests/check-qstring
LINK tests/check-qlist
LINK tests/check-qnull
LINK tests/check-qjson
CC tests/test-qapi-visit.o
CC tests/test-qapi-types.o
CC tests/test-qapi-event.o
CC tests/test-qmp-introspect.o
CC tests/test-qmp-marshal.o
LINK tests/test-coroutine
LINK tests/test-visitor-serialization
LINK tests/test-iov
LINK tests/test-aio
LINK tests/test-throttle
LINK tests/test-thread-pool
LINK tests/test-hbitmap
LINK tests/test-blockjob
LINK tests/test-blockjob-txn
LINK tests/test-x86-cpuid
LINK tests/test-xbzrle
LINK tests/test-vmstate
LINK tests/test-cutils
LINK tests/test-mul64
LINK tests/test-int128
LINK tests/rcutorture
LINK tests/test-rcu-list
LINK tests/test-qdist
LINK tests/test-qht
LINK tests/qht-bench
LINK tests/test-bitops
LINK tests/check-qom-interface
LINK tests/check-qom-proplist
LINK tests/test-qemu-opts
LINK tests/test-write-threshold
LINK tests/test-crypto-hash
LINK tests/test-crypto-cipher
LINK tests/test-crypto-secret
LINK tests/test-qga
LINK tests/test-timed-average
LINK tests/test-io-task
LINK tests/test-io-channel-socket
LINK tests/test-io-channel-file
LINK tests/test-io-channel-command
LINK tests/test-io-channel-buffer
LINK tests/test-base64
LINK tests/test-crypto-ivgen
LINK tests/test-crypto-afsplit
LINK tests/test-crypto-xts
LINK tests/test-crypto-block
LINK tests/test-logging
LINK tests/test-replication
LINK tests/test-bufferiszero
LINK tests/test-uuid
LINK tests/ptimer-test
LINK tests/vhost-user-test
LINK tests/endianness-test
LINK tests/fdc-test
LINK tests/ide-test
LINK tests/ahci-test
LINK tests/hd-geo-test
LINK tests/boot-order-test
LINK tests/bios-tables-test
LINK tests/boot-serial-test
LINK tests/pxe-test
LINK tests/rtc-test
LINK tests/ipmi-kcs-test
LINK tests/ipmi-bt-test
LINK tests/i440fx-test
LINK tests/fw_cfg-test
LINK tests/drive_del-test
LINK tests/wdt_ib700-test
LINK tests/tco-test
LINK tests/e1000-test
LINK tests/e1000e-test
LINK tests/rtl8139-test
LINK tests/pcnet-test
LINK tests/eepro100-test
LINK tests/ne2000-test
LINK tests/nvme-test
LINK tests/ac97-test
LINK tests/es1370-test
LINK tests/virtio-net-test
LINK tests/virtio-balloon-test
LINK tests/virtio-blk-test
LINK tests/virtio-rng-test
LINK tests/virtio-scsi-test
LINK tests/virtio-serial-test
LINK tests/virtio-console-test
LINK tests/tpci200-test
LINK tests/ipoctal232-test
LINK tests/display-vga-test
LINK tests/intel-hda-test
LINK tests/ivshmem-test
LINK tests/vmxnet3-test
LINK tests/pvpanic-test
LINK tests/i82801b11-test
LINK tests/ioh3420-test
LINK tests/usb-hcd-ohci-test
LINK tests/usb-hcd-uhci-test
LINK tests/usb-hcd-ehci-test
LINK tests/usb-hcd-xhci-test
LINK tests/pc-cpu-test
LINK tests/q35-test
LINK tests/test-netfilter
LINK tests/test-filter-mirror
LINK tests/test-filter-redirector
LINK tests/postcopy-test
LINK tests/test-x86-cpuid-compat
LINK tests/device-introspect-test
LINK tests/qom-test
GTESTER tests/check-qdict
GTESTER tests/test-char
GTESTER tests/check-qfloat
GTESTER tests/check-qint
GTESTER tests/check-qstring
GTESTER tests/check-qlist
GTESTER tests/check-qnull
GTESTER tests/check-qjson
LINK tests/test-qobject-output-visitor
LINK tests/test-clone-visitor
LINK tests/test-qobject-input-visitor
LINK tests/test-qobject-input-strict
LINK tests/test-qmp-commands
LINK tests/test-string-input-visitor
LINK tests/test-string-output-visitor
LINK tests/test-qmp-event
LINK tests/test-opts-visitor
GTESTER tests/test-coroutine
GTESTER tests/test-visitor-serialization
GTESTER tests/test-iov
GTESTER tests/test-hbitmap
GTESTER tests/test-aio
GTESTER tests/test-throttle
GTESTER tests/test-thread-pool
GTESTER tests/test-blockjob
GTESTER tests/test-blockjob-txn
GTESTER tests/test-x86-cpuid
GTESTER tests/test-xbzrle
GTESTER tests/test-vmstate
GTESTER tests/test-cutils
GTESTER tests/test-mul64
GTESTER tests/test-int128
Failed to load simple/primitive:b_1
Failed to load simple/primitive:i64_2
Failed to load simple/primitive:i32_1
Failed to load simple/primitive:i32_1
GTESTER tests/rcutorture
GTESTER tests/test-rcu-list
GTESTER tests/test-qdist
GTESTER tests/test-qht
LINK tests/test-qht-par
GTESTER tests/test-bitops
GTESTER tests/check-qom-interface
GTESTER tests/check-qom-proplist
GTESTER tests/test-qemu-opts
GTESTER tests/test-write-threshold
GTESTER tests/test-crypto-hash
GTESTER tests/test-crypto-cipher
GTESTER tests/test-crypto-secret
GTESTER tests/test-qga
GTESTER tests/test-timed-average
GTESTER tests/test-io-task
GTESTER tests/test-io-channel-file
GTESTER tests/test-io-channel-socket
GTESTER tests/test-io-channel-command
GTESTER tests/test-io-channel-buffer
GTESTER tests/test-base64
GTESTER tests/test-crypto-ivgen
GTESTER tests/test-crypto-afsplit
GTESTER tests/test-crypto-xts
GTESTER tests/test-crypto-block
GTESTER tests/test-logging
GTESTER tests/test-replication
GTESTER tests/test-bufferiszero
GTESTER tests/test-uuid
GTESTER tests/ptimer-test
GTESTER check-qtest-x86_64
GTESTER check-qtest-aarch64
GTESTER tests/test-qobject-output-visitor
GTESTER tests/test-clone-visitor
GTESTER tests/test-qobject-input-visitor
GTESTER tests/test-qobject-input-strict
GTESTER tests/test-qmp-commands
GTESTER tests/test-string-input-visitor
GTESTER tests/test-string-output-visitor
GTESTER tests/test-qmp-event
GTESTER tests/test-opts-visitor
GTESTER tests/test-qht-par
ftruncate: Permission denied
ftruncate: Permission denied
ftruncate: Permission denied
**
ERROR:/tmp/qemu-test/src/tests/vhost-user-test.c:668:test_migrate: assertion failed: (qdict_haskey(rsp, "return"))
GTester: last random seed: R02Seccd902967207816906b699912cedc1e
ftruncate: Permission denied
ftruncate: Permission denied
Could not access KVM kernel module: No such file or directory
failed to initialize KVM: No such file or directory
Back to tcg accelerator.
Could not access KVM kernel module: No such file or directory
failed to initialize KVM: No such file or directory
Back to tcg accelerator.
Could not access KVM kernel module: No such file or directory
failed to initialize KVM: No such file or directory
Back to tcg accelerator.
Could not access KVM kernel module: No such file or directory
failed to initialize KVM: No such file or directory
Back to tcg accelerator.
Could not access KVM kernel module: No such file or directory
failed to initialize KVM: No such file or directory
Back to tcg accelerator.
Could not access KVM kernel module: No such file or directory
failed to initialize KVM: No such file or directory
Back to tcg accelerator.
Could not access KVM kernel module: No such file or directory
failed to initialize KVM: No such file or directory
Back to tcg accelerator.
Could not access KVM kernel module: No such file or directory
failed to initialize KVM: No such file or directory
Back to tcg accelerator.
Could not access KVM kernel module: No such file or directory
failed to initialize KVM: No such file or directory
Back to tcg accelerator.
Could not access KVM kernel module: No such file or directory
failed to initialize KVM: No such file or directory
Back to tcg accelerator.
make[1]: Leaving directory `/var/tmp/patchew-tester-tmp-pb3qxzah/src'
BUILD fedora
make[1]: Entering directory `/var/tmp/patchew-tester-tmp-pb3qxzah/src'
ARCHIVE qemu.tgz
ARCHIVE dtc.tgz
COPY RUNNER
RUN test-mingw in qemu:fedora
Packages installed:
PyYAML-3.11-12.fc24.x86_64
SDL-devel-1.2.15-21.fc24.x86_64
bc-1.06.95-16.fc24.x86_64
bison-3.0.4-4.fc24.x86_64
ccache-3.3.2-1.fc24.x86_64
clang-3.8.0-2.fc24.x86_64
findutils-4.6.0-7.fc24.x86_64
flex-2.6.0-2.fc24.x86_64
gcc-6.2.1-2.fc24.x86_64
gcc-c++-6.2.1-2.fc24.x86_64
git-2.7.4-3.fc24.x86_64
glib2-devel-2.48.2-1.fc24.x86_64
libfdt-devel-1.4.2-1.fc24.x86_64
make-4.1-5.fc24.x86_64
mingw32-SDL-1.2.15-7.fc24.noarch
mingw32-bzip2-1.0.6-7.fc24.noarch
mingw32-curl-7.47.0-1.fc24.noarch
mingw32-glib2-2.48.2-1.fc24.noarch
mingw32-gmp-6.1.0-1.fc24.noarch
mingw32-gnutls-3.4.14-1.fc24.noarch
mingw32-gtk2-2.24.31-1.fc24.noarch
mingw32-gtk3-3.20.9-1.fc24.noarch
mingw32-libjpeg-turbo-1.5.0-1.fc24.noarch
mingw32-libpng-1.6.23-1.fc24.noarch
mingw32-libssh2-1.4.3-5.fc24.noarch
mingw32-libtasn1-4.5-2.fc24.noarch
mingw32-nettle-3.2-1.fc24.noarch
mingw32-pixman-0.34.0-1.fc24.noarch
mingw32-pkg-config-0.28-6.fc24.x86_64
mingw64-SDL-1.2.15-7.fc24.noarch
mingw64-bzip2-1.0.6-7.fc24.noarch
mingw64-curl-7.47.0-1.fc24.noarch
mingw64-glib2-2.48.2-1.fc24.noarch
mingw64-gmp-6.1.0-1.fc24.noarch
mingw64-gnutls-3.4.14-1.fc24.noarch
mingw64-gtk2-2.24.31-1.fc24.noarch
mingw64-gtk3-3.20.9-1.fc24.noarch
mingw64-libjpeg-turbo-1.5.0-1.fc24.noarch
mingw64-libpng-1.6.23-1.fc24.noarch
mingw64-libssh2-1.4.3-5.fc24.noarch
mingw64-libtasn1-4.5-2.fc24.noarch
mingw64-nettle-3.2-1.fc24.noarch
mingw64-pixman-0.34.0-1.fc24.noarch
mingw64-pkg-config-0.28-6.fc24.x86_64
perl-5.22.2-362.fc24.x86_64
pixman-devel-0.34.0-2.fc24.x86_64
sparse-0.5.0-7.fc24.x86_64
tar-1.28-7.fc24.x86_64
which-2.20-13.fc24.x86_64
zlib-devel-1.2.8-10.fc24.x86_64
Environment variables:
PACKAGES=ccache git tar PyYAML sparse flex bison glib2-devel pixman-devel zlib-devel SDL-devel libfdt-devel gcc gcc-c++ clang make perl which bc findutils mingw32-pixman mingw32-glib2 mingw32-gmp mingw32-SDL mingw32-pkg-config mingw32-gtk2 mingw32-gtk3 mingw32-gnutls mingw32-nettle mingw32-libtasn1 mingw32-libjpeg-turbo mingw32-libpng mingw32-curl mingw32-libssh2 mingw32-bzip2 mingw64-pixman mingw64-glib2 mingw64-gmp mingw64-SDL mingw64-pkg-config mingw64-gtk2 mingw64-gtk3 mingw64-gnutls mingw64-nettle mingw64-libtasn1 mingw64-libjpeg-turbo mingw64-libpng mingw64-curl mingw64-libssh2 mingw64-bzip2
HOSTNAME=
TERM=xterm
MAKEFLAGS= -j16
HISTSIZE=1000
J=16
USER=root
CCACHE_DIR=/var/tmp/ccache
EXTRA_CONFIGURE_OPTS=
V=
SHOW_ENV=1
MAIL=/var/spool/mail/root
PATH=/usr/lib/ccache:/usr/lib64/ccache:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin
PWD=/
TARGET_LIST=
HISTCONTROL=ignoredups
SHLVL=1
HOME=/root
TEST_DIR=/tmp/qemu-test
LOGNAME=root
LESSOPEN=||/usr/bin/lesspipe.sh %s
FEATURES=mingw clang pyyaml dtc
DEBUG=
_=/usr/bin/env
Configure options:
--enable-werror --target-list=x86_64-softmmu,aarch64-softmmu --prefix=/var/tmp/qemu-build/install --cross-prefix=x86_64-w64-mingw32- --enable-trace-backends=simple --enable-debug --enable-gnutls --enable-nettle --enable-curl --enable-vnc --enable-bzip2 --enable-guest-agent --with-sdlabi=1.2 --with-gtkabi=2.0
Install prefix /var/tmp/qemu-build/install
BIOS directory /var/tmp/qemu-build/install
binary directory /var/tmp/qemu-build/install
library directory /var/tmp/qemu-build/install/lib
module directory /var/tmp/qemu-build/install/lib
libexec directory /var/tmp/qemu-build/install/libexec
include directory /var/tmp/qemu-build/install/include
config directory /var/tmp/qemu-build/install
local state directory queried at runtime
Windows SDK no
Source path /tmp/qemu-test/src
C compiler x86_64-w64-mingw32-gcc
Host C compiler cc
C++ compiler x86_64-w64-mingw32-g++
Objective-C compiler clang
ARFLAGS rv
CFLAGS -g
QEMU_CFLAGS -I/usr/x86_64-w64-mingw32/sys-root/mingw/include/pixman-1 -I$(SRC_PATH)/dtc/libfdt -Werror -mms-bitfields -I/usr/x86_64-w64-mingw32/sys-root/mingw/include/glib-2.0 -I/usr/x86_64-w64-mingw32/sys-root/mingw/lib/glib-2.0/include -I/usr/x86_64-w64-mingw32/sys-root/mingw/include -m64 -mcx16 -mthreads -D__USE_MINGW_ANSI_STDIO=1 -DWIN32_LEAN_AND_MEAN -DWINVER=0x501 -D_GNU_SOURCE -D_FILE_OFFSET_BITS=64 -D_LARGEFILE_SOURCE -Wstrict-prototypes -Wredundant-decls -Wall -Wundef -Wwrite-strings -Wmissing-prototypes -fno-strict-aliasing -fno-common -fwrapv -Wendif-labels -Wno-shift-negative-value -Wmissing-include-dirs -Wempty-body -Wnested-externs -Wformat-security -Wformat-y2k -Winit-self -Wignored-qualifiers -Wold-style-declaration -Wold-style-definition -Wtype-limits -fstack-protector-strong -I/usr/x86_64-w64-mingw32/sys-root/mingw/include -I/usr/x86_64-w64-mingw32/sys-root/mingw/include/p11-kit-1 -I/usr/x86_64-w64-mingw32/sys-root/mingw/include -I/usr/x86_64-w64-mingw32/sys-root/mingw/include -I/usr/x86_64-w64-mingw32/sys-root/mingw/include/libpng16
LDFLAGS -Wl,--nxcompat -Wl,--no-seh -Wl,--dynamicbase -Wl,--warn-common -m64 -g
make make
install install
python python -B
smbd /usr/sbin/smbd
module support no
host CPU x86_64
host big endian no
target list x86_64-softmmu aarch64-softmmu
tcg debug enabled yes
gprof enabled no
sparse enabled no
strip binaries no
profiler no
static build no
pixman system
SDL support yes (1.2.15)
GTK support yes (2.24.31)
GTK GL support no
VTE support no
TLS priority NORMAL
GNUTLS support yes
GNUTLS rnd yes
libgcrypt no
libgcrypt kdf no
nettle yes (3.2)
nettle kdf yes
libtasn1 yes
curses support no
virgl support no
curl support yes
mingw32 support yes
Audio drivers dsound
Block whitelist (rw)
Block whitelist (ro)
VirtFS support no
VNC support yes
VNC SASL support no
VNC JPEG support yes
VNC PNG support yes
xen support no
brlapi support no
bluez support no
Documentation no
PIE no
vde support no
netmap support no
Linux AIO support no
ATTR/XATTR support no
Install blobs yes
KVM support no
COLO support yes
RDMA support no
TCG interpreter no
fdt support yes
preadv support no
fdatasync no
madvise no
posix_madvise no
libcap-ng support no
vhost-net support no
vhost-scsi support no
vhost-vsock support no
Trace backends simple
Trace output file trace-<pid>
spice support no
rbd support no
xfsctl support no
smartcard support no
libusb no
usb net redir no
OpenGL support no
OpenGL dmabufs no
libiscsi support no
libnfs support no
build guest agent yes
QGA VSS support no
QGA w32 disk info yes
QGA MSI support no
seccomp support no
coroutine backend win32
coroutine pool yes
debug stack usage no
GlusterFS support no
Archipelago support no
gcov gcov
gcov enabled no
TPM support yes
libssh2 support yes
TPM passthrough no
QOM debugging yes
lzo support no
snappy support no
bzip2 support yes
NUMA host support no
tcmalloc support no
jemalloc support no
avx2 optimization yes
replication support yes
GEN x86_64-softmmu/config-devices.mak.tmp
mkdir -p dtc/libfdt
mkdir -p dtc/tests
GEN aarch64-softmmu/config-devices.mak.tmp
GEN config-host.h
GEN qemu-options.def
GEN qmp-commands.h
GEN qapi-types.h
GEN qapi-visit.h
GEN qapi-event.h
GEN qmp-introspect.h
GEN module_block.h
GEN tests/test-qapi-types.h
GEN tests/test-qapi-visit.h
GEN tests/test-qmp-commands.h
GEN tests/test-qapi-event.h
GEN tests/test-qmp-introspect.h
GEN x86_64-softmmu/config-devices.mak
GEN aarch64-softmmu/config-devices.mak
GEN trace/generated-tracers.h
DEP /tmp/qemu-test/src/dtc/tests/dumptrees.c
GEN trace/generated-tcg-tracers.h
GEN trace/generated-helpers-wrappers.h
GEN trace/generated-helpers.h
DEP /tmp/qemu-test/src/dtc/tests/trees.S
DEP /tmp/qemu-test/src/dtc/tests/testutils.c
DEP /tmp/qemu-test/src/dtc/tests/value-labels.c
DEP /tmp/qemu-test/src/dtc/tests/asm_tree_dump.c
GEN config-all-devices.mak
DEP /tmp/qemu-test/src/dtc/tests/truncated_property.c
DEP /tmp/qemu-test/src/dtc/tests/subnode_iterate.c
DEP /tmp/qemu-test/src/dtc/tests/integer-expressions.c
DEP /tmp/qemu-test/src/dtc/tests/utilfdt_test.c
DEP /tmp/qemu-test/src/dtc/tests/path_offset_aliases.c
DEP /tmp/qemu-test/src/dtc/tests/add_subnode_with_nops.c
DEP /tmp/qemu-test/src/dtc/tests/dtbs_equal_unordered.c
DEP /tmp/qemu-test/src/dtc/tests/dtb_reverse.c
DEP /tmp/qemu-test/src/dtc/tests/dtbs_equal_ordered.c
DEP /tmp/qemu-test/src/dtc/tests/extra-terminating-null.c
DEP /tmp/qemu-test/src/dtc/tests/incbin.c
DEP /tmp/qemu-test/src/dtc/tests/phandle_format.c
DEP /tmp/qemu-test/src/dtc/tests/boot-cpuid.c
DEP /tmp/qemu-test/src/dtc/tests/path-references.c
DEP /tmp/qemu-test/src/dtc/tests/references.c
DEP /tmp/qemu-test/src/dtc/tests/string_escapes.c
DEP /tmp/qemu-test/src/dtc/tests/propname_escapes.c
DEP /tmp/qemu-test/src/dtc/tests/appendprop2.c
DEP /tmp/qemu-test/src/dtc/tests/appendprop1.c
DEP /tmp/qemu-test/src/dtc/tests/del_node.c
DEP /tmp/qemu-test/src/dtc/tests/del_property.c
DEP /tmp/qemu-test/src/dtc/tests/setprop.c
DEP /tmp/qemu-test/src/dtc/tests/set_name.c
DEP /tmp/qemu-test/src/dtc/tests/rw_tree1.c
DEP /tmp/qemu-test/src/dtc/tests/nopulate.c
DEP /tmp/qemu-test/src/dtc/tests/open_pack.c
DEP /tmp/qemu-test/src/dtc/tests/mangle-layout.c
DEP /tmp/qemu-test/src/dtc/tests/move_and_save.c
DEP /tmp/qemu-test/src/dtc/tests/sw_tree1.c
DEP /tmp/qemu-test/src/dtc/tests/nop_node.c
DEP /tmp/qemu-test/src/dtc/tests/nop_property.c
DEP /tmp/qemu-test/src/dtc/tests/setprop_inplace.c
DEP /tmp/qemu-test/src/dtc/tests/notfound.c
DEP /tmp/qemu-test/src/dtc/tests/sized_cells.c
DEP /tmp/qemu-test/src/dtc/tests/char_literal.c
DEP /tmp/qemu-test/src/dtc/tests/get_alias.c
DEP /tmp/qemu-test/src/dtc/tests/node_check_compatible.c
DEP /tmp/qemu-test/src/dtc/tests/node_offset_by_compatible.c
DEP /tmp/qemu-test/src/dtc/tests/node_offset_by_phandle.c
DEP /tmp/qemu-test/src/dtc/tests/node_offset_by_prop_value.c
DEP /tmp/qemu-test/src/dtc/tests/parent_offset.c
DEP /tmp/qemu-test/src/dtc/tests/supernode_atdepth_offset.c
DEP /tmp/qemu-test/src/dtc/tests/get_path.c
DEP /tmp/qemu-test/src/dtc/tests/get_phandle.c
DEP /tmp/qemu-test/src/dtc/tests/getprop.c
DEP /tmp/qemu-test/src/dtc/tests/get_name.c
DEP /tmp/qemu-test/src/dtc/tests/path_offset.c
DEP /tmp/qemu-test/src/dtc/tests/subnode_offset.c
DEP /tmp/qemu-test/src/dtc/tests/find_property.c
DEP /tmp/qemu-test/src/dtc/tests/root_node.c
DEP /tmp/qemu-test/src/dtc/tests/get_mem_rsv.c
DEP /tmp/qemu-test/src/dtc/libfdt/fdt_empty_tree.c
DEP /tmp/qemu-test/src/dtc/libfdt/fdt_strerror.c
DEP /tmp/qemu-test/src/dtc/libfdt/fdt_rw.c
DEP /tmp/qemu-test/src/dtc/libfdt/fdt_sw.c
DEP /tmp/qemu-test/src/dtc/libfdt/fdt_wip.c
DEP /tmp/qemu-test/src/dtc/libfdt/fdt_ro.c
DEP /tmp/qemu-test/src/dtc/libfdt/fdt.c
DEP /tmp/qemu-test/src/dtc/util.c
DEP /tmp/qemu-test/src/dtc/fdtput.c
DEP /tmp/qemu-test/src/dtc/fdtget.c
DEP /tmp/qemu-test/src/dtc/fdtdump.c
DEP /tmp/qemu-test/src/dtc/srcpos.c
LEX convert-dtsv0-lexer.lex.c
BISON dtc-parser.tab.c
LEX dtc-lexer.lex.c
DEP /tmp/qemu-test/src/dtc/treesource.c
DEP /tmp/qemu-test/src/dtc/livetree.c
DEP /tmp/qemu-test/src/dtc/fstree.c
DEP /tmp/qemu-test/src/dtc/flattree.c
DEP /tmp/qemu-test/src/dtc/data.c
DEP /tmp/qemu-test/src/dtc/dtc.c
DEP /tmp/qemu-test/src/dtc/checks.c
DEP convert-dtsv0-lexer.lex.c
DEP dtc-parser.tab.c
DEP dtc-lexer.lex.c
CHK version_gen.h
UPD version_gen.h
DEP /tmp/qemu-test/src/dtc/util.c
CC libfdt/fdt.o
CC libfdt/fdt_ro.o
CC libfdt/fdt_wip.o
CC libfdt/fdt_sw.o
CC libfdt/fdt_rw.o
CC libfdt/fdt_strerror.o
CC libfdt/fdt_empty_tree.o
AR libfdt/libfdt.a
x86_64-w64-mingw32-ar: creating libfdt/libfdt.a
a - libfdt/fdt.o
a - libfdt/fdt_ro.o
a - libfdt/fdt_wip.o
a - libfdt/fdt_sw.o
a - libfdt/fdt_rw.o
a - libfdt/fdt_strerror.o
a - libfdt/fdt_empty_tree.o
RC version.lo
RC version.o
GEN qga/qapi-generated/qga-qapi-types.h
GEN qga/qapi-generated/qga-qapi-visit.h
GEN qga/qapi-generated/qga-qmp-commands.h
GEN qga/qapi-generated/qga-qapi-types.c
GEN qga/qapi-generated/qga-qapi-visit.c
GEN qga/qapi-generated/qga-qmp-marshal.c
GEN qmp-introspect.c
GEN qapi-types.c
GEN qapi-visit.c
GEN qapi-event.c
CC qapi/qapi-visit-core.o
CC qapi/qapi-dealloc-visitor.o
CC qapi/qobject-input-visitor.o
CC qapi/qobject-output-visitor.o
CC qapi/qmp-registry.o
CC qapi/qmp-dispatch.o
CC qapi/string-input-visitor.o
CC qapi/string-output-visitor.o
CC qapi/opts-visitor.o
CC qapi/qapi-clone-visitor.o
CC qapi/qmp-event.o
CC qapi/qapi-util.o
CC qobject/qnull.o
CC qobject/qint.o
CC qobject/qstring.o
CC qobject/qdict.o
CC qobject/qlist.o
CC qobject/qfloat.o
CC qobject/qbool.o
CC qobject/qjson.o
CC qobject/qobject.o
CC qobject/json-lexer.o
CC qobject/json-streamer.o
CC qobject/json-parser.o
GEN trace/generated-tracers.c
CC trace/simple.o
CC trace/control.o
CC trace/qmp.o
CC util/osdep.o
CC util/cutils.o
CC util/unicode.o
CC util/qemu-timer-common.o
CC util/bufferiszero.o
CC util/event_notifier-win32.o
CC util/oslib-win32.o
CC util/qemu-thread-win32.o
CC util/envlist.o
CC util/path.o
CC util/module.o
CC util/bitmap.o
CC util/bitops.o
CC util/hbitmap.o
CC util/fifo8.o
CC util/acl.o
CC util/error.o
CC util/qemu-error.o
CC util/id.o
CC util/iov.o
CC util/qemu-config.o
CC util/qemu-sockets.o
CC util/notify.o
CC util/uri.o
CC util/qemu-option.o
CC util/qemu-progress.o
CC util/hexdump.o
CC util/crc32c.o
CC util/uuid.o
CC util/throttle.o
CC util/getauxval.o
CC util/readline.o
CC util/qemu-coroutine.o
CC util/rcu.o
CC util/qemu-coroutine-lock.o
CC util/qemu-coroutine-io.o
CC util/qemu-coroutine-sleep.o
CC util/coroutine-win32.o
CC util/buffer.o
CC util/timed-average.o
CC util/base64.o
CC util/log.o
CC util/qdist.o
CC util/qht.o
CC util/range.o
CC crypto/pbkdf-stub.o
CC stubs/arch-query-cpu-def.o
CC stubs/arch-query-cpu-model-expansion.o
CC stubs/arch-query-cpu-model-comparison.o
CC stubs/arch-query-cpu-model-baseline.o
CC stubs/bdrv-next-monitor-owned.o
CC stubs/blk-commit-all.o
CC stubs/blockdev-close-all-bdrv-states.o
CC stubs/clock-warp.o
CC stubs/cpu-get-clock.o
CC stubs/cpu-get-icount.o
CC stubs/dump.o
CC stubs/fdset-add-fd.o
CC stubs/fdset-find-fd.o
CC stubs/fdset-get-fd.o
CC stubs/fdset-remove-fd.o
CC stubs/gdbstub.o
CC stubs/get-next-serial.o
CC stubs/get-fd.o
CC stubs/get-vm-name.o
CC stubs/iothread.o
CC stubs/iothread-lock.o
CC stubs/is-daemonized.o
CC stubs/machine-init-done.o
CC stubs/migr-blocker.o
CC stubs/mon-is-qmp.o
CC stubs/mon-printf.o
CC stubs/monitor-init.o
CC stubs/notify-event.o
CC stubs/qtest.o
CC stubs/replay.o
CC stubs/replay-user.o
CC stubs/reset.o
CC stubs/runstate-check.o
CC stubs/set-fd-handler.o
CC stubs/slirp.o
CC stubs/sysbus.o
CC stubs/trace-control.o
CC stubs/uuid.o
CC stubs/vm-stop.o
CC stubs/vmstate.o
CC stubs/fd-register.o
CC stubs/cpus.o
CC stubs/kvm.o
CC stubs/qmp_pc_dimm_device_list.o
CC stubs/target-monitor-defs.o
CC stubs/target-get-monitor-def.o
CC stubs/vhost.o
CC stubs/iohandler.o
CC stubs/smbios_type_38.o
CC stubs/ipmi.o
CC stubs/pc_madt_cpu_entry.o
CC stubs/migration-colo.o
GEN qemu-img-cmds.h
CC async.o
CC thread-pool.o
CC block.o
CC blockjob.o
CC main-loop.o
CC iohandler.o
CC qemu-timer.o
CC aio-win32.o
CC qemu-io-cmds.o
CC replication.o
CC block/raw_bsd.o
CC block/qcow.o
CC block/vdi.o
CC block/vmdk.o
CC block/cloop.o
CC block/bochs.o
CC block/vpc.o
CC block/vvfat.o
CC block/dmg.o
CC block/qcow2.o
CC block/qcow2-refcount.o
CC block/qcow2-cluster.o
CC block/qcow2-snapshot.o
CC block/qed.o
CC block/qcow2-cache.o
CC block/qed-gencb.o
CC block/qed-l2-cache.o
CC block/qed-table.o
CC block/qed-cluster.o
CC block/qed-check.o
CC block/vhdx.o
CC block/vhdx-endian.o
CC block/vhdx-log.o
CC block/quorum.o
CC block/parallels.o
CC block/blkdebug.o
CC block/blkverify.o
CC block/blkreplay.o
CC block/block-backend.o
CC block/snapshot.o
CC block/qapi.o
CC block/raw-win32.o
CC block/win32-aio.o
CC block/null.o
CC block/mirror.o
CC block/commit.o
CC block/io.o
CC block/throttle-groups.o
CC block/nbd.o
CC block/nbd-client.o
CC block/sheepdog.o
CC block/accounting.o
CC block/dirty-bitmap.o
CC block/write-threshold.o
CC block/backup.o
CC block/replication.o
CC block/crypto.o
CC nbd/server.o
CC nbd/client.o
CC nbd/common.o
CC block/curl.o
CC block/ssh.o
CC block/dmg-bz2.o
CC crypto/init.o
CC crypto/hash.o
CC crypto/hash-nettle.o
CC crypto/aes.o
CC crypto/desrfb.o
CC crypto/cipher.o
CC crypto/tlscreds.o
CC crypto/tlscredsanon.o
CC crypto/tlscredsx509.o
CC crypto/tlssession.o
CC crypto/secret.o
CC crypto/random-gnutls.o
CC crypto/pbkdf.o
CC crypto/pbkdf-nettle.o
CC crypto/ivgen.o
CC crypto/ivgen-essiv.o
CC crypto/ivgen-plain.o
CC crypto/ivgen-plain64.o
CC crypto/afsplit.o
CC crypto/xts.o
CC crypto/block.o
CC crypto/block-qcow.o
CC crypto/block-luks.o
CC io/channel.o
CC io/channel-buffer.o
CC io/channel-command.o
CC io/channel-file.o
CC io/channel-socket.o
CC io/channel-tls.o
CC io/channel-watch.o
CC io/channel-websock.o
CC io/channel-util.o
CC io/task.o
CC qom/object.o
CC qom/container.o
CC qom/qom-qobject.o
CC qom/object_interfaces.o
CC qemu-io.o
CC blockdev.o
CC blockdev-nbd.o
CC iothread.o
CC qdev-monitor.o
CC device-hotplug.o
CC os-win32.o
CC qemu-char.o
CC page_cache.o
CC accel.o
CC bt-host.o
CC bt-vhci.o
CC dma-helpers.o
CC vl.o
CC tpm.o
CC device_tree.o
GEN qmp-marshal.c
CC qmp.o
CC hmp.o
CC cpus-common.o
CC audio/audio.o
CC audio/noaudio.o
CC audio/wavaudio.o
CC audio/mixeng.o
CC audio/sdlaudio.o
CC audio/dsoundaudio.o
CC audio/audio_win_int.o
CC audio/wavcapture.o
CC backends/rng.o
CC backends/rng-egd.o
CC backends/msmouse.o
CC backends/testdev.o
CC backends/tpm.o
CC backends/hostmem.o
CC backends/hostmem-ram.o
CC block/stream.o
CC disas/arm.o
CXX disas/arm-a64.o
CC disas/i386.o
CXX disas/libvixl/vixl/utils.o
CXX disas/libvixl/vixl/compiler-intrinsics.o
CXX disas/libvixl/vixl/a64/instructions-a64.o
CXX disas/libvixl/vixl/a64/decoder-a64.o
CXX disas/libvixl/vixl/a64/disasm-a64.o
CC hw/acpi/core.o
CC hw/acpi/piix4.o
CC hw/acpi/pcihp.o
CC hw/acpi/ich9.o
CC hw/acpi/tco.o
CC hw/acpi/cpu_hotplug.o
CC hw/acpi/memory_hotplug.o
CC hw/acpi/memory_hotplug_acpi_table.o
CC hw/acpi/cpu.o
CC hw/acpi/acpi_interface.o
CC hw/acpi/bios-linker-loader.o
CC hw/acpi/aml-build.o
CC hw/acpi/ipmi.o
CC hw/audio/sb16.o
CC hw/audio/es1370.o
CC hw/audio/ac97.o
CC hw/audio/fmopl.o
CC hw/audio/adlib.o
CC hw/audio/gus.o
CC hw/audio/gusemu_hal.o
CC hw/audio/gusemu_mixer.o
CC hw/audio/cs4231a.o
CC hw/audio/intel-hda.o
CC hw/audio/hda-codec.o
CC hw/audio/pcspk.o
CC hw/audio/wm8750.o
CC hw/audio/pl041.o
CC hw/audio/lm4549.o
CC hw/audio/marvell_88w8618.o
CC hw/block/block.o
CC hw/block/cdrom.o
CC hw/block/hd-geometry.o
CC hw/block/fdc.o
CC hw/block/m25p80.o
CC hw/block/nand.o
CC hw/block/pflash_cfi01.o
CC hw/block/pflash_cfi02.o
CC hw/block/ecc.o
CC hw/block/onenand.o
CC hw/block/nvme.o
CC hw/bt/core.o
CC hw/bt/l2cap.o
CC hw/bt/sdp.o
CC hw/bt/hci.o
CC hw/bt/hid.o
CC hw/bt/hci-csr.o
CC hw/char/ipoctal232.o
CC hw/char/parallel.o
CC hw/char/pl011.o
CC hw/char/serial.o
CC hw/char/serial-isa.o
CC hw/char/serial-pci.o
CC hw/char/virtio-console.o
CC hw/char/cadence_uart.o
CC hw/char/debugcon.o
CC hw/char/imx_serial.o
CC hw/core/qdev.o
CC hw/core/qdev-properties.o
CC hw/core/bus.o
CC hw/core/fw-path-provider.o
CC hw/core/irq.o
CC hw/core/hotplug.o
CC hw/core/ptimer.o
CC hw/core/sysbus.o
CC hw/core/machine.o
CC hw/core/null-machine.o
CC hw/core/loader.o
CC hw/core/qdev-properties-system.o
CC hw/core/register.o
CC hw/core/or-irq.o
CC hw/core/platform-bus.o
CC hw/display/ads7846.o
CC hw/display/cirrus_vga.o
CC hw/display/pl110.o
CC hw/display/ssd0303.o
CC hw/display/ssd0323.o
CC hw/display/vga-pci.o
CC hw/display/vga-isa.o
CC hw/display/vmware_vga.o
CC hw/display/blizzard.o
CC hw/display/exynos4210_fimd.o
CC hw/display/framebuffer.o
CC hw/display/tc6393xb.o
CC hw/dma/pl080.o
CC hw/dma/pl330.o
CC hw/dma/i8257.o
CC hw/dma/xlnx-zynq-devcfg.o
CC hw/gpio/max7310.o
CC hw/gpio/pl061.o
CC hw/gpio/zaurus.o
CC hw/gpio/gpio_key.o
CC hw/i2c/core.o
CC hw/i2c/smbus.o
CC hw/i2c/smbus_eeprom.o
CC hw/i2c/i2c-ddc.o
CC hw/i2c/versatile_i2c.o
CC hw/i2c/smbus_ich9.o
CC hw/i2c/pm_smbus.o
CC hw/i2c/bitbang_i2c.o
CC hw/i2c/exynos4210_i2c.o
CC hw/i2c/imx_i2c.o
CC hw/i2c/aspeed_i2c.o
CC hw/ide/core.o
CC hw/ide/atapi.o
CC hw/ide/qdev.o
CC hw/ide/pci.o
CC hw/ide/isa.o
CC hw/ide/piix.o
CC hw/ide/microdrive.o
CC hw/ide/ahci.o
CC hw/ide/ich.o
CC hw/input/hid.o
CC hw/input/lm832x.o
CC hw/input/pckbd.o
CC hw/input/pl050.o
CC hw/input/ps2.o
CC hw/input/stellaris_input.o
CC hw/input/tsc2005.o
CC hw/input/vmmouse.o
CC hw/input/virtio-input.o
CC hw/input/virtio-input-hid.o
CC hw/intc/i8259_common.o
CC hw/intc/i8259.o
CC hw/intc/pl190.o
CC hw/intc/imx_avic.o
CC hw/intc/realview_gic.o
CC hw/intc/ioapic_common.o
CC hw/intc/arm_gic_common.o
CC hw/intc/arm_gic.o
CC hw/intc/arm_gicv2m.o
CC hw/intc/arm_gicv3_common.o
CC hw/intc/arm_gicv3.o
CC hw/intc/arm_gicv3_dist.o
CC hw/intc/arm_gicv3_redist.o
CC hw/intc/arm_gicv3_its_common.o
CC hw/intc/intc.o
CC hw/ipack/ipack.o
CC hw/ipack/tpci200.o
CC hw/ipmi/ipmi.o
CC hw/ipmi/ipmi_bmc_sim.o
CC hw/ipmi/ipmi_bmc_extern.o
CC hw/ipmi/isa_ipmi_kcs.o
CC hw/ipmi/isa_ipmi_bt.o
CC hw/isa/isa-bus.o
CC hw/isa/apm.o
CC hw/mem/pc-dimm.o
CC hw/mem/nvdimm.o
CC hw/misc/applesmc.o
CC hw/misc/max111x.o
CC hw/misc/tmp105.o
CC hw/misc/debugexit.o
CC hw/misc/sga.o
CC hw/misc/pc-testdev.o
CC hw/misc/pci-testdev.o
CC hw/misc/arm_l2x0.o
CC hw/misc/arm_integrator_debug.o
CC hw/misc/a9scu.o
CC hw/misc/arm11scu.o
CC hw/net/ne2000.o
CC hw/net/eepro100.o
CC hw/net/pcnet-pci.o
CC hw/net/pcnet.o
CC hw/net/e1000.o
CC hw/net/e1000x_common.o
CC hw/net/net_tx_pkt.o
CC hw/net/net_rx_pkt.o
CC hw/net/e1000e.o
CC hw/net/e1000e_core.o
CC hw/net/rtl8139.o
CC hw/net/vmxnet3.o
CC hw/net/smc91c111.o
CC hw/net/lan9118.o
CC hw/net/ne2000-isa.o
CC hw/net/xgmac.o
CC hw/net/allwinner_emac.o
CC hw/net/imx_fec.o
CC hw/net/cadence_gem.o
CC hw/net/stellaris_enet.o
CC hw/net/rocker/rocker.o
CC hw/net/rocker/rocker_fp.o
CC hw/net/rocker/rocker_desc.o
CC hw/net/rocker/rocker_world.o
CC hw/net/rocker/rocker_of_dpa.o
CC hw/nvram/eeprom93xx.o
CC hw/nvram/fw_cfg.o
CC hw/nvram/chrp_nvram.o
CC hw/pci-bridge/pci_bridge_dev.o
CC hw/pci-bridge/pci_expander_bridge.o
CC hw/pci-bridge/xio3130_upstream.o
CC hw/pci-bridge/xio3130_downstream.o
CC hw/pci-bridge/ioh3420.o
CC hw/pci-bridge/i82801b11.o
CC hw/pci-host/pam.o
CC hw/pci-host/versatile.o
CC hw/pci-host/piix.o
CC hw/pci-host/q35.o
CC hw/pci-host/gpex.o
CC hw/pci/pci.o
CC hw/pci/pci_bridge.o
CC hw/pci/msix.o
CC hw/pci/msi.o
CC hw/pci/shpc.o
CC hw/pci/slotid_cap.o
CC hw/pci/pci_host.o
CC hw/pci/pcie_host.o
CC hw/pci/pcie.o
CC hw/pci/pcie_aer.o
CC hw/pci/pcie_port.o
CC hw/pci/pci-stub.o
CC hw/pcmcia/pcmcia.o
CC hw/scsi/scsi-disk.o
CC hw/scsi/scsi-generic.o
CC hw/scsi/scsi-bus.o
CC hw/scsi/lsi53c895a.o
CC hw/scsi/mptsas.o
CC hw/scsi/mptconfig.o
CC hw/scsi/mptendian.o
CC hw/scsi/megasas.o
CC hw/scsi/vmw_pvscsi.o
CC hw/scsi/esp.o
CC hw/scsi/esp-pci.o
CC hw/sd/pl181.o
CC hw/sd/ssi-sd.o
CC hw/sd/sd.o
CC hw/sd/core.o
CC hw/sd/sdhci.o
CC hw/smbios/smbios.o
CC hw/smbios/smbios_type_38.o
CC hw/ssi/pl022.o
CC hw/ssi/ssi.o
CC hw/ssi/xilinx_spips.o
CC hw/ssi/aspeed_smc.o
CC hw/ssi/stm32f2xx_spi.o
CC hw/timer/arm_timer.o
CC hw/timer/arm_mptimer.o
CC hw/timer/a9gtimer.o
CC hw/timer/cadence_ttc.o
CC hw/timer/ds1338.o
CC hw/timer/hpet.o
CC hw/timer/i8254_common.o
CC hw/timer/i8254.o
CC hw/timer/pl031.o
CC hw/timer/twl92230.o
CC hw/timer/imx_epit.o
CC hw/timer/imx_gpt.o
CC hw/timer/stm32f2xx_timer.o
CC hw/timer/aspeed_timer.o
CC hw/tpm/tpm_tis.o
CC hw/usb/core.o
CC hw/usb/combined-packet.o
CC hw/usb/bus.o
CC hw/usb/libhw.o
CC hw/usb/desc.o
CC hw/usb/desc-msos.o
CC hw/usb/hcd-uhci.o
CC hw/usb/hcd-ohci.o
CC hw/usb/hcd-ehci.o
CC hw/usb/hcd-ehci-pci.o
CC hw/usb/hcd-ehci-sysbus.o
CC hw/usb/hcd-xhci.o
CC hw/usb/hcd-musb.o
CC hw/usb/dev-hub.o
CC hw/usb/dev-hid.o
CC hw/usb/dev-wacom.o
CC hw/usb/dev-storage.o
CC hw/usb/dev-uas.o
CC hw/usb/dev-audio.o
CC hw/usb/dev-serial.o
CC hw/usb/dev-network.o
CC hw/usb/dev-bluetooth.o
CC hw/usb/dev-smartcard-reader.o
CC hw/usb/host-stub.o
CC hw/virtio/virtio-rng.o
CC hw/virtio/virtio-pci.o
CC hw/virtio/virtio-bus.o
CC hw/virtio/virtio-mmio.o
CC hw/watchdog/watchdog.o
CC hw/watchdog/wdt_i6300esb.o
CC hw/watchdog/wdt_ib700.o
CC migration/migration.o
CC migration/socket.o
CC migration/fd.o
CC migration/exec.o
CC migration/tls.o
CC migration/colo-comm.o
CC migration/colo.o
CC migration/colo-failover.o
CC migration/vmstate.o
CC migration/qemu-file.o
CC migration/qemu-file-channel.o
CC migration/xbzrle.o
CC migration/postcopy-ram.o
CC migration/qjson.o
CC migration/block.o
CC net/net.o
CC net/queue.o
CC net/checksum.o
CC net/util.o
CC net/hub.o
CC net/socket.o
CC net/dump.o
CC net/eth.o
CC net/tap-win32.o
CC net/slirp.o
CC net/filter.o
CC net/filter-buffer.o
CC net/filter-mirror.o
CC net/colo-compare.o
CC net/colo.o
CC net/filter-rewriter.o
CC qom/cpu.o
CC replay/replay.o
CC replay/replay-internal.o
CC replay/replay-events.o
CC replay/replay-time.o
CC replay/replay-input.o
CC replay/replay-char.o
CC replay/replay-snapshot.o
CC slirp/cksum.o
CC slirp/if.o
CC slirp/ip_icmp.o
CC slirp/ip6_icmp.o
CC slirp/ip6_input.o
CC slirp/ip6_output.o
CC slirp/ip_input.o
CC slirp/ip_output.o
CC slirp/dnssearch.o
CC slirp/dhcpv6.o
CC slirp/slirp.o
CC slirp/mbuf.o
CC slirp/misc.o
CC slirp/sbuf.o
CC slirp/socket.o
CC slirp/tcp_input.o
CC slirp/tcp_output.o
CC slirp/tcp_subr.o
CC slirp/tcp_timer.o
CC slirp/udp.o
CC slirp/udp6.o
CC slirp/bootp.o
CC slirp/tftp.o
CC slirp/arp_table.o
CC slirp/ndp_table.o
CC ui/keymaps.o
CC ui/console.o
CC ui/cursor.o
CC ui/qemu-pixman.o
CC ui/input.o
CC ui/input-keymap.o
CC ui/input-legacy.o
CC ui/sdl.o
CC ui/sdl_zoom.o
CC ui/x_keymap.o
CC ui/vnc.o
CC ui/vnc-enc-zlib.o
CC ui/vnc-enc-hextile.o
CC ui/vnc-enc-tight.o
CC ui/vnc-palette.o
CC ui/vnc-enc-zrle.o
CC ui/vnc-auth-vencrypt.o
CC ui/vnc-ws.o
CC ui/vnc-jobs.o
CC ui/gtk.o
CC qga/commands.o
CC qga/guest-agent-command-state.o
CC qga/main.o
CC qga/commands-win32.o
CC qga/channel-win32.o
CC qga/service-win32.o
CC qga/vss-win32.o
CC qga/qapi-generated/qga-qapi-types.o
CC qga/qapi-generated/qga-qapi-visit.o
CC qga/qapi-generated/qga-qmp-marshal.o
AS optionrom/multiboot.o
AS optionrom/linuxboot.o
CC optionrom/linuxboot_dma.o
AS optionrom/kvmvapic.o
BUILD optionrom/multiboot.img
BUILD optionrom/linuxboot.img
CC qmp-introspect.o
BUILD optionrom/linuxboot_dma.img
BUILD optionrom/multiboot.raw
CC qapi-types.o
BUILD optionrom/linuxboot.raw
BUILD optionrom/linuxboot_dma.raw
SIGN optionrom/multiboot.bin
CC qapi-visit.o
SIGN optionrom/linuxboot.bin
SIGN optionrom/linuxboot_dma.bin
BUILD optionrom/kvmvapic.img
CC qapi-event.o
BUILD optionrom/kvmvapic.raw
SIGN optionrom/kvmvapic.bin
AR libqemustub.a
CC qemu-img.o
CC qmp-marshal.o
CC trace/generated-tracers.o
AR libqemuutil.a
LINK qemu-ga.exe
LINK qemu-img.exe
LINK qemu-io.exe
GEN x86_64-softmmu/hmp-commands.h
GEN x86_64-softmmu/hmp-commands-info.h
GEN x86_64-softmmu/config-target.h
GEN aarch64-softmmu/hmp-commands.h
GEN aarch64-softmmu/hmp-commands-info.h
GEN aarch64-softmmu/config-target.h
CC x86_64-softmmu/exec.o
CC x86_64-softmmu/translate-all.o
CC x86_64-softmmu/cpu-exec.o
CC x86_64-softmmu/translate-common.o
CC x86_64-softmmu/cpu-exec-common.o
CC x86_64-softmmu/tcg/tcg.o
CC x86_64-softmmu/tcg/tcg-op.o
CC x86_64-softmmu/tcg/optimize.o
CC x86_64-softmmu/tcg/tcg-common.o
CC x86_64-softmmu/fpu/softfloat.o
CC x86_64-softmmu/disas.o
CC x86_64-softmmu/tcg-runtime.o
CC x86_64-softmmu/kvm-stub.o
CC x86_64-softmmu/arch_init.o
CC x86_64-softmmu/cpus.o
CC x86_64-softmmu/monitor.o
CC aarch64-softmmu/exec.o
CC aarch64-softmmu/translate-all.o
CC aarch64-softmmu/cpu-exec.o
CC aarch64-softmmu/translate-common.o
CC x86_64-softmmu/balloon.o
CC x86_64-softmmu/gdbstub.o
CC aarch64-softmmu/cpu-exec-common.o
CC x86_64-softmmu/ioport.o
CC aarch64-softmmu/tcg/tcg.o
CC aarch64-softmmu/tcg/tcg-op.o
CC x86_64-softmmu/numa.o
CC aarch64-softmmu/tcg/optimize.o
CC x86_64-softmmu/qtest.o
CC x86_64-softmmu/bootdevice.o
CC x86_64-softmmu/memory.o
CC aarch64-softmmu/tcg/tcg-common.o
CC aarch64-softmmu/fpu/softfloat.o
CC aarch64-softmmu/disas.o
CC aarch64-softmmu/tcg-runtime.o
GEN aarch64-softmmu/gdbstub-xml.c
CC x86_64-softmmu/cputlb.o
CC x86_64-softmmu/memory_mapping.o
CC x86_64-softmmu/dump.o
CC x86_64-softmmu/migration/ram.o
CC aarch64-softmmu/kvm-stub.o
CC aarch64-softmmu/arch_init.o
CC x86_64-softmmu/migration/savevm.o
CC x86_64-softmmu/xen-common-stub.o
CC aarch64-softmmu/cpus.o
CC aarch64-softmmu/monitor.o
CC x86_64-softmmu/xen-hvm-stub.o
CC aarch64-softmmu/gdbstub.o
CC aarch64-softmmu/balloon.o
CC x86_64-softmmu/hw/acpi/nvdimm.o
CC aarch64-softmmu/ioport.o
CC x86_64-softmmu/hw/block/virtio-blk.o
CC x86_64-softmmu/hw/block/dataplane/virtio-blk.o
CC aarch64-softmmu/numa.o
CC aarch64-softmmu/qtest.o
CC aarch64-softmmu/bootdevice.o
CC aarch64-softmmu/memory.o
CC x86_64-softmmu/hw/char/virtio-serial-bus.o
CC aarch64-softmmu/cputlb.o
CC aarch64-softmmu/memory_mapping.o
CC x86_64-softmmu/hw/core/nmi.o
CC x86_64-softmmu/hw/core/generic-loader.o
CC x86_64-softmmu/hw/cpu/core.o
CC aarch64-softmmu/dump.o
CC aarch64-softmmu/migration/ram.o
CC x86_64-softmmu/hw/display/vga.o
CC x86_64-softmmu/hw/display/virtio-gpu.o
CC aarch64-softmmu/migration/savevm.o
CC x86_64-softmmu/hw/display/virtio-gpu-3d.o
CC aarch64-softmmu/xen-common-stub.o
CC x86_64-softmmu/hw/display/virtio-gpu-pci.o
CC aarch64-softmmu/xen-hvm-stub.o
CC x86_64-softmmu/hw/display/virtio-vga.o
CC aarch64-softmmu/hw/adc/stm32f2xx_adc.o
CC x86_64-softmmu/hw/intc/apic.o
CC aarch64-softmmu/hw/block/virtio-blk.o
CC aarch64-softmmu/hw/block/dataplane/virtio-blk.o
CC x86_64-softmmu/hw/intc/apic_common.o
CC aarch64-softmmu/hw/char/exynos4210_uart.o
CC aarch64-softmmu/hw/char/omap_uart.o
CC x86_64-softmmu/hw/intc/ioapic.o
CC aarch64-softmmu/hw/char/digic-uart.o
CC x86_64-softmmu/hw/isa/lpc_ich9.o
CC aarch64-softmmu/hw/char/stm32f2xx_usart.o
CC aarch64-softmmu/hw/char/bcm2835_aux.o
CC aarch64-softmmu/hw/char/virtio-serial-bus.o
CC x86_64-softmmu/hw/misc/vmport.o
CC aarch64-softmmu/hw/core/nmi.o
CC aarch64-softmmu/hw/core/generic-loader.o
CC x86_64-softmmu/hw/misc/pvpanic.o
CC x86_64-softmmu/hw/misc/edu.o
CC aarch64-softmmu/hw/cpu/arm11mpcore.o
CC x86_64-softmmu/hw/net/virtio-net.o
CC x86_64-softmmu/hw/net/vhost_net.o
CC x86_64-softmmu/hw/scsi/virtio-scsi.o
CC x86_64-softmmu/hw/scsi/virtio-scsi-dataplane.o
CC aarch64-softmmu/hw/cpu/realview_mpcore.o
CC aarch64-softmmu/hw/cpu/a9mpcore.o
CC x86_64-softmmu/hw/timer/mc146818rtc.o
CC x86_64-softmmu/hw/virtio/virtio.o
CC aarch64-softmmu/hw/cpu/a15mpcore.o
CC x86_64-softmmu/hw/virtio/virtio-balloon.o
CC x86_64-softmmu/hw/i386/multiboot.o
CC x86_64-softmmu/hw/i386/pc.o
CC aarch64-softmmu/hw/cpu/core.o
CC x86_64-softmmu/hw/i386/pc_piix.o
CC aarch64-softmmu/hw/display/omap_dss.o
CC aarch64-softmmu/hw/display/omap_lcdc.o
CC x86_64-softmmu/hw/i386/pc_q35.o
CC x86_64-softmmu/hw/i386/pc_sysfw.o
CC aarch64-softmmu/hw/display/pxa2xx_lcd.o
CC aarch64-softmmu/hw/display/bcm2835_fb.o
CC x86_64-softmmu/hw/i386/x86-iommu.o
CC x86_64-softmmu/hw/i386/intel_iommu.o
CC x86_64-softmmu/hw/i386/amd_iommu.o
CC aarch64-softmmu/hw/display/vga.o
CC x86_64-softmmu/hw/i386/kvmvapic.o
CC x86_64-softmmu/hw/i386/acpi-build.o
CC aarch64-softmmu/hw/display/virtio-gpu.o
CC aarch64-softmmu/hw/display/virtio-gpu-3d.o
CC x86_64-softmmu/hw/i386/pci-assign-load-rom.o
CC aarch64-softmmu/hw/display/virtio-gpu-pci.o
CC x86_64-softmmu/target-i386/translate.o
CC aarch64-softmmu/hw/display/dpcd.o
CC aarch64-softmmu/hw/display/xlnx_dp.o
CC x86_64-softmmu/target-i386/helper.o
CC x86_64-softmmu/target-i386/cpu.o
CC aarch64-softmmu/hw/dma/xlnx_dpdma.o
CC aarch64-softmmu/hw/dma/omap_dma.o
CC aarch64-softmmu/hw/dma/soc_dma.o
CC x86_64-softmmu/target-i386/bpt_helper.o
CC aarch64-softmmu/hw/dma/pxa2xx_dma.o
CC aarch64-softmmu/hw/dma/bcm2835_dma.o
CC x86_64-softmmu/target-i386/excp_helper.o
CC x86_64-softmmu/target-i386/fpu_helper.o
CC aarch64-softmmu/hw/gpio/omap_gpio.o
CC aarch64-softmmu/hw/gpio/imx_gpio.o
CC aarch64-softmmu/hw/i2c/omap_i2c.o
CC x86_64-softmmu/target-i386/cc_helper.o
CC x86_64-softmmu/target-i386/int_helper.o
CC x86_64-softmmu/target-i386/svm_helper.o
CC x86_64-softmmu/target-i386/smm_helper.o
CC x86_64-softmmu/target-i386/misc_helper.o
CC x86_64-softmmu/target-i386/mem_helper.o
CC aarch64-softmmu/hw/input/pxa2xx_keypad.o
CC aarch64-softmmu/hw/input/tsc210x.o
CC x86_64-softmmu/target-i386/seg_helper.o
CC x86_64-softmmu/target-i386/mpx_helper.o
CC aarch64-softmmu/hw/intc/armv7m_nvic.o
CC aarch64-softmmu/hw/intc/exynos4210_gic.o
CC aarch64-softmmu/hw/intc/exynos4210_combiner.o
CC x86_64-softmmu/target-i386/gdbstub.o
CC x86_64-softmmu/target-i386/machine.o
CC aarch64-softmmu/hw/intc/omap_intc.o
CC x86_64-softmmu/target-i386/arch_memory_mapping.o
CC x86_64-softmmu/target-i386/arch_dump.o
CC x86_64-softmmu/target-i386/monitor.o
CC aarch64-softmmu/hw/intc/bcm2835_ic.o
CC x86_64-softmmu/target-i386/kvm-stub.o
CC aarch64-softmmu/hw/intc/bcm2836_control.o
GEN trace/generated-helpers.c
CC aarch64-softmmu/hw/intc/allwinner-a10-pic.o
CC x86_64-softmmu/trace/control-target.o
CC aarch64-softmmu/hw/intc/aspeed_vic.o
CC aarch64-softmmu/hw/intc/arm_gicv3_cpuif.o
CC aarch64-softmmu/hw/misc/arm_sysctl.o
CC aarch64-softmmu/hw/misc/cbus.o
CC aarch64-softmmu/hw/misc/exynos4210_pmu.o
CC aarch64-softmmu/hw/misc/imx_ccm.o
CC aarch64-softmmu/hw/misc/imx31_ccm.o
CC aarch64-softmmu/hw/misc/imx25_ccm.o
CC x86_64-softmmu/trace/generated-helpers.o
CC aarch64-softmmu/hw/misc/imx6_ccm.o
CC aarch64-softmmu/hw/misc/imx6_src.o
CC aarch64-softmmu/hw/misc/mst_fpga.o
CC aarch64-softmmu/hw/misc/omap_clk.o
CC aarch64-softmmu/hw/misc/omap_gpmc.o
CC aarch64-softmmu/hw/misc/omap_l4.o
CC aarch64-softmmu/hw/misc/omap_sdrc.o
CC aarch64-softmmu/hw/misc/omap_tap.o
CC aarch64-softmmu/hw/misc/bcm2835_mbox.o
CC aarch64-softmmu/hw/misc/bcm2835_property.o
CC aarch64-softmmu/hw/misc/zynq_slcr.o
CC aarch64-softmmu/hw/misc/zynq-xadc.o
CC aarch64-softmmu/hw/misc/stm32f2xx_syscfg.o
CC aarch64-softmmu/hw/misc/edu.o
CC aarch64-softmmu/hw/misc/auxbus.o
CC aarch64-softmmu/hw/misc/aspeed_scu.o
CC aarch64-softmmu/hw/misc/aspeed_sdmc.o
CC aarch64-softmmu/hw/net/virtio-net.o
CC aarch64-softmmu/hw/net/vhost_net.o
CC aarch64-softmmu/hw/pcmcia/pxa2xx.o
CC aarch64-softmmu/hw/scsi/virtio-scsi.o
CC aarch64-softmmu/hw/scsi/virtio-scsi-dataplane.o
CC aarch64-softmmu/hw/sd/omap_mmc.o
CC aarch64-softmmu/hw/sd/pxa2xx_mmci.o
CC aarch64-softmmu/hw/ssi/omap_spi.o
CC aarch64-softmmu/hw/ssi/imx_spi.o
CC aarch64-softmmu/hw/timer/exynos4210_mct.o
CC aarch64-softmmu/hw/timer/exynos4210_pwm.o
CC aarch64-softmmu/hw/timer/exynos4210_rtc.o
CC aarch64-softmmu/hw/timer/omap_gptimer.o
CC aarch64-softmmu/hw/timer/omap_synctimer.o
CC aarch64-softmmu/hw/timer/pxa2xx_timer.o
CC aarch64-softmmu/hw/timer/digic-timer.o
CC aarch64-softmmu/hw/timer/allwinner-a10-pit.o
CC aarch64-softmmu/hw/usb/tusb6010.o
CC aarch64-softmmu/hw/virtio/virtio.o
CC aarch64-softmmu/hw/virtio/virtio-balloon.o
LINK x86_64-softmmu/qemu-system-x86_64w.exe
CC aarch64-softmmu/hw/arm/boot.o
CC aarch64-softmmu/hw/arm/collie.o
CC aarch64-softmmu/hw/arm/exynos4_boards.o
CC aarch64-softmmu/hw/arm/gumstix.o
CC aarch64-softmmu/hw/arm/highbank.o
CC aarch64-softmmu/hw/arm/digic_boards.o
CC aarch64-softmmu/hw/arm/integratorcp.o
CC aarch64-softmmu/hw/arm/mainstone.o
CC aarch64-softmmu/hw/arm/musicpal.o
CC aarch64-softmmu/hw/arm/nseries.o
CC aarch64-softmmu/hw/arm/omap_sx1.o
CC aarch64-softmmu/hw/arm/palm.o
CC aarch64-softmmu/hw/arm/realview.o
CC aarch64-softmmu/hw/arm/spitz.o
CC aarch64-softmmu/hw/arm/stellaris.o
CC aarch64-softmmu/hw/arm/tosa.o
CC aarch64-softmmu/hw/arm/versatilepb.o
CC aarch64-softmmu/hw/arm/vexpress.o
CC aarch64-softmmu/hw/arm/virt.o
CC aarch64-softmmu/hw/arm/xilinx_zynq.o
CC aarch64-softmmu/hw/arm/z2.o
GEN x86_64-softmmu/qemu-system-x86_64.exe
CC aarch64-softmmu/hw/arm/virt-acpi-build.o
CC aarch64-softmmu/hw/arm/netduino2.o
CC aarch64-softmmu/hw/arm/sysbus-fdt.o
CC aarch64-softmmu/hw/arm/exynos4210.o
CC aarch64-softmmu/hw/arm/armv7m.o
CC aarch64-softmmu/hw/arm/pxa2xx.o
CC aarch64-softmmu/hw/arm/pxa2xx_gpio.o
CC aarch64-softmmu/hw/arm/pxa2xx_pic.o
CC aarch64-softmmu/hw/arm/digic.o
CC aarch64-softmmu/hw/arm/omap1.o
CC aarch64-softmmu/hw/arm/omap2.o
CC aarch64-softmmu/hw/arm/strongarm.o
CC aarch64-softmmu/hw/arm/allwinner-a10.o
CC aarch64-softmmu/hw/arm/cubieboard.o
CC aarch64-softmmu/hw/arm/bcm2835_peripherals.o
CC aarch64-softmmu/hw/arm/bcm2836.o
CC aarch64-softmmu/hw/arm/raspi.o
CC aarch64-softmmu/hw/arm/stm32f205_soc.o
CC aarch64-softmmu/hw/arm/xlnx-zynqmp.o
CC aarch64-softmmu/hw/arm/xlnx-ep108.o
CC aarch64-softmmu/hw/arm/fsl-imx25.o
CC aarch64-softmmu/hw/arm/imx25_pdk.o
CC aarch64-softmmu/hw/arm/fsl-imx31.o
CC aarch64-softmmu/hw/arm/kzm.o
CC aarch64-softmmu/hw/arm/fsl-imx6.o
CC aarch64-softmmu/hw/arm/sabrelite.o
CC aarch64-softmmu/hw/arm/aspeed_soc.o
CC aarch64-softmmu/hw/arm/aspeed.o
CC aarch64-softmmu/target-arm/arm-semi.o
CC aarch64-softmmu/target-arm/machine.o
CC aarch64-softmmu/target-arm/psci.o
CC aarch64-softmmu/target-arm/arch_dump.o
CC aarch64-softmmu/target-arm/monitor.o
CC aarch64-softmmu/target-arm/kvm-stub.o
CC aarch64-softmmu/target-arm/translate.o
CC aarch64-softmmu/target-arm/op_helper.o
CC aarch64-softmmu/target-arm/helper.o
CC aarch64-softmmu/target-arm/cpu.o
CC aarch64-softmmu/target-arm/neon_helper.o
CC aarch64-softmmu/target-arm/iwmmxt_helper.o
CC aarch64-softmmu/target-arm/gdbstub.o
CC aarch64-softmmu/target-arm/cpu64.o
CC aarch64-softmmu/target-arm/translate-a64.o
CC aarch64-softmmu/target-arm/helper-a64.o
CC aarch64-softmmu/target-arm/gdbstub64.o
In file included from /tmp/qemu-test/src/target-arm/arm-semi.c:117:0:
/tmp/qemu-test/src/include/exec/softmmu-arm-semi.h: In function 'softmmu_unlock_user':
/tmp/qemu-test/src/include/exec/softmmu-arm-semi.h:139:14: error: unused variable 'pc' [-Werror=unused-variable]
uint8_t *pc = p;
^~
cc1: all warnings being treated as errors
/tmp/qemu-test/src/rules.mak:60: recipe for target 'target-arm/arm-semi.o' failed
make[1]: *** [target-arm/arm-semi.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC aarch64-softmmu/target-arm/crypto_helper.o
In file included from /tmp/qemu-test/src/target-arm/gdbstub.c:24:0:
/tmp/qemu-test/src/include/exec/softmmu-arm-semi.h: In function 'softmmu_unlock_user':
/tmp/qemu-test/src/include/exec/softmmu-arm-semi.h:139:14: error: unused variable 'pc' [-Werror=unused-variable]
uint8_t *pc = p;
^~
At top level:
/tmp/qemu-test/src/include/exec/softmmu-arm-semi.h:136:13: error: 'softmmu_unlock_user' defined but not used [-Werror=unused-function]
static void softmmu_unlock_user(CPUArchState *env, void *p, target_ulong addr,
^~~~~~~~~~~~~~~~~~~
/tmp/qemu-test/src/include/exec/softmmu-arm-semi.h:118:14: error: 'softmmu_lock_user_string' defined but not used [-Werror=unused-function]
static char *softmmu_lock_user_string(CPUArchState *env, target_ulong addr)
^~~~~~~~~~~~~~~~~~~~~~~~
/tmp/qemu-test/src/include/exec/softmmu-arm-semi.h:106:14: error: 'softmmu_lock_user' defined but not used [-Werror=unused-function]
static void *softmmu_lock_user(CPUArchState *env,
^~~~~~~~~~~~~~~~~
cc1: all warnings being treated as errors
/tmp/qemu-test/src/rules.mak:60: recipe for target 'target-arm/gdbstub.o' failed
make[1]: *** [target-arm/gdbstub.o] Error 1
Makefile:202: recipe for target 'subdir-aarch64-softmmu' failed
make: *** [subdir-aarch64-softmmu] Error 2
make[1]: *** [docker-run] Error 2
make[1]: Leaving directory `/var/tmp/patchew-tester-tmp-pb3qxzah/src'
make: *** [docker-run-test-mingw@fedora] Error 2
=== OUTPUT END ===
Test command exited with code: 2
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@freelists.org
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [Qemu-devel] [PATCH 1/5] ARM BE8/BE32 semihosting and gdbstub support.
2016-11-03 17:30 ` [Qemu-devel] [PATCH 1/5] ARM BE8/BE32 semihosting and gdbstub support Julian Brown
@ 2016-11-03 22:23 ` Peter Maydell
2016-11-03 23:34 ` Julian Brown
` (2 more replies)
0 siblings, 3 replies; 28+ messages in thread
From: Peter Maydell @ 2016-11-03 22:23 UTC (permalink / raw)
To: Julian Brown; +Cc: QEMU Developers
On 3 November 2016 at 17:30, Julian Brown <julian@codesourcery.com> wrote:
> This patch improves support for semihosting and debugging with the
> in-built gdbstub for ARM system-mode emulation in big-endian mode (either
> BE8 or BE32), after the fairly recent changes to allow a single QEMU
> binary to deal with each of LE, BE8 and BE32 modes in one. It's only
> currently good for little-endian host systems. The relevant use case
> is using QEMU as a "bare metal" instruction-set simulator, e.g. for
> toolchain testing.
>
> For semihosting, the softmmu-semi.h file is overridden with an
> ARM-specific version that knows about byte-swapping target memory into
> host order -- including that which has been byte-swapped at load time
> for BE32 mode.
Something here seems really weird. I would expect gdb
to be able to cope with the target CPU's endianness
settings. After all there is real world code which
starts off in one endianness, temporarily swaps to
the other and then switches back again, and gdb needs
to be able to step through it without issues. So having
code in the gdbstub interface that looks at arm_bswap_needed()
seems rather odd and in the wrong place. What the guest
CPU happens to be doing at any particular point shouldn't
affect the way we talk to gdb.
> For the gdbstub, we'd like to be able to invoke QEMU from GDB like:
>
> (gdb) target remote | arm-qemu-system -cpu=foo [options] /dev/null
> (gdb) load
> (gdb) ...
>
> which unfortunately bypasses the probing of the loaded ELF file (since
> it's just /dev/null) to determine whether to use BE8/BE32 mode. So,
> I added some "virtual" CPUs to set the endian type instead (arm926-be,
> cortex-a15-be for BE32/BE8 mode respectively), from the reset value
> of the SCTLR. This is kind of like having a configuration input to the
> CPU on some hardware board to select endianness, which is a completely
> legitimate thing to have, even if the implementation as-is is not really
> ideal from a software-engineering standpoint. It suffices for our current
> use-case though.
Strong 'no' for the approach of having different CPU
names, I'm afraid. What you want is to have a CPU
property which works like the hardware CPU's CFGEND
signal to set the reset value of the SCTLR.EE bit. Then
a board can use that where it would wire up CFGEND
in real hardware, and on the command line you can
have -cpu whatever,cfgend=yes (which is a bit ugly
but then it's borderline whether it makes any sense at
all for the user to be able to set the endianness on
the commandline).
(For the rest of the series: you've missed the 2.8
freeze, and I'm on holiday for most of November, so
it may be a while before I can get to it; hopefully
somebody else will step up and have a look at it.)
thanks
-- PMM
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [Qemu-devel] [PATCH 4/5] ARM BE32 watchpoint fix.
2016-11-03 17:30 ` [Qemu-devel] [PATCH 4/5] ARM BE32 watchpoint fix Julian Brown
@ 2016-11-03 23:14 ` Peter Maydell
2016-11-03 23:20 ` Julian Brown
0 siblings, 1 reply; 28+ messages in thread
From: Peter Maydell @ 2016-11-03 23:14 UTC (permalink / raw)
To: Julian Brown; +Cc: QEMU Developers
On 3 November 2016 at 17:30, Julian Brown <julian@codesourcery.com> wrote:
> In BE32 mode, sub-word size watchpoints can fail to trigger because the
> address of the access is adjusted in the opcode helpers before being
> compared with the watchpoint registers. This patch reversed the address
> adjustment before performing the comparison.
>
> Signed-off-by: Julian Brown <julian@codesourcery.com>
> ---
> exec.c | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/exec.c b/exec.c
> index 4c84389..eadab54 100644
> --- a/exec.c
> +++ b/exec.c
> @@ -2047,6 +2047,19 @@ static void check_watchpoint(int offset, int len, MemTxAttrs attrs, int flags)
> return;
> }
> vaddr = (cpu->mem_io_vaddr & TARGET_PAGE_MASK) + offset;
> +#if defined(TARGET_ARM) && !defined(CONFIG_USER_ONLY)
> + /* In BE32 system mode, target memory is stored byteswapped (FIXME:
> + relative to a little-endian host system), and by the time we reach here
> + (via an opcode helper) the addresses of subword accesses have been
> + adjusted to account for that, which means that watchpoints will not
> + match. Undo the adjustment here. */
> + if (arm_sctlr_b(env)) {
> + if (len == 1)
> + vaddr ^= 3;
> + else if (len == 2)
> + vaddr ^= 2;
> + }
> +#endif
No target-CPU specific code in exec.c, please...
thanks
-- PMM
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [Qemu-devel] [PATCH 4/5] ARM BE32 watchpoint fix.
2016-11-03 23:14 ` Peter Maydell
@ 2016-11-03 23:20 ` Julian Brown
2016-11-04 8:55 ` Paolo Bonzini
0 siblings, 1 reply; 28+ messages in thread
From: Julian Brown @ 2016-11-03 23:20 UTC (permalink / raw)
To: Peter Maydell; +Cc: QEMU Developers
On Thu, 3 Nov 2016 23:14:05 +0000
Peter Maydell <peter.maydell@linaro.org> wrote:
> On 3 November 2016 at 17:30, Julian Brown <julian@codesourcery.com>
> wrote:
> > In BE32 mode, sub-word size watchpoints can fail to trigger because
> > the address of the access is adjusted in the opcode helpers before
> > being compared with the watchpoint registers. This patch reversed
> > the address adjustment before performing the comparison.
> >
> > Signed-off-by: Julian Brown <julian@codesourcery.com>
> > ---
> > exec.c | 13 +++++++++++++
> > 1 file changed, 13 insertions(+)
> >
> > diff --git a/exec.c b/exec.c
> > index 4c84389..eadab54 100644
> > --- a/exec.c
> > +++ b/exec.c
> > @@ -2047,6 +2047,19 @@ static void check_watchpoint(int offset, int
> > len, MemTxAttrs attrs, int flags) return;
> > }
> > vaddr = (cpu->mem_io_vaddr & TARGET_PAGE_MASK) + offset;
> > +#if defined(TARGET_ARM) && !defined(CONFIG_USER_ONLY)
> > + /* In BE32 system mode, target memory is stored byteswapped
> > (FIXME:
> > + relative to a little-endian host system), and by the time
> > we reach here
> > + (via an opcode helper) the addresses of subword accesses
> > have been
> > + adjusted to account for that, which means that watchpoints
> > will not
> > + match. Undo the adjustment here. */
> > + if (arm_sctlr_b(env)) {
> > + if (len == 1)
> > + vaddr ^= 3;
> > + else if (len == 2)
> > + vaddr ^= 2;
> > + }
> > +#endif
>
> No target-CPU specific code in exec.c, please...
Yeah, I'd imagine not. I struggled with this one. Any suggestions for a
better way to do this?
Thanks,
Julian
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [Qemu-devel] [PATCH 1/5] ARM BE8/BE32 semihosting and gdbstub support.
2016-11-03 22:23 ` Peter Maydell
@ 2016-11-03 23:34 ` Julian Brown
2016-11-04 8:48 ` Paolo Bonzini
2016-11-04 9:03 ` Paolo Bonzini
2016-12-06 15:11 ` Julian Brown
2 siblings, 1 reply; 28+ messages in thread
From: Julian Brown @ 2016-11-03 23:34 UTC (permalink / raw)
To: Peter Maydell; +Cc: QEMU Developers
On Thu, 3 Nov 2016 22:23:09 +0000
Peter Maydell <peter.maydell@linaro.org> wrote:
> On 3 November 2016 at 17:30, Julian Brown <julian@codesourcery.com>
> wrote:
> > This patch improves support for semihosting and debugging with the
> > in-built gdbstub for ARM system-mode emulation in big-endian mode
> > (either BE8 or BE32), after the fairly recent changes to allow a
> > single QEMU binary to deal with each of LE, BE8 and BE32 modes in
> > one. It's only currently good for little-endian host systems. The
> > relevant use case is using QEMU as a "bare metal" instruction-set
> > simulator, e.g. for toolchain testing.
> >
> > For semihosting, the softmmu-semi.h file is overridden with an
> > ARM-specific version that knows about byte-swapping target memory
> > into host order -- including that which has been byte-swapped at
> > load time for BE32 mode.
>
> Something here seems really weird. I would expect gdb
> to be able to cope with the target CPU's endianness
> settings. After all there is real world code which
> starts off in one endianness, temporarily swaps to
> the other and then switches back again, and gdb needs
> to be able to step through it without issues. So having
> code in the gdbstub interface that looks at arm_bswap_needed()
> seems rather odd and in the wrong place. What the guest
> CPU happens to be doing at any particular point shouldn't
> affect the way we talk to gdb.
I think the way it works is, if you invoke GDB with something like,
$ arm-eabi-gdb big-endian-binary.elf
then the remote protocol will talk in big-endian format (memory
read/write packets, register read/write packets, etc.) for that session.
I'm not sure if it'll transparently switch to little-endian remote
protocol format if the target does a SETEND instruction, or whatever.
I'd guess not.
So (IIRC!) the gdbstub needs to interpret some of these read/write
values on the host, i.e. in host byte ordering. "Traditionally", the
ldl_p and stl_p (etc.) macros would byteswap depending on the
TARGET_WORDS_BIGENDIAN setting -- that's how come our internal testing
using QEMU worked at all in the past. But that's changed with the
single-binary-for-all-endiannesses patches.
So -- all uses of ld*_p and st*_p, and the TARGET_WORDS_BIGENDIAN
macro, are now suspect in ARM system-emulation mode. The gdbstub.c
changes appear to fix some of those, but... yeah, there may be
subtleties remaining, like run-time endian switching by the target.
Generally it's not ideal, but I'm not sure how to do better.
Thanks,
Julian
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [Qemu-devel] [PATCH 1/5] ARM BE8/BE32 semihosting and gdbstub support.
2016-11-03 23:34 ` Julian Brown
@ 2016-11-04 8:48 ` Paolo Bonzini
2016-11-04 10:25 ` Julian Brown
0 siblings, 1 reply; 28+ messages in thread
From: Paolo Bonzini @ 2016-11-04 8:48 UTC (permalink / raw)
To: Julian Brown, Peter Maydell; +Cc: QEMU Developers
On 04/11/2016 00:34, Julian Brown wrote:
>
> So (IIRC!) the gdbstub needs to interpret some of these read/write
> values on the host, i.e. in host byte ordering. "Traditionally", the
> ldl_p and stl_p (etc.) macros would byteswap depending on the
> TARGET_WORDS_BIGENDIAN setting -- that's how come our internal testing
> using QEMU worked at all in the past. But that's changed with the
> single-binary-for-all-endiannesses patches.
I'm not sure what you mean here... BE8 wasn't supported at all in
system emulation mode before those patches, and there are still two
binaries for user-mode little-endian on one side and BE8/BE32 on the
other. The details of how QEMU distinguished BE8 from BE32 changed
(from bswap_code to SCTLR.B and CPSR.E) but TARGET_WORDS_BIGENDIAN
remained set for qemu-armeb.
The difference for user-mode in fact was very small; for system mode
emulation it was larger because QEMU grew support for all three of
CPSR.E, SCTLR.B and SCTLR.EE. But then again there was no
qemu-system-armeb before, maybe it was something you had in your
internal QEMU?
That said, if indeed gdb expects wire endianness to match ELF
endianness, you have to do something about it indeed in the gdbstub.
But it seems weird to look at CPSR.E, as that would flip values across
SETEND. SCTLR.B|SCTLR.EE seems more plausible. The addition of a CPU
property for reset, as suggested by Peter, would then make a lot of
sense. Each CPU initfn would then look at that property and use it to
initialize (depending on the model) either SCTLR.B or SCTLR.EE.
The change to arm_cpu_memory_rw_debug for BE32 is also interesting. gdb
documentation says
The stub need not use any particular size or alignment when
gathering data from memory for the response; even if ADDR is
word-aligned and LENGTH is a multiple of the word size, the stub is
free to use byte accesses, or not.
while your change means that gdb actually wants you to do byte accesses.
Paolo
> So -- all uses of ld*_p and st*_p, and the TARGET_WORDS_BIGENDIAN
> macro, are now suspect in ARM system-emulation mode. The gdbstub.c
> changes appear to fix some of those, but... yeah, there may be
> subtleties remaining, like run-time endian switching by the target.
> Generally it's not ideal, but I'm not sure how to do better.
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [Qemu-devel] [PATCH 4/5] ARM BE32 watchpoint fix.
2016-11-03 23:20 ` Julian Brown
@ 2016-11-04 8:55 ` Paolo Bonzini
2016-12-06 15:12 ` Julian Brown
0 siblings, 1 reply; 28+ messages in thread
From: Paolo Bonzini @ 2016-11-04 8:55 UTC (permalink / raw)
To: Julian Brown, Peter Maydell; +Cc: QEMU Developers
On 04/11/2016 00:20, Julian Brown wrote:
> On Thu, 3 Nov 2016 23:14:05 +0000
> Peter Maydell <peter.maydell@linaro.org> wrote:
>
>> On 3 November 2016 at 17:30, Julian Brown <julian@codesourcery.com>
>> wrote:
>>> In BE32 mode, sub-word size watchpoints can fail to trigger because
>>> the address of the access is adjusted in the opcode helpers before
>>> being compared with the watchpoint registers. This patch reversed
>>> the address adjustment before performing the comparison.
>>>
>>> Signed-off-by: Julian Brown <julian@codesourcery.com>
>>> ---
>>> exec.c | 13 +++++++++++++
>>> 1 file changed, 13 insertions(+)
>>>
>>> diff --git a/exec.c b/exec.c
>>> index 4c84389..eadab54 100644
>>> --- a/exec.c
>>> +++ b/exec.c
>>> @@ -2047,6 +2047,19 @@ static void check_watchpoint(int offset, int
>>> len, MemTxAttrs attrs, int flags) return;
>>> }
>>> vaddr = (cpu->mem_io_vaddr & TARGET_PAGE_MASK) + offset;
>>> +#if defined(TARGET_ARM) && !defined(CONFIG_USER_ONLY)
>>> + /* In BE32 system mode, target memory is stored byteswapped
>>> (FIXME:
>>> + relative to a little-endian host system), and by the time
>>> we reach here
>>> + (via an opcode helper) the addresses of subword accesses
>>> have been
>>> + adjusted to account for that, which means that watchpoints
>>> will not
>>> + match. Undo the adjustment here. */
>>> + if (arm_sctlr_b(env)) {
>>> + if (len == 1)
>>> + vaddr ^= 3;
>>> + else if (len == 2)
>>> + vaddr ^= 2;
>>> + }
>>> +#endif
>>
>> No target-CPU specific code in exec.c, please...
>
> Yeah, I'd imagine not. I struggled with this one. Any suggestions for a
> better way to do this?
You can add a function pointer to CPUClass and call it from here. It's
how cc->debug_check_watchpoint is being called already.
Paolo
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [Qemu-devel] [PATCH 3/5] Fix arm_semi_flen_cb for BE32 system mode.
2016-11-03 17:30 ` [Qemu-devel] [PATCH 3/5] Fix arm_semi_flen_cb for BE32 system mode Julian Brown
@ 2016-11-04 9:00 ` Paolo Bonzini
2016-12-06 15:11 ` Julian Brown
0 siblings, 1 reply; 28+ messages in thread
From: Paolo Bonzini @ 2016-11-04 9:00 UTC (permalink / raw)
To: Julian Brown, qemu-devel
On 03/11/2016 18:30, Julian Brown wrote:
> +#ifdef CONFIG_USER_ONLY
> size = be32_to_cpu(size);
> +#else
> + /* If we're running in BE32 system mode, we don't need to do an explicit
> + * byte swap, because (I think) target memory is already stored in
> + * byte-swapped format.
Isn't this true also of user-mode (both BE8 and BE32)?
Paolo
> + */
> + if (!arm_sctlr_b(env)) {
> + size = be32_to_cpu(size);
> + }
> +#endif
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [Qemu-devel] [PATCH 1/5] ARM BE8/BE32 semihosting and gdbstub support.
2016-11-03 22:23 ` Peter Maydell
2016-11-03 23:34 ` Julian Brown
@ 2016-11-04 9:03 ` Paolo Bonzini
2016-12-06 15:11 ` Julian Brown
2 siblings, 0 replies; 28+ messages in thread
From: Paolo Bonzini @ 2016-11-04 9:03 UTC (permalink / raw)
To: Peter Maydell, Julian Brown; +Cc: QEMU Developers
On 03/11/2016 23:23, Peter Maydell wrote:
> (For the rest of the series: you've missed the 2.8
> freeze, and I'm on holiday for most of November, so
> it may be a while before I can get to it; hopefully
> somebody else will step up and have a look at it.)
2/4/5 are relatively obvious bugfixes (in particular patch 5 is
completely trivial). I commented separately on patch 3.
Paolo
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [Qemu-devel] [PATCH 1/5] ARM BE8/BE32 semihosting and gdbstub support.
2016-11-04 8:48 ` Paolo Bonzini
@ 2016-11-04 10:25 ` Julian Brown
2016-11-04 11:01 ` Paolo Bonzini
0 siblings, 1 reply; 28+ messages in thread
From: Julian Brown @ 2016-11-04 10:25 UTC (permalink / raw)
To: Paolo Bonzini; +Cc: Peter Maydell, QEMU Developers
On Fri, 4 Nov 2016 09:48:06 +0100
Paolo Bonzini <pbonzini@redhat.com> wrote:
> On 04/11/2016 00:34, Julian Brown wrote:
> >
> > So (IIRC!) the gdbstub needs to interpret some of these read/write
> > values on the host, i.e. in host byte ordering. "Traditionally", the
> > ldl_p and stl_p (etc.) macros would byteswap depending on the
> > TARGET_WORDS_BIGENDIAN setting -- that's how come our internal
> > testing using QEMU worked at all in the past. But that's changed
> > with the single-binary-for-all-endiannesses patches.
>
> I'm not sure what you mean here... BE8 wasn't supported at all in
> system emulation mode before those patches, and there are still two
> binaries for user-mode little-endian on one side and BE8/BE32 on the
> other. The details of how QEMU distinguished BE8 from BE32 changed
> (from bswap_code to SCTLR.B and CPSR.E) but TARGET_WORDS_BIGENDIAN
> remained set for qemu-armeb.
>
> The difference for user-mode in fact was very small; for system mode
> emulation it was larger because QEMU grew support for all three of
> CPSR.E, SCTLR.B and SCTLR.EE. But then again there was no
> qemu-system-armeb before, maybe it was something you had in your
> internal QEMU?
Yes, exactly. I think we more-or-less just added a armeb-softmmu.mak
and things worked -- at least as far as BE32 mode, and bearing in mind
that we were only interested in instruction-set simulation. BE8 mode is
(ahem) a different matter, i.e. we (as in Mentor) might just have been
getting that wrong. Oops!
> That said, if indeed gdb expects wire endianness to match ELF
> endianness, you have to do something about it indeed in the gdbstub.
> But it seems weird to look at CPSR.E, as that would flip values across
> SETEND. SCTLR.B|SCTLR.EE seems more plausible. The addition of a CPU
> property for reset, as suggested by Peter, would then make a lot of
> sense. Each CPU initfn would then look at that property and use it to
> initialize (depending on the model) either SCTLR.B or SCTLR.EE.
OK, that makes sense, thanks.
> The change to arm_cpu_memory_rw_debug for BE32 is also interesting.
> gdb documentation says
>
> The stub need not use any particular size or alignment when
> gathering data from memory for the response; even if ADDR is
> word-aligned and LENGTH is a multiple of the word size, the stub
> is free to use byte accesses, or not.
>
> while your change means that gdb actually wants you to do byte
> accesses.
The splitting-into-bytes is just an implementation convenience -- the
simplest way I could see of handling the low-order address bit reversal
without breaking abstractions more or shuffling lots of code around.
I'm not sure if GDB was actually requesting sub-word access sizes.
Thanks,
Julian
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [Qemu-devel] [PATCH 1/5] ARM BE8/BE32 semihosting and gdbstub support.
2016-11-04 10:25 ` Julian Brown
@ 2016-11-04 11:01 ` Paolo Bonzini
0 siblings, 0 replies; 28+ messages in thread
From: Paolo Bonzini @ 2016-11-04 11:01 UTC (permalink / raw)
To: Julian Brown; +Cc: Peter Maydell, QEMU Developers
On 04/11/2016 11:25, Julian Brown wrote:
> > The change to arm_cpu_memory_rw_debug for BE32 is also interesting.
> > gdb documentation says
> >
> > The stub need not use any particular size or alignment when
> > gathering data from memory for the response; even if ADDR is
> > word-aligned and LENGTH is a multiple of the word size, the stub
> > is free to use byte accesses, or not.
> >
> > while your change means that gdb actually wants you to do byte
> > accesses.
>
> The splitting-into-bytes is just an implementation convenience -- the
> simplest way I could see of handling the low-order address bit reversal
> without breaking abstractions more or shuffling lots of code around.
> I'm not sure if GDB was actually requesting sub-word access sizes.
Right, the question is what GDB actually wants. I don't really
understand how BE32 is compatible with "the stub need not use any
particular size or alignment", unless GDB takes care of tweaking the
address on its end (and possibly taking care of always reading full
words when len>4?!?).
Also, it would not depend on SCTLR.B, but rather on the CFGEND property
and on CFGEND being tied to SCTLR.B.
Thanks,
Paolo
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [Qemu-devel] [PATCH 5/5] Fix typo in arm_cpu_do_interrupt_aarch32.
2016-11-03 21:26 ` [Qemu-devel] [PATCH 5/5] Fix typo in arm_cpu_do_interrupt_aarch32 Julian Brown
@ 2016-11-04 13:02 ` Peter Maydell
0 siblings, 0 replies; 28+ messages in thread
From: Peter Maydell @ 2016-11-04 13:02 UTC (permalink / raw)
To: Julian Brown; +Cc: QEMU Developers
On 3 November 2016 at 21:26, Julian Brown <julian@codesourcery.com> wrote:
> This appears to be a typo in arm_cpu_do_interrupt_aarch32 (OR'ing with ~CPSR_E
> instead of CPSR_E).
>
> Signed-off-by: Julian Brown <julian@codesourcery.com>
> ---
> target-arm/helper.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index 25b15dc..b5b65ca 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -6438,7 +6438,7 @@ static void arm_cpu_do_interrupt_aarch32(CPUState *cs)
> /* Set new mode endianness */
> env->uncached_cpsr &= ~CPSR_E;
> if (env->cp15.sctlr_el[arm_current_el(env)] & SCTLR_EE) {
> - env->uncached_cpsr |= ~CPSR_E;
> + env->uncached_cpsr |= CPSR_E;
> }
> env->daif |= mask;
> /* this is a lie, as the was no c1_sys on V4T/V5, but who cares
> --
> 1.9.1
This is an obvious bugfix so I've applied it to target-arm.next
for 2.8. I tweaked the commit message a bit to say what the
effects of the bug were.
thanks
-- PMM
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [Qemu-devel] [PATCH 2/5] Fix Thumb-1 BE32 execution and disassembly.
2016-11-03 17:30 ` [Qemu-devel] [PATCH 2/5] Fix Thumb-1 BE32 execution and disassembly Julian Brown
@ 2016-11-04 13:30 ` Peter Maydell
2016-11-04 14:04 ` Julian Brown
0 siblings, 1 reply; 28+ messages in thread
From: Peter Maydell @ 2016-11-04 13:30 UTC (permalink / raw)
To: Julian Brown; +Cc: QEMU Developers
On 3 November 2016 at 17:30, Julian Brown <julian@codesourcery.com> wrote:
> Thumb-1 code has some issues in BE32 mode (as currently implemented). In
> short, since bytes are swapped within words at load time for BE32
> executables, this also swaps pairs of adjacent Thumb-1 instructions.
>
> This patch un-swaps those pairs of instructions again, both for execution,
> and for disassembly.
>
> Signed-off-by: Julian Brown <julian@codesourcery.com>
> ---
> disas/arm.c | 46 +++++++++++++++++++++++++++++++++++-----------
> include/disas/bfd.h | 1 +
> target-arm/arm_ldst.h | 10 +++++++++-
> target-arm/cpu.c | 4 ++++
> 4 files changed, 49 insertions(+), 12 deletions(-)
>
> diff --git a/disas/arm.c b/disas/arm.c
> index 93c6503..4807ba3 100644
> --- a/disas/arm.c
> +++ b/disas/arm.c
> @@ -3863,10 +3863,11 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info)
> int is_data = false;
> unsigned int size = 4;
> void (*printer) (bfd_vma, struct disassemble_info *, long);
> - int little;
> + int little, is_thumb1_be32 = false;
>
> little = (info->endian == BFD_ENDIAN_LITTLE);
> is_thumb |= (pc & 1);
> + is_thumb1_be32 = (info->flags & INSN_ARM_THUMB1_BE32) != 0;
> pc &= ~(bfd_vma)1;
>
> if (force_thumb)
> @@ -3915,11 +3916,22 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info)
> info->bytes_per_chunk = 2;
> size = 2;
>
> - status = info->read_memory_func (pc, (bfd_byte *)b, 2, info);
> - if (little)
> - given = (b[0]) | (b[1] << 8);
> - else
> - given = (b[1]) | (b[0] << 8);
> + if (is_thumb1_be32) {
> + status = info->read_memory_func(pc & ~3, (bfd_byte *)b, 4, info);
> + assert(little);
> + if ((pc & 2) == 0) {
> + given = b[2] | (b[3] << 8);
> + } else {
> + given = b[0] | (b[1] << 8);
> + }
> + } else {
> + status = info->read_memory_func(pc, (bfd_byte *)b, 2, info);
> + if (little) {
> + given = (b[0]) | (b[1] << 8);
> + } else {
> + given = (b[1]) | (b[0] << 8);
> + }
> + }
Could we do this instead by changing the read_memory_func() so that it
did the appropriate XORing of addresses ? (Chaining through to
the original read_memory_func would be a bit irritating as you'd
need to find a place to stash that function pointer where you
could get at it again from the new read_memory_func.)
thanks
-- PMM
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [Qemu-devel] [PATCH 2/5] Fix Thumb-1 BE32 execution and disassembly.
2016-11-04 13:30 ` Peter Maydell
@ 2016-11-04 14:04 ` Julian Brown
2016-12-06 15:12 ` Julian Brown
0 siblings, 1 reply; 28+ messages in thread
From: Julian Brown @ 2016-11-04 14:04 UTC (permalink / raw)
To: Peter Maydell; +Cc: QEMU Developers
On Fri, 4 Nov 2016 13:30:12 +0000
Peter Maydell <peter.maydell@linaro.org> wrote:
> On 3 November 2016 at 17:30, Julian Brown <julian@codesourcery.com>
> wrote:
> > Thumb-1 code has some issues in BE32 mode (as currently
> > implemented). In short, since bytes are swapped within words at
> > load time for BE32 executables, this also swaps pairs of adjacent
> > Thumb-1 instructions.
> >
> > This patch un-swaps those pairs of instructions again, both for
> > execution, and for disassembly.
> >
> > Signed-off-by: Julian Brown <julian@codesourcery.com>
> > ---
> > disas/arm.c | 46
> > +++++++++++++++++++++++++++++++++++-----------
> > include/disas/bfd.h | 1 + target-arm/arm_ldst.h | 10 +++++++++-
> > target-arm/cpu.c | 4 ++++
> > 4 files changed, 49 insertions(+), 12 deletions(-)
> >
> > diff --git a/disas/arm.c b/disas/arm.c
> > index 93c6503..4807ba3 100644
> > --- a/disas/arm.c
> > +++ b/disas/arm.c
> > @@ -3863,10 +3863,11 @@ print_insn_arm (bfd_vma pc, struct
> > disassemble_info *info) int is_data = false;
> > unsigned int size = 4;
> > void (*printer) (bfd_vma, struct disassemble_info *,
> > long);
> > - int little;
> > + int little, is_thumb1_be32 = false;
> >
> > little = (info->endian == BFD_ENDIAN_LITTLE);
> > is_thumb |= (pc & 1);
> > + is_thumb1_be32 = (info->flags & INSN_ARM_THUMB1_BE32) != 0;
> > pc &= ~(bfd_vma)1;
> >
> > if (force_thumb)
> > @@ -3915,11 +3916,22 @@ print_insn_arm (bfd_vma pc, struct
> > disassemble_info *info) info->bytes_per_chunk = 2;
> > size = 2;
> >
> > - status = info->read_memory_func (pc, (bfd_byte *)b, 2, info);
> > - if (little)
> > - given = (b[0]) | (b[1] << 8);
> > - else
> > - given = (b[1]) | (b[0] << 8);
> > + if (is_thumb1_be32) {
> > + status = info->read_memory_func(pc & ~3, (bfd_byte *)b,
> > 4, info);
> > + assert(little);
> > + if ((pc & 2) == 0) {
> > + given = b[2] | (b[3] << 8);
> > + } else {
> > + given = b[0] | (b[1] << 8);
> > + }
> > + } else {
> > + status = info->read_memory_func(pc, (bfd_byte *)b, 2,
> > info);
> > + if (little) {
> > + given = (b[0]) | (b[1] << 8);
> > + } else {
>
> > + given = (b[1]) | (b[0] << 8);
> > + }
> > + }
>
> Could we do this instead by changing the read_memory_func() so that it
> did the appropriate XORing of addresses ? (Chaining through to
> the original read_memory_func would be a bit irritating as you'd
> need to find a place to stash that function pointer where you
> could get at it again from the new read_memory_func.)
Hmm, not sure. I'll try to think about whether that can be done nicely.
Julian
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [Qemu-devel] [PATCH 1/5] ARM BE8/BE32 semihosting and gdbstub support.
2016-11-03 22:23 ` Peter Maydell
2016-11-03 23:34 ` Julian Brown
2016-11-04 9:03 ` Paolo Bonzini
@ 2016-12-06 15:11 ` Julian Brown
2016-12-06 15:44 ` Peter Maydell
2 siblings, 1 reply; 28+ messages in thread
From: Julian Brown @ 2016-12-06 15:11 UTC (permalink / raw)
To: Peter Maydell; +Cc: QEMU Developers, Paolo Bonzini
[-- Attachment #1: Type: text/plain, Size: 984 bytes --]
On Thu, 3 Nov 2016 22:23:09 +0000
Peter Maydell <peter.maydell@linaro.org> wrote:
> Strong 'no' for the approach of having different CPU
> names, I'm afraid. What you want is to have a CPU
> property which works like the hardware CPU's CFGEND
> signal to set the reset value of the SCTLR.EE bit. Then
> a board can use that where it would wire up CFGEND
> in real hardware, and on the command line you can
> have -cpu whatever,cfgend=yes (which is a bit ugly
> but then it's borderline whether it makes any sense at
> all for the user to be able to set the endianness on
> the commandline).
How about something like this? (Re-testing these patches has taken a
while because I hit apparent reliability problems running GDB tests
against the trunk QEMU: I filed
https://bugs.launchpad.net/qemu/+bug/1647683 for that).
(There's some slight dubiousness about memory ownership with the GLIB
functions -- I don't have a good handle on that, really, but I think
it's OK.)
Thanks,
Julian
[-- Attachment #2: 0001-ARM-BE8-BE32-semihosting-and-gdbstub-support.patch --]
[-- Type: text/x-patch, Size: 15154 bytes --]
>From d76129fb9ab60df696af6bc4911041f95b3a560b Mon Sep 17 00:00:00 2001
From: Julian Brown <julian@codesourcery.com>
Date: Tue, 1 Nov 2016 08:35:48 -0700
Subject: [PATCH 1/4] ARM BE8/BE32 semihosting and gdbstub support.
This patch improves support for semihosting and debugging with the
in-built gdbstub for ARM system-mode emulation in big-endian mode (either
BE8 or BE32), after the fairly recent changes to allow a single QEMU
binary to deal with each of LE, BE8 and BE32 modes in one. It's only
currently good for little-endian host systems. The relevant use case
is using QEMU as a "bare metal" instruction-set simulator, e.g. for
toolchain testing.
For semihosting, the softmmu-semi.h file is overridden with an
ARM-specific version that knows about byte-swapping target memory into
host order -- including that which has been byte-swapped at load time
for BE32 mode.
For the gdbstub, we'd like to be able to invoke QEMU from GDB like:
(gdb) target remote | arm-qemu-system -cpu=foo [options] /dev/null
(gdb) load
(gdb) ...
which unfortunately bypasses the probing of the loaded ELF file (since
it's just /dev/null) to determine whether to use BE8/BE32 mode. A
"cfgend" boolean parameter has been added for this scenario, mirroring
the configuration input on (some?) ARM cores, to choose a core-appropriate
big-endian mode at reset. (Use e.g. -cpu=arm926,cfgend=yes).
Signed-off-by: Julian Brown <julian@codesourcery.com>
---
hw/arm/boot.c | 16 ++++-
include/exec/softmmu-arm-semi.h | 148 ++++++++++++++++++++++++++++++++++++++++
target-arm/arm-semi.c | 2 +-
target-arm/cpu.c | 52 +++++++++++++-
target-arm/cpu.h | 12 ++++
target-arm/gdbstub.c | 42 ++++++++++++
6 files changed, 267 insertions(+), 5 deletions(-)
create mode 100644 include/exec/softmmu-arm-semi.h
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index 942416d..68a6574 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -894,7 +894,21 @@ static void arm_load_kernel_notify(Notifier *notifier, void *data)
entry = info->loader_start + kernel_load_offset;
kernel_size = load_image_targphys(info->kernel_filename, entry,
info->ram_size - kernel_load_offset);
- is_linux = 1;
+ if (kernel_size > 0) {
+ is_linux = 1;
+ } else {
+ /* We've been launched with a kernel of /dev/null or similar.
+ * Infer endianness from the reset value of the SCTLR for this
+ * CPU/board. (This can be altered using the cfgend parameter.)
+ */
+ if (!arm_feature(&cpu->env, ARM_FEATURE_V7) &&
+ (cpu->reset_sctlr & SCTLR_B) != 0)
+ info->endianness = ARM_ENDIANNESS_BE32;
+ else if ((cpu->reset_sctlr & SCTLR_EE) != 0)
+ info->endianness = ARM_ENDIANNESS_BE8;
+ else
+ info->endianness = ARM_ENDIANNESS_LE;
+ }
}
if (kernel_size < 0) {
fprintf(stderr, "qemu: could not load kernel '%s'\n",
diff --git a/include/exec/softmmu-arm-semi.h b/include/exec/softmmu-arm-semi.h
new file mode 100644
index 0000000..d97e017
--- /dev/null
+++ b/include/exec/softmmu-arm-semi.h
@@ -0,0 +1,148 @@
+/*
+ * Helper routines to provide target memory access for ARM semihosting
+ * syscalls in system emulation mode.
+ *
+ * Copyright (c) 2007 CodeSourcery, (c) 2016 Mentor Graphics
+ *
+ * This code is licensed under the GPL
+ */
+
+#ifndef SOFTMMU_ARM_SEMI_H
+#define SOFTMMU_ARM_SEMI_H 1
+
+/* In BE32 system mode, the CPU-specific memory_rw_debug method will arrange to
+ * perform byteswapping on the target memory, so that it appears to the host as
+ * it appears to the emulated CPU. Memory is read verbatim in BE8 mode. (In
+ * other words, this function arranges so that BUF has the same format in both
+ * BE8 and BE32 system mode.)
+ */
+
+static inline int armsemi_memory_rw_debug(CPUState *cpu, target_ulong addr,
+ uint8_t *buf, int len, bool is_write)
+{
+ CPUClass *cc = CPU_GET_CLASS(cpu);
+
+ if (cc->memory_rw_debug) {
+ return cc->memory_rw_debug(cpu, addr, buf, len, is_write);
+ }
+ return cpu_memory_rw_debug(cpu, addr, buf, len, is_write);
+}
+
+/* In big-endian mode (either BE8 or BE32), values larger than a byte will be
+ * transferred to/from memory in big-endian format. Assuming we're on a
+ * little-endian host machine, such values will need to be byteswapped before
+ * and after the host processes them.
+ *
+ * This means that byteswapping will occur *twice* in BE32 mode for
+ * halfword/word reads/writes.
+ */
+
+static inline bool arm_bswap_needed(CPUARMState *env)
+{
+#ifdef HOST_WORDS_BIGENDIAN
+#error HOST_WORDS_BIGENDIAN is not supported for ARM semihosting at the moment.
+#else
+ return arm_sctlr_b(env) || arm_sctlr_ee(env);
+#endif
+}
+
+static inline uint64_t softmmu_tget64(CPUArchState *env, target_ulong addr)
+{
+ uint64_t val;
+
+ armsemi_memory_rw_debug(ENV_GET_CPU(env), addr, (uint8_t *)&val, 8, 0);
+ if (arm_bswap_needed(env)) {
+ return bswap64(val);
+ } else {
+ return val;
+ }
+}
+
+static inline uint32_t softmmu_tget32(CPUArchState *env, target_ulong addr)
+{
+ uint32_t val;
+
+ armsemi_memory_rw_debug(ENV_GET_CPU(env), addr, (uint8_t *)&val, 4, 0);
+ if (arm_bswap_needed(env)) {
+ return bswap32(val);
+ } else {
+ return val;
+ }
+}
+
+static inline uint32_t softmmu_tget8(CPUArchState *env, target_ulong addr)
+{
+ uint8_t val;
+ armsemi_memory_rw_debug(ENV_GET_CPU(env), addr, &val, 1, 0);
+ return val;
+}
+
+#define get_user_u64(arg, p) ({ arg = softmmu_tget64(env, p); 0; })
+#define get_user_u32(arg, p) ({ arg = softmmu_tget32(env, p) ; 0; })
+#define get_user_u8(arg, p) ({ arg = softmmu_tget8(env, p) ; 0; })
+#define get_user_ual(arg, p) get_user_u32(arg, p)
+
+static inline void softmmu_tput64(CPUArchState *env,
+ target_ulong addr, uint64_t val)
+{
+ if (arm_bswap_needed(env)) {
+ val = bswap64(val);
+ }
+ cpu_memory_rw_debug(ENV_GET_CPU(env), addr, (uint8_t *)&val, 8, 1);
+}
+
+static inline void softmmu_tput32(CPUArchState *env,
+ target_ulong addr, uint32_t val)
+{
+ if (arm_bswap_needed(env)) {
+ val = bswap32(val);
+ }
+ armsemi_memory_rw_debug(ENV_GET_CPU(env), addr, (uint8_t *)&val, 4, 1);
+}
+#define put_user_u64(arg, p) ({ softmmu_tput64(env, p, arg) ; 0; })
+#define put_user_u32(arg, p) ({ softmmu_tput32(env, p, arg) ; 0; })
+#define put_user_ual(arg, p) put_user_u32(arg, p)
+
+static void *softmmu_lock_user(CPUArchState *env,
+ target_ulong addr, target_ulong len, int copy)
+{
+ uint8_t *p;
+ /* TODO: Make this something that isn't fixed size. */
+ p = malloc(len);
+ if (p && copy) {
+ armsemi_memory_rw_debug(ENV_GET_CPU(env), addr, p, len, 0);
+ }
+ return p;
+}
+#define lock_user(type, p, len, copy) softmmu_lock_user(env, p, len, copy)
+static char *softmmu_lock_user_string(CPUArchState *env, target_ulong addr)
+{
+ char *p;
+ char *s;
+ uint8_t c;
+ /* TODO: Make this something that isn't fixed size. */
+ s = p = malloc(1024);
+ if (!s) {
+ return NULL;
+ }
+ do {
+ armsemi_memory_rw_debug(ENV_GET_CPU(env), addr, &c, 1, 0);
+ addr++;
+ *(p++) = c;
+ } while (c);
+ return s;
+}
+#define lock_user_string(p) softmmu_lock_user_string(env, p)
+static void softmmu_unlock_user(CPUArchState *env, void *p, target_ulong addr,
+ target_ulong len)
+{
+ uint8_t *pc = p;
+ if (len) {
+ armsemi_memory_rw_debug(ENV_GET_CPU(env), addr, p, len, 1);
+ }
+ free(p);
+}
+
+#define unlock_user(s, args, len) softmmu_unlock_user(env, s, args, len)
+
+#endif
diff --git a/target-arm/arm-semi.c b/target-arm/arm-semi.c
index 7cac873..a9cf5f2 100644
--- a/target-arm/arm-semi.c
+++ b/target-arm/arm-semi.c
@@ -114,7 +114,7 @@ static inline uint32_t set_swi_errno(CPUARMState *env, uint32_t code)
return code;
}
-#include "exec/softmmu-semi.h"
+#include "exec/softmmu-arm-semi.h"
#endif
static target_ulong arm_semi_syscall_len;
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 2eb4098..6afb0d9 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -33,6 +33,7 @@
#include "sysemu/sysemu.h"
#include "sysemu/kvm.h"
#include "kvm_arm.h"
+#include "exec/cpu-common.h"
static void arm_cpu_set_pc(CPUState *cs, vaddr value)
{
@@ -497,6 +498,9 @@ static Property arm_cpu_rvbar_property =
static Property arm_cpu_has_el3_property =
DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true);
+static Property arm_cpu_cfgend_property =
+ DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false);
+
/* use property name "pmu" to match other archs and virt tools */
static Property arm_cpu_has_pmu_property =
DEFINE_PROP_BOOL("pmu", ARMCPU, has_pmu, true);
@@ -559,6 +563,18 @@ static void arm_cpu_post_init(Object *obj)
}
}
+ qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property,
+ &error_abort);
+
+ qdev_prop_set_globals(DEVICE(obj));
+
+ if (object_property_get_bool(obj, "cfgend", NULL)) {
+ if (arm_feature(&cpu->env, ARM_FEATURE_V7)) {
+ cpu->reset_sctlr |= SCTLR_EE;
+ } else {
+ cpu->reset_sctlr |= SCTLR_B;
+ }
+ }
}
static void arm_cpu_finalizefn(Object *obj)
@@ -758,6 +774,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
{
ObjectClass *oc;
+ CPUClass *cc;
char *typename;
char **cpuname;
@@ -765,15 +782,20 @@ static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
return NULL;
}
- cpuname = g_strsplit(cpu_model, ",", 1);
+ cpuname = g_strsplit(cpu_model, ",", 2);
typename = g_strdup_printf("%s-" TYPE_ARM_CPU, cpuname[0]);
oc = object_class_by_name(typename);
- g_strfreev(cpuname);
- g_free(typename);
if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) ||
object_class_is_abstract(oc)) {
+ g_strfreev(cpuname);
+ g_free(typename);
return NULL;
}
+
+ cc = CPU_CLASS(oc);
+ cc->parse_features(typename, cpuname[1], &error_fatal);
+ g_strfreev(cpuname);
+
return oc;
}
@@ -1534,6 +1556,27 @@ static gchar *arm_gdb_arch_name(CPUState *cs)
return g_strdup("arm");
}
+#ifndef CONFIG_USER_ONLY
+static int arm_cpu_memory_rw_debug(CPUState *cpu, vaddr address,
+ uint8_t *buf, int len, bool is_write)
+{
+ target_ulong addr = address;
+ ARMCPU *armcpu = ARM_CPU(cpu);
+ CPUARMState *env = &armcpu->env;
+
+ if (arm_sctlr_b(env)) {
+ target_ulong i;
+ for (i = 0; i < len; i++) {
+ cpu_memory_rw_debug(cpu, (addr + i) ^ 3, &buf[i], 1, is_write);
+ }
+ } else {
+ cpu_memory_rw_debug(cpu, addr, buf, len, is_write);
+ }
+
+ return 0;
+}
+#endif
+
static void arm_cpu_class_init(ObjectClass *oc, void *data)
{
ARMCPUClass *acc = ARM_CPU_CLASS(oc);
@@ -1551,6 +1594,9 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
cc->has_work = arm_cpu_has_work;
cc->cpu_exec_interrupt = arm_cpu_exec_interrupt;
cc->dump_state = arm_cpu_dump_state;
+#if !defined(CONFIG_USER_ONLY)
+ cc->memory_rw_debug = arm_cpu_memory_rw_debug;
+#endif
cc->set_pc = arm_cpu_set_pc;
cc->gdb_read_register = arm_cpu_gdb_read_register;
cc->gdb_write_register = arm_cpu_gdb_write_register;
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index ca5c849..03f19ab 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -657,6 +657,12 @@ struct ARMCPU {
uint32_t dcz_blocksize;
uint64_t rvbar;
+ /* Whether the cfgend input is high (i.e. this CPU should reset into
+ big-endian mode). This setting isn't used directly: instead it modifies
+ the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the
+ architecture version. */
+ bool cfgend;
+
ARMELChangeHook *el_change_hook;
void *el_change_hook_opaque;
};
@@ -2108,6 +2114,12 @@ static inline bool arm_sctlr_b(CPUARMState *env)
(env->cp15.sctlr_el[1] & SCTLR_B) != 0;
}
+static inline bool arm_sctlr_ee(CPUARMState *env)
+{
+ return arm_feature(env, ARM_FEATURE_V7) &&
+ (env->cp15.sctlr_el[1] & SCTLR_EE) != 0;
+}
+
/* Return true if the processor is in big-endian mode. */
static inline bool arm_cpu_data_is_big_endian(CPUARMState *env)
{
diff --git a/target-arm/gdbstub.c b/target-arm/gdbstub.c
index 04c1208..1e9fe68 100644
--- a/target-arm/gdbstub.c
+++ b/target-arm/gdbstub.c
@@ -21,6 +21,7 @@
#include "qemu-common.h"
#include "cpu.h"
#include "exec/gdbstub.h"
+#include "exec/softmmu-arm-semi.h"
/* Old gdb always expect FPA registers. Newer (xml-aware) gdb only expect
whatever the target description contains. Due to a historical mishap
@@ -32,10 +33,22 @@ int arm_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
{
ARMCPU *cpu = ARM_CPU(cs);
CPUARMState *env = &cpu->env;
+#ifndef CONFIG_USER_ONLY
+ bool targ_bigendian = arm_bswap_needed(env);
+#endif
if (n < 16) {
/* Core integer register. */
+#ifdef CONFIG_USER_ONLY
return gdb_get_reg32(mem_buf, env->regs[n]);
+#else
+ if (targ_bigendian) {
+ stl_be_p(mem_buf, env->regs[n]);
+ } else {
+ stl_le_p(mem_buf, env->regs[n]);
+ }
+ return 4;
+#endif
}
if (n < 24) {
/* FPA registers. */
@@ -51,10 +64,28 @@ int arm_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
if (gdb_has_xml) {
return 0;
}
+#ifdef CONFIG_USER_ONLY
return gdb_get_reg32(mem_buf, 0);
+#else
+ if (targ_bigendian) {
+ stl_be_p(mem_buf, 0);
+ } else {
+ stl_le_p(mem_buf, 0);
+ }
+ return 4;
+#endif
case 25:
/* CPSR */
+#ifdef CONFIG_USER_ONLY
return gdb_get_reg32(mem_buf, cpsr_read(env));
+#else
+ if (targ_bigendian) {
+ stl_be_p(mem_buf, cpsr_read(env));
+ } else {
+ stl_le_p(mem_buf, cpsr_read(env));
+ }
+ return 4;
+#endif
}
/* Unknown register. */
return 0;
@@ -65,8 +96,19 @@ int arm_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
ARMCPU *cpu = ARM_CPU(cs);
CPUARMState *env = &cpu->env;
uint32_t tmp;
+#ifndef CONFIG_USER_ONLY
+ bool targ_bigendian = arm_bswap_needed(env);
+#endif
+#ifdef CONFIG_USER_ONLY
tmp = ldl_p(mem_buf);
+#else
+ if (targ_bigendian) {
+ tmp = ldl_be_p(mem_buf);
+ } else {
+ tmp = ldl_le_p(mem_buf);
+ }
+#endif
/* Mask out low bit of PC to workaround gdb bugs. This will probably
cause problems if we ever implement the Jazelle DBX extensions. */
--
1.9.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* Re: [Qemu-devel] [PATCH 3/5] Fix arm_semi_flen_cb for BE32 system mode.
2016-11-04 9:00 ` Paolo Bonzini
@ 2016-12-06 15:11 ` Julian Brown
0 siblings, 0 replies; 28+ messages in thread
From: Julian Brown @ 2016-12-06 15:11 UTC (permalink / raw)
To: Paolo Bonzini; +Cc: qemu-devel
[-- Attachment #1: Type: text/plain, Size: 652 bytes --]
On Fri, 4 Nov 2016 10:00:19 +0100
Paolo Bonzini <pbonzini@redhat.com> wrote:
> On 03/11/2016 18:30, Julian Brown wrote:
> > +#ifdef CONFIG_USER_ONLY
> > size = be32_to_cpu(size);
> > +#else
> > + /* If we're running in BE32 system mode, we don't need to do
> > an explicit
> > + * byte swap, because (I think) target memory is already
> > stored in
> > + * byte-swapped format.
>
> Isn't this true also of user-mode (both BE8 and BE32)?
I'm not sure, I don't think the "load-time" byteswapping affects user
mode in the same way. Anyway, this can be refactored as attached, which
looks a bit more plausible perhaps.
Thanks,
Julian
[-- Attachment #2: 0004-Fix-arm_semi_flen_cb-for-BE32-system-mode.patch --]
[-- Type: text/x-patch, Size: 1064 bytes --]
>From 0e5d7e43404250900bfea3f8dc21fefa59069190 Mon Sep 17 00:00:00 2001
From: Julian Brown <julian@codesourcery.com>
Date: Thu, 6 Oct 2016 04:02:08 -0700
Subject: [PATCH 4/4] Fix arm_semi_flen_cb for BE32 system mode.
This patch fixes the arm_semi_flen_cb callback so that it doesn't return
a byte-swapped size in BE32 system mode.
---
target-arm/arm-semi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-arm/arm-semi.c b/target-arm/arm-semi.c
index a9cf5f2..1ad1e63 100644
--- a/target-arm/arm-semi.c
+++ b/target-arm/arm-semi.c
@@ -187,7 +187,7 @@ static void arm_semi_flen_cb(CPUState *cs, target_ulong ret, target_ulong err)
/* The size is always stored in big-endian order, extract
the value. We assume the size always fit in 32 bits. */
uint32_t size;
- cpu_memory_rw_debug(cs, arm_flen_buf(cpu) + 32, (uint8_t *)&size, 4, 0);
+ armsemi_memory_rw_debug(cs, arm_flen_buf(cpu) + 32, (uint8_t *)&size, 4, 0);
size = be32_to_cpu(size);
if (is_a64(env)) {
env->xregs[0] = size;
--
1.9.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* Re: [Qemu-devel] [PATCH 2/5] Fix Thumb-1 BE32 execution and disassembly.
2016-11-04 14:04 ` Julian Brown
@ 2016-12-06 15:12 ` Julian Brown
0 siblings, 0 replies; 28+ messages in thread
From: Julian Brown @ 2016-12-06 15:12 UTC (permalink / raw)
To: Peter Maydell; +Cc: QEMU Developers
[-- Attachment #1: Type: text/plain, Size: 3222 bytes --]
On Fri, 4 Nov 2016 14:04:24 +0000
Julian Brown <julian@codesourcery.com> wrote:
> On Fri, 4 Nov 2016 13:30:12 +0000
> Peter Maydell <peter.maydell@linaro.org> wrote:
>
> > On 3 November 2016 at 17:30, Julian Brown <julian@codesourcery.com>
> > wrote:
> > > Thumb-1 code has some issues in BE32 mode (as currently
> > > implemented). In short, since bytes are swapped within words at
> > > load time for BE32 executables, this also swaps pairs of adjacent
> > > Thumb-1 instructions.
> > >
> > > This patch un-swaps those pairs of instructions again, both for
> > > execution, and for disassembly.
> > >
> > > Signed-off-by: Julian Brown <julian@codesourcery.com>
> > > ---
> > > disas/arm.c | 46
> > > +++++++++++++++++++++++++++++++++++-----------
> > > include/disas/bfd.h | 1 + target-arm/arm_ldst.h | 10 +++++++++-
> > > target-arm/cpu.c | 4 ++++
> > > 4 files changed, 49 insertions(+), 12 deletions(-)
> > >
> > > diff --git a/disas/arm.c b/disas/arm.c
> > > index 93c6503..4807ba3 100644
> > > --- a/disas/arm.c
> > > +++ b/disas/arm.c
> > > @@ -3863,10 +3863,11 @@ print_insn_arm (bfd_vma pc, struct
> > > disassemble_info *info) int is_data = false;
> > > unsigned int size = 4;
> > > void (*printer) (bfd_vma, struct disassemble_info *,
> > > long);
> > > - int little;
> > > + int little, is_thumb1_be32 = false;
> > >
> > > little = (info->endian == BFD_ENDIAN_LITTLE);
> > > is_thumb |= (pc & 1);
> > > + is_thumb1_be32 = (info->flags & INSN_ARM_THUMB1_BE32) != 0;
> > > pc &= ~(bfd_vma)1;
> > >
> > > if (force_thumb)
> > > @@ -3915,11 +3916,22 @@ print_insn_arm (bfd_vma pc, struct
> > > disassemble_info *info) info->bytes_per_chunk = 2;
> > > size = 2;
> > >
> > > - status = info->read_memory_func (pc, (bfd_byte *)b, 2,
> > > info);
> > > - if (little)
> > > - given = (b[0]) | (b[1] << 8);
> > > - else
> > > - given = (b[1]) | (b[0] << 8);
> > > + if (is_thumb1_be32) {
> > > + status = info->read_memory_func(pc & ~3, (bfd_byte *)b,
> > > 4, info);
> > > + assert(little);
> > > + if ((pc & 2) == 0) {
> > > + given = b[2] | (b[3] << 8);
> > > + } else {
> > > + given = b[0] | (b[1] << 8);
> > > + }
> > > + } else {
> > > + status = info->read_memory_func(pc, (bfd_byte *)b, 2,
> > > info);
> > > + if (little) {
> > > + given = (b[0]) | (b[1] << 8);
> > > + } else {
> >
> > > + given = (b[1]) | (b[0] << 8);
> > > + }
> > > + }
> >
> > Could we do this instead by changing the read_memory_func() so that
> > it did the appropriate XORing of addresses ? (Chaining through to
> > the original read_memory_func would be a bit irritating as you'd
> > need to find a place to stash that function pointer where you
> > could get at it again from the new read_memory_func.)
>
> Hmm, not sure. I'll try to think about whether that can be done
> nicely.
How about this? I've kept the INSN_ARM_THUMB1_BE32 flag, but it's not
100% certain if it's still required. There's probably less
function-pointer trickery with it left in.
Thanks,
Julian
[-- Attachment #2: 0002-Fix-Thumb-1-BE32-execution-and-disassembly.patch --]
[-- Type: text/x-patch, Size: 4934 bytes --]
>From 852098f65becab24648adce97f93d0c87aa474cd Mon Sep 17 00:00:00 2001
From: Julian Brown <julian@codesourcery.com>
Date: Wed, 5 Oct 2016 09:26:44 -0700
Subject: [PATCH 2/4] Fix Thumb-1 BE32 execution and disassembly.
Thumb-1 code has some issues in BE32 mode (as currently implemented). In
short, since bytes are swapped within words at load time for BE32
executables, this also swaps pairs of adjacent Thumb-1 instructions.
This patch un-swaps those pairs of instructions again, both for execution,
and for disassembly.
---
disas.c | 1 +
include/disas/bfd.h | 7 +++++++
target-arm/arm_ldst.h | 10 +++++++++-
target-arm/cpu.c | 32 ++++++++++++++++++++++++++++++++
4 files changed, 49 insertions(+), 1 deletion(-)
diff --git a/disas.c b/disas.c
index 67f116a..506e56f 100644
--- a/disas.c
+++ b/disas.c
@@ -190,6 +190,7 @@ void target_disas(FILE *out, CPUState *cpu, target_ulong code,
s.cpu = cpu;
s.info.read_memory_func = target_read_memory;
+ s.info.read_memory_inner_func = NULL;
s.info.buffer_vma = code;
s.info.buffer_length = size;
s.info.print_address_func = generic_print_address;
diff --git a/include/disas/bfd.h b/include/disas/bfd.h
index 8a3488c..5c1e1c5 100644
--- a/include/disas/bfd.h
+++ b/include/disas/bfd.h
@@ -291,6 +291,7 @@ typedef struct disassemble_info {
The bottom 16 bits are for the internal use of the disassembler. */
unsigned long flags;
#define INSN_HAS_RELOC 0x80000000
+#define INSN_ARM_THUMB1_BE32 0x00010000
PTR private_data;
/* Function used to get bytes to disassemble. MEMADDR is the
@@ -302,6 +303,12 @@ typedef struct disassemble_info {
(bfd_vma memaddr, bfd_byte *myaddr, int length,
struct disassemble_info *info);
+ /* A place to stash the real read_memory_func if read_memory_func wants to
+ do some funky address arithmetic or similar (e.g. for ARM BE32 mode). */
+ int (*read_memory_inner_func)
+ (bfd_vma memaddr, bfd_byte *myaddr, int length,
+ struct disassemble_info *info);
+
/* Function which should be called if we get an error that we can't
recover from. STATUS is the errno value from read_memory_func and
MEMADDR is the address that we were trying to read. INFO is a
diff --git a/target-arm/arm_ldst.h b/target-arm/arm_ldst.h
index a76d89f..01587b3 100644
--- a/target-arm/arm_ldst.h
+++ b/target-arm/arm_ldst.h
@@ -39,7 +39,15 @@ static inline uint32_t arm_ldl_code(CPUARMState *env, target_ulong addr,
static inline uint16_t arm_lduw_code(CPUARMState *env, target_ulong addr,
bool sctlr_b)
{
- uint16_t insn = cpu_lduw_code(env, addr);
+ uint16_t insn;
+#ifndef CONFIG_USER_ONLY
+ /* In big-endian (BE32) mode, adjacent Thumb instructions have been swapped
+ within each word. Undo that now. */
+ if (sctlr_b) {
+ addr ^= 2;
+ }
+#endif
+ insn = cpu_lduw_code(env, addr);
if (bswap_code(sctlr_b)) {
return bswap16(insn);
}
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 6afb0d9..6099d50 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -409,6 +409,30 @@ print_insn_thumb1(bfd_vma pc, disassemble_info *info)
return print_insn_arm(pc | 1, info);
}
+static int arm_read_memory_func(bfd_vma memaddr, bfd_byte *myaddr,
+ int length, struct disassemble_info *info)
+{
+ assert(info->read_memory_inner_func);
+
+ if ((info->flags & INSN_ARM_THUMB1_BE32) != 0 && length == 2) {
+ int status;
+ unsigned char b[4];
+ assert(info->endian == BFD_ENDIAN_LITTLE);
+ status = info->read_memory_inner_func(memaddr & ~3, (bfd_byte *)b, 4,
+ info);
+ if ((memaddr & 2) == 0) {
+ myaddr[0] = b[2];
+ myaddr[1] = b[3];
+ } else {
+ myaddr[0] = b[0];
+ myaddr[1] = b[1];
+ }
+ return status;
+ } else {
+ return info->read_memory_inner_func(memaddr, myaddr, length, info);
+ }
+}
+
static void arm_disas_set_info(CPUState *cpu, disassemble_info *info)
{
ARMCPU *ac = ARM_CPU(cpu);
@@ -424,6 +448,10 @@ static void arm_disas_set_info(CPUState *cpu, disassemble_info *info)
#endif
} else if (env->thumb) {
info->print_insn = print_insn_thumb1;
+ info->flags &= ~INSN_ARM_THUMB1_BE32;
+ if (arm_sctlr_b(env)) {
+ info->flags |= INSN_ARM_THUMB1_BE32;
+ }
} else {
info->print_insn = print_insn_arm;
}
@@ -434,6 +462,10 @@ static void arm_disas_set_info(CPUState *cpu, disassemble_info *info)
info->endian = BFD_ENDIAN_BIG;
#endif
}
+ if (info->read_memory_inner_func == NULL) {
+ info->read_memory_inner_func = info->read_memory_func;
+ info->read_memory_func = arm_read_memory_func;
+ }
}
static void arm_cpu_initfn(Object *obj)
--
1.9.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* Re: [Qemu-devel] [PATCH 4/5] ARM BE32 watchpoint fix.
2016-11-04 8:55 ` Paolo Bonzini
@ 2016-12-06 15:12 ` Julian Brown
0 siblings, 0 replies; 28+ messages in thread
From: Julian Brown @ 2016-12-06 15:12 UTC (permalink / raw)
To: Paolo Bonzini; +Cc: Peter Maydell, QEMU Developers
[-- Attachment #1: Type: text/plain, Size: 2131 bytes --]
On Fri, 4 Nov 2016 09:55:17 +0100
Paolo Bonzini <pbonzini@redhat.com> wrote:
> On 04/11/2016 00:20, Julian Brown wrote:
> > On Thu, 3 Nov 2016 23:14:05 +0000
> > Peter Maydell <peter.maydell@linaro.org> wrote:
> >
> >> On 3 November 2016 at 17:30, Julian Brown <julian@codesourcery.com>
> >> wrote:
> >>> In BE32 mode, sub-word size watchpoints can fail to trigger
> >>> because the address of the access is adjusted in the opcode
> >>> helpers before being compared with the watchpoint registers.
> >>> This patch reversed the address adjustment before performing the
> >>> comparison.
> >>>
> >>> Signed-off-by: Julian Brown <julian@codesourcery.com>
> >>> ---
> >>> exec.c | 13 +++++++++++++
> >>> 1 file changed, 13 insertions(+)
> >>>
> >>> diff --git a/exec.c b/exec.c
> >>> index 4c84389..eadab54 100644
> >>> --- a/exec.c
> >>> +++ b/exec.c
> >>> @@ -2047,6 +2047,19 @@ static void check_watchpoint(int offset,
> >>> int len, MemTxAttrs attrs, int flags) return;
> >>> }
> >>> vaddr = (cpu->mem_io_vaddr & TARGET_PAGE_MASK) + offset;
> >>> +#if defined(TARGET_ARM) && !defined(CONFIG_USER_ONLY)
> >>> + /* In BE32 system mode, target memory is stored byteswapped
> >>> (FIXME:
> >>> + relative to a little-endian host system), and by the time
> >>> we reach here
> >>> + (via an opcode helper) the addresses of subword accesses
> >>> have been
> >>> + adjusted to account for that, which means that watchpoints
> >>> will not
> >>> + match. Undo the adjustment here. */
> >>> + if (arm_sctlr_b(env)) {
> >>> + if (len == 1)
> >>> + vaddr ^= 3;
> >>> + else if (len == 2)
> >>> + vaddr ^= 2;
> >>> + }
> >>> +#endif
> >>
> >> No target-CPU specific code in exec.c, please...
> >
> > Yeah, I'd imagine not. I struggled with this one. Any suggestions
> > for a better way to do this?
>
> You can add a function pointer to CPUClass and call it from here.
> It's how cc->debug_check_watchpoint is being called already.
How's this? There's still some grubbiness, but it's mostly confined to
the ARM backend code.
Thanks,
Julian
[-- Attachment #2: 0003-ARM-BE32-watchpoint-fix.patch --]
[-- Type: text/x-patch, Size: 4712 bytes --]
>From 7d9e9ab88060ab05faedff26b24f513e72c4795b Mon Sep 17 00:00:00 2001
From: Julian Brown <julian@codesourcery.com>
Date: Tue, 11 Oct 2016 02:00:40 -0700
Subject: [PATCH 3/4] ARM BE32 watchpoint fix.
In BE32 mode, sub-word size watchpoints can fail to trigger because the
address of the access is adjusted in the opcode helpers before being
compared with the watchpoint registers. This patch reverses the address
adjustment before performing the comparison with the help of a new CPUClass
hook.
---
exec.c | 1 +
include/qom/cpu.h | 1 +
qom/cpu.c | 6 ++++++
target-arm/cpu.c | 3 +++
target-arm/internals.h | 5 +++++
target-arm/op_helper.c | 22 ++++++++++++++++++++++
6 files changed, 38 insertions(+)
diff --git a/exec.c b/exec.c
index 3d867f1..1c65e22 100644
--- a/exec.c
+++ b/exec.c
@@ -2090,6 +2090,7 @@ static void check_watchpoint(int offset, int len, MemTxAttrs attrs, int flags)
return;
}
vaddr = (cpu->mem_io_vaddr & TARGET_PAGE_MASK) + offset;
+ vaddr = cc->adjust_watchpoint_address(cpu, vaddr, len);
QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
if (cpu_watchpoint_address_matches(wp, vaddr, len)
&& (wp->flags & flags)) {
diff --git a/include/qom/cpu.h b/include/qom/cpu.h
index 0d18b58..c100ec2 100644
--- a/include/qom/cpu.h
+++ b/include/qom/cpu.h
@@ -195,6 +195,7 @@ typedef struct CPUClass {
bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request);
void (*disas_set_info)(CPUState *cpu, disassemble_info *info);
+ vaddr (*adjust_watchpoint_address)(CPUState *cpu, vaddr addr, int len);
} CPUClass;
#ifdef HOST_WORDS_BIGENDIAN
diff --git a/qom/cpu.c b/qom/cpu.c
index 03d9190..9ad07c8 100644
--- a/qom/cpu.c
+++ b/qom/cpu.c
@@ -383,6 +383,11 @@ static int64_t cpu_common_get_arch_id(CPUState *cpu)
return cpu->cpu_index;
}
+static vaddr cpu_adjust_watchpoint_address(CPUState *cpu, vaddr addr, int len)
+{
+ return addr;
+}
+
static void cpu_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
@@ -407,6 +412,7 @@ static void cpu_class_init(ObjectClass *klass, void *data)
k->cpu_exec_enter = cpu_common_noop;
k->cpu_exec_exit = cpu_common_noop;
k->cpu_exec_interrupt = cpu_common_exec_interrupt;
+ k->adjust_watchpoint_address = cpu_adjust_watchpoint_address;
dc->realize = cpu_common_realizefn;
dc->unrealize = cpu_common_unrealizefn;
/*
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 6099d50..a609211 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -1650,6 +1650,9 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_stop_before_watchpoint = true;
cc->debug_excp_handler = arm_debug_excp_handler;
cc->debug_check_watchpoint = arm_debug_check_watchpoint;
+#if !defined(CONFIG_USER_ONLY)
+ cc->adjust_watchpoint_address = arm_adjust_watchpoint_address;
+#endif
cc->disas_set_info = arm_disas_set_info;
}
diff --git a/target-arm/internals.h b/target-arm/internals.h
index 3edccd2..132f8d0 100644
--- a/target-arm/internals.h
+++ b/target-arm/internals.h
@@ -437,6 +437,11 @@ void hw_breakpoint_update_all(ARMCPU *cpu);
/* Callback function for checking if a watchpoint should trigger. */
bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp);
+/* Adjust addresses (in BE32 mode) before testing against watchpoint
+ * addresses.
+ */
+vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len);
+
/* Callback function for when a watchpoint or breakpoint triggers. */
void arm_debug_excp_handler(CPUState *cs);
diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c
index cd94216..dc92e49 100644
--- a/target-arm/op_helper.c
+++ b/target-arm/op_helper.c
@@ -1216,6 +1216,28 @@ bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp)
return check_watchpoints(cpu);
}
+vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len)
+{
+ ARMCPU *cpu = ARM_CPU(cs);
+ CPUARMState *env = &cpu->env;
+
+ /* In BE32 system mode, target memory is stored byteswapped (FIXME:
+ * relative to a little-endian host system), and by the time we reach here
+ * (via an opcode helper) the addresses of subword accesses have been
+ * adjusted to account for that, which means that watchpoints will not
+ * match. Undo the adjustment here.
+ */
+ if (arm_sctlr_b(env)) {
+ if (len == 1) {
+ addr ^= 3;
+ } else if (len == 2) {
+ addr ^= 2;
+ }
+ }
+
+ return addr;
+}
+
void arm_debug_excp_handler(CPUState *cs)
{
/* Called by core code when a watchpoint or breakpoint fires;
--
1.9.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* Re: [Qemu-devel] [PATCH 1/5] ARM BE8/BE32 semihosting and gdbstub support.
2016-12-06 15:11 ` Julian Brown
@ 2016-12-06 15:44 ` Peter Maydell
2016-12-06 15:51 ` Julian Brown
0 siblings, 1 reply; 28+ messages in thread
From: Peter Maydell @ 2016-12-06 15:44 UTC (permalink / raw)
To: Julian Brown; +Cc: QEMU Developers, Paolo Bonzini
On 6 December 2016 at 15:11, Julian Brown <julian@codesourcery.com> wrote:
> On Thu, 3 Nov 2016 22:23:09 +0000
> Peter Maydell <peter.maydell@linaro.org> wrote:
>
>> Strong 'no' for the approach of having different CPU
>> names, I'm afraid. What you want is to have a CPU
>> property which works like the hardware CPU's CFGEND
>> signal to set the reset value of the SCTLR.EE bit. Then
>> a board can use that where it would wire up CFGEND
>> in real hardware, and on the command line you can
>> have -cpu whatever,cfgend=yes (which is a bit ugly
>> but then it's borderline whether it makes any sense at
>> all for the user to be able to set the endianness on
>> the commandline).
>
> How about something like this?
Could you send that as an inline patch rather than
an attachment? Patches hidden in attachments are kind
of painful to deal with.
thanks
-- PMM
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [Qemu-devel] [PATCH 1/5] ARM BE8/BE32 semihosting and gdbstub support.
2016-12-06 15:44 ` Peter Maydell
@ 2016-12-06 15:51 ` Julian Brown
2016-12-06 16:14 ` Peter Maydell
0 siblings, 1 reply; 28+ messages in thread
From: Julian Brown @ 2016-12-06 15:51 UTC (permalink / raw)
To: Peter Maydell; +Cc: QEMU Developers, Paolo Bonzini
On Tue, 6 Dec 2016 15:44:07 +0000
Peter Maydell <peter.maydell@linaro.org> wrote:
> On 6 December 2016 at 15:11, Julian Brown <julian@codesourcery.com>
> wrote:
> > On Thu, 3 Nov 2016 22:23:09 +0000
> > Peter Maydell <peter.maydell@linaro.org> wrote:
> >
> >> Strong 'no' for the approach of having different CPU
> >> names, I'm afraid. What you want is to have a CPU
> >> property which works like the hardware CPU's CFGEND
> >> signal to set the reset value of the SCTLR.EE bit. Then
> >> a board can use that where it would wire up CFGEND
> >> in real hardware, and on the command line you can
> >> have -cpu whatever,cfgend=yes (which is a bit ugly
> >> but then it's borderline whether it makes any sense at
> >> all for the user to be able to set the endianness on
> >> the commandline).
> >
> > How about something like this?
>
> Could you send that as an inline patch rather than
> an attachment? Patches hidden in attachments are kind
> of painful to deal with.
Does this work? Sorry, sending replies direct from git is the level
past the one I've got to so far :-).
Thanks,
Julian
From d76129fb9ab60df696af6bc4911041f95b3a560b Mon Sep 17 00:00:00 2001
From: Julian Brown <julian@codesourcery.com>
Date: Tue, 1 Nov 2016 08:35:48 -0700
Subject: [PATCH 1/4] ARM BE8/BE32 semihosting and gdbstub support.
This patch improves support for semihosting and debugging with the
in-built gdbstub for ARM system-mode emulation in big-endian mode (either
BE8 or BE32), after the fairly recent changes to allow a single QEMU
binary to deal with each of LE, BE8 and BE32 modes in one. It's only
currently good for little-endian host systems. The relevant use case
is using QEMU as a "bare metal" instruction-set simulator, e.g. for
toolchain testing.
For semihosting, the softmmu-semi.h file is overridden with an
ARM-specific version that knows about byte-swapping target memory into
host order -- including that which has been byte-swapped at load time
for BE32 mode.
For the gdbstub, we'd like to be able to invoke QEMU from GDB like:
(gdb) target remote | arm-qemu-system -cpu=foo [options] /dev/null
(gdb) load
(gdb) ...
which unfortunately bypasses the probing of the loaded ELF file (since
it's just /dev/null) to determine whether to use BE8/BE32 mode. A
"cfgend" boolean parameter has been added for this scenario, mirroring
the configuration input on (some?) ARM cores, to choose a core-appropriate
big-endian mode at reset. (Use e.g. -cpu=arm926,cfgend=yes).
Signed-off-by: Julian Brown <julian@codesourcery.com>
---
hw/arm/boot.c | 16 ++++-
include/exec/softmmu-arm-semi.h | 148 ++++++++++++++++++++++++++++++++++++++++
target-arm/arm-semi.c | 2 +-
target-arm/cpu.c | 52 +++++++++++++-
target-arm/cpu.h | 12 ++++
target-arm/gdbstub.c | 42 ++++++++++++
6 files changed, 267 insertions(+), 5 deletions(-)
create mode 100644 include/exec/softmmu-arm-semi.h
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index 942416d..68a6574 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -894,7 +894,21 @@ static void arm_load_kernel_notify(Notifier *notifier, void *data)
entry = info->loader_start + kernel_load_offset;
kernel_size = load_image_targphys(info->kernel_filename, entry,
info->ram_size - kernel_load_offset);
- is_linux = 1;
+ if (kernel_size > 0) {
+ is_linux = 1;
+ } else {
+ /* We've been launched with a kernel of /dev/null or similar.
+ * Infer endianness from the reset value of the SCTLR for this
+ * CPU/board. (This can be altered using the cfgend parameter.)
+ */
+ if (!arm_feature(&cpu->env, ARM_FEATURE_V7) &&
+ (cpu->reset_sctlr & SCTLR_B) != 0)
+ info->endianness = ARM_ENDIANNESS_BE32;
+ else if ((cpu->reset_sctlr & SCTLR_EE) != 0)
+ info->endianness = ARM_ENDIANNESS_BE8;
+ else
+ info->endianness = ARM_ENDIANNESS_LE;
+ }
}
if (kernel_size < 0) {
fprintf(stderr, "qemu: could not load kernel '%s'\n",
diff --git a/include/exec/softmmu-arm-semi.h b/include/exec/softmmu-arm-semi.h
new file mode 100644
index 0000000..d97e017
--- /dev/null
+++ b/include/exec/softmmu-arm-semi.h
@@ -0,0 +1,148 @@
+/*
+ * Helper routines to provide target memory access for ARM semihosting
+ * syscalls in system emulation mode.
+ *
+ * Copyright (c) 2007 CodeSourcery, (c) 2016 Mentor Graphics
+ *
+ * This code is licensed under the GPL
+ */
+
+#ifndef SOFTMMU_ARM_SEMI_H
+#define SOFTMMU_ARM_SEMI_H 1
+
+/* In BE32 system mode, the CPU-specific memory_rw_debug method will arrange to
+ * perform byteswapping on the target memory, so that it appears to the host as
+ * it appears to the emulated CPU. Memory is read verbatim in BE8 mode. (In
+ * other words, this function arranges so that BUF has the same format in both
+ * BE8 and BE32 system mode.)
+ */
+
+static inline int armsemi_memory_rw_debug(CPUState *cpu, target_ulong addr,
+ uint8_t *buf, int len, bool is_write)
+{
+ CPUClass *cc = CPU_GET_CLASS(cpu);
+
+ if (cc->memory_rw_debug) {
+ return cc->memory_rw_debug(cpu, addr, buf, len, is_write);
+ }
+ return cpu_memory_rw_debug(cpu, addr, buf, len, is_write);
+}
+
+/* In big-endian mode (either BE8 or BE32), values larger than a byte will be
+ * transferred to/from memory in big-endian format. Assuming we're on a
+ * little-endian host machine, such values will need to be byteswapped before
+ * and after the host processes them.
+ *
+ * This means that byteswapping will occur *twice* in BE32 mode for
+ * halfword/word reads/writes.
+ */
+
+static inline bool arm_bswap_needed(CPUARMState *env)
+{
+#ifdef HOST_WORDS_BIGENDIAN
+#error HOST_WORDS_BIGENDIAN is not supported for ARM semihosting at the moment.
+#else
+ return arm_sctlr_b(env) || arm_sctlr_ee(env);
+#endif
+}
+
+static inline uint64_t softmmu_tget64(CPUArchState *env, target_ulong addr)
+{
+ uint64_t val;
+
+ armsemi_memory_rw_debug(ENV_GET_CPU(env), addr, (uint8_t *)&val, 8, 0);
+ if (arm_bswap_needed(env)) {
+ return bswap64(val);
+ } else {
+ return val;
+ }
+}
+
+static inline uint32_t softmmu_tget32(CPUArchState *env, target_ulong addr)
+{
+ uint32_t val;
+
+ armsemi_memory_rw_debug(ENV_GET_CPU(env), addr, (uint8_t *)&val, 4, 0);
+ if (arm_bswap_needed(env)) {
+ return bswap32(val);
+ } else {
+ return val;
+ }
+}
+
+static inline uint32_t softmmu_tget8(CPUArchState *env, target_ulong addr)
+{
+ uint8_t val;
+ armsemi_memory_rw_debug(ENV_GET_CPU(env), addr, &val, 1, 0);
+ return val;
+}
+
+#define get_user_u64(arg, p) ({ arg = softmmu_tget64(env, p); 0; })
+#define get_user_u32(arg, p) ({ arg = softmmu_tget32(env, p) ; 0; })
+#define get_user_u8(arg, p) ({ arg = softmmu_tget8(env, p) ; 0; })
+#define get_user_ual(arg, p) get_user_u32(arg, p)
+
+static inline void softmmu_tput64(CPUArchState *env,
+ target_ulong addr, uint64_t val)
+{
+ if (arm_bswap_needed(env)) {
+ val = bswap64(val);
+ }
+ cpu_memory_rw_debug(ENV_GET_CPU(env), addr, (uint8_t *)&val, 8, 1);
+}
+
+static inline void softmmu_tput32(CPUArchState *env,
+ target_ulong addr, uint32_t val)
+{
+ if (arm_bswap_needed(env)) {
+ val = bswap32(val);
+ }
+ armsemi_memory_rw_debug(ENV_GET_CPU(env), addr, (uint8_t *)&val, 4, 1);
+}
+#define put_user_u64(arg, p) ({ softmmu_tput64(env, p, arg) ; 0; })
+#define put_user_u32(arg, p) ({ softmmu_tput32(env, p, arg) ; 0; })
+#define put_user_ual(arg, p) put_user_u32(arg, p)
+
+static void *softmmu_lock_user(CPUArchState *env,
+ target_ulong addr, target_ulong len, int copy)
+{
+ uint8_t *p;
+ /* TODO: Make this something that isn't fixed size. */
+ p = malloc(len);
+ if (p && copy) {
+ armsemi_memory_rw_debug(ENV_GET_CPU(env), addr, p, len, 0);
+ }
+ return p;
+}
+#define lock_user(type, p, len, copy) softmmu_lock_user(env, p, len, copy)
+static char *softmmu_lock_user_string(CPUArchState *env, target_ulong addr)
+{
+ char *p;
+ char *s;
+ uint8_t c;
+ /* TODO: Make this something that isn't fixed size. */
+ s = p = malloc(1024);
+ if (!s) {
+ return NULL;
+ }
+ do {
+ armsemi_memory_rw_debug(ENV_GET_CPU(env), addr, &c, 1, 0);
+ addr++;
+ *(p++) = c;
+ } while (c);
+ return s;
+}
+#define lock_user_string(p) softmmu_lock_user_string(env, p)
+static void softmmu_unlock_user(CPUArchState *env, void *p, target_ulong addr,
+ target_ulong len)
+{
+ uint8_t *pc = p;
+ if (len) {
+ armsemi_memory_rw_debug(ENV_GET_CPU(env), addr, p, len, 1);
+ }
+ free(p);
+}
+
+#define unlock_user(s, args, len) softmmu_unlock_user(env, s, args, len)
+
+#endif
diff --git a/target-arm/arm-semi.c b/target-arm/arm-semi.c
index 7cac873..a9cf5f2 100644
--- a/target-arm/arm-semi.c
+++ b/target-arm/arm-semi.c
@@ -114,7 +114,7 @@ static inline uint32_t set_swi_errno(CPUARMState *env, uint32_t code)
return code;
}
-#include "exec/softmmu-semi.h"
+#include "exec/softmmu-arm-semi.h"
#endif
static target_ulong arm_semi_syscall_len;
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 2eb4098..6afb0d9 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -33,6 +33,7 @@
#include "sysemu/sysemu.h"
#include "sysemu/kvm.h"
#include "kvm_arm.h"
+#include "exec/cpu-common.h"
static void arm_cpu_set_pc(CPUState *cs, vaddr value)
{
@@ -497,6 +498,9 @@ static Property arm_cpu_rvbar_property =
static Property arm_cpu_has_el3_property =
DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true);
+static Property arm_cpu_cfgend_property =
+ DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false);
+
/* use property name "pmu" to match other archs and virt tools */
static Property arm_cpu_has_pmu_property =
DEFINE_PROP_BOOL("pmu", ARMCPU, has_pmu, true);
@@ -559,6 +563,18 @@ static void arm_cpu_post_init(Object *obj)
}
}
+ qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property,
+ &error_abort);
+
+ qdev_prop_set_globals(DEVICE(obj));
+
+ if (object_property_get_bool(obj, "cfgend", NULL)) {
+ if (arm_feature(&cpu->env, ARM_FEATURE_V7)) {
+ cpu->reset_sctlr |= SCTLR_EE;
+ } else {
+ cpu->reset_sctlr |= SCTLR_B;
+ }
+ }
}
static void arm_cpu_finalizefn(Object *obj)
@@ -758,6 +774,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
{
ObjectClass *oc;
+ CPUClass *cc;
char *typename;
char **cpuname;
@@ -765,15 +782,20 @@ static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
return NULL;
}
- cpuname = g_strsplit(cpu_model, ",", 1);
+ cpuname = g_strsplit(cpu_model, ",", 2);
typename = g_strdup_printf("%s-" TYPE_ARM_CPU, cpuname[0]);
oc = object_class_by_name(typename);
- g_strfreev(cpuname);
- g_free(typename);
if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) ||
object_class_is_abstract(oc)) {
+ g_strfreev(cpuname);
+ g_free(typename);
return NULL;
}
+
+ cc = CPU_CLASS(oc);
+ cc->parse_features(typename, cpuname[1], &error_fatal);
+ g_strfreev(cpuname);
+
return oc;
}
@@ -1534,6 +1556,27 @@ static gchar *arm_gdb_arch_name(CPUState *cs)
return g_strdup("arm");
}
+#ifndef CONFIG_USER_ONLY
+static int arm_cpu_memory_rw_debug(CPUState *cpu, vaddr address,
+ uint8_t *buf, int len, bool is_write)
+{
+ target_ulong addr = address;
+ ARMCPU *armcpu = ARM_CPU(cpu);
+ CPUARMState *env = &armcpu->env;
+
+ if (arm_sctlr_b(env)) {
+ target_ulong i;
+ for (i = 0; i < len; i++) {
+ cpu_memory_rw_debug(cpu, (addr + i) ^ 3, &buf[i], 1, is_write);
+ }
+ } else {
+ cpu_memory_rw_debug(cpu, addr, buf, len, is_write);
+ }
+
+ return 0;
+}
+#endif
+
static void arm_cpu_class_init(ObjectClass *oc, void *data)
{
ARMCPUClass *acc = ARM_CPU_CLASS(oc);
@@ -1551,6 +1594,9 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
cc->has_work = arm_cpu_has_work;
cc->cpu_exec_interrupt = arm_cpu_exec_interrupt;
cc->dump_state = arm_cpu_dump_state;
+#if !defined(CONFIG_USER_ONLY)
+ cc->memory_rw_debug = arm_cpu_memory_rw_debug;
+#endif
cc->set_pc = arm_cpu_set_pc;
cc->gdb_read_register = arm_cpu_gdb_read_register;
cc->gdb_write_register = arm_cpu_gdb_write_register;
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index ca5c849..03f19ab 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -657,6 +657,12 @@ struct ARMCPU {
uint32_t dcz_blocksize;
uint64_t rvbar;
+ /* Whether the cfgend input is high (i.e. this CPU should reset into
+ big-endian mode). This setting isn't used directly: instead it modifies
+ the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the
+ architecture version. */
+ bool cfgend;
+
ARMELChangeHook *el_change_hook;
void *el_change_hook_opaque;
};
@@ -2108,6 +2114,12 @@ static inline bool arm_sctlr_b(CPUARMState *env)
(env->cp15.sctlr_el[1] & SCTLR_B) != 0;
}
+static inline bool arm_sctlr_ee(CPUARMState *env)
+{
+ return arm_feature(env, ARM_FEATURE_V7) &&
+ (env->cp15.sctlr_el[1] & SCTLR_EE) != 0;
+}
+
/* Return true if the processor is in big-endian mode. */
static inline bool arm_cpu_data_is_big_endian(CPUARMState *env)
{
diff --git a/target-arm/gdbstub.c b/target-arm/gdbstub.c
index 04c1208..1e9fe68 100644
--- a/target-arm/gdbstub.c
+++ b/target-arm/gdbstub.c
@@ -21,6 +21,7 @@
#include "qemu-common.h"
#include "cpu.h"
#include "exec/gdbstub.h"
+#include "exec/softmmu-arm-semi.h"
/* Old gdb always expect FPA registers. Newer (xml-aware) gdb only expect
whatever the target description contains. Due to a historical mishap
@@ -32,10 +33,22 @@ int arm_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
{
ARMCPU *cpu = ARM_CPU(cs);
CPUARMState *env = &cpu->env;
+#ifndef CONFIG_USER_ONLY
+ bool targ_bigendian = arm_bswap_needed(env);
+#endif
if (n < 16) {
/* Core integer register. */
+#ifdef CONFIG_USER_ONLY
return gdb_get_reg32(mem_buf, env->regs[n]);
+#else
+ if (targ_bigendian) {
+ stl_be_p(mem_buf, env->regs[n]);
+ } else {
+ stl_le_p(mem_buf, env->regs[n]);
+ }
+ return 4;
+#endif
}
if (n < 24) {
/* FPA registers. */
@@ -51,10 +64,28 @@ int arm_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
if (gdb_has_xml) {
return 0;
}
+#ifdef CONFIG_USER_ONLY
return gdb_get_reg32(mem_buf, 0);
+#else
+ if (targ_bigendian) {
+ stl_be_p(mem_buf, 0);
+ } else {
+ stl_le_p(mem_buf, 0);
+ }
+ return 4;
+#endif
case 25:
/* CPSR */
+#ifdef CONFIG_USER_ONLY
return gdb_get_reg32(mem_buf, cpsr_read(env));
+#else
+ if (targ_bigendian) {
+ stl_be_p(mem_buf, cpsr_read(env));
+ } else {
+ stl_le_p(mem_buf, cpsr_read(env));
+ }
+ return 4;
+#endif
}
/* Unknown register. */
return 0;
@@ -65,8 +96,19 @@ int arm_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
ARMCPU *cpu = ARM_CPU(cs);
CPUARMState *env = &cpu->env;
uint32_t tmp;
+#ifndef CONFIG_USER_ONLY
+ bool targ_bigendian = arm_bswap_needed(env);
+#endif
+#ifdef CONFIG_USER_ONLY
tmp = ldl_p(mem_buf);
+#else
+ if (targ_bigendian) {
+ tmp = ldl_be_p(mem_buf);
+ } else {
+ tmp = ldl_le_p(mem_buf);
+ }
+#endif
/* Mask out low bit of PC to workaround gdb bugs. This will probably
cause problems if we ever implement the Jazelle DBX extensions. */
--
1.9.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* Re: [Qemu-devel] [PATCH 1/5] ARM BE8/BE32 semihosting and gdbstub support.
2016-12-06 15:51 ` Julian Brown
@ 2016-12-06 16:14 ` Peter Maydell
0 siblings, 0 replies; 28+ messages in thread
From: Peter Maydell @ 2016-12-06 16:14 UTC (permalink / raw)
To: Julian Brown; +Cc: QEMU Developers, Paolo Bonzini
On 6 December 2016 at 15:51, Julian Brown <julian@codesourcery.com> wrote:
> On Tue, 6 Dec 2016 15:44:07 +0000
> Peter Maydell <peter.maydell@linaro.org> wrote:
>
>> On 6 December 2016 at 15:11, Julian Brown <julian@codesourcery.com>
>> wrote:
>> > On Thu, 3 Nov 2016 22:23:09 +0000
>> > Peter Maydell <peter.maydell@linaro.org> wrote:
>> >
>> >> Strong 'no' for the approach of having different CPU
>> >> names, I'm afraid. What you want is to have a CPU
>> >> property which works like the hardware CPU's CFGEND
>> >> signal to set the reset value of the SCTLR.EE bit. Then
>> >> a board can use that where it would wire up CFGEND
>> >> in real hardware, and on the command line you can
>> >> have -cpu whatever,cfgend=yes (which is a bit ugly
>> >> but then it's borderline whether it makes any sense at
>> >> all for the user to be able to set the endianness on
>> >> the commandline).
>> >
>> > How about something like this?
>>
>> Could you send that as an inline patch rather than
>> an attachment? Patches hidden in attachments are kind
>> of painful to deal with.
>
> Does this work? Sorry, sending replies direct from git is the level
> past the one I've got to so far :-).
Yes, this works; it's probably easiest to just send a v2
of the patchset, though, since I notice you sent followups
with patches to most of the original patch emails.
This patch looks like it's trying to do too many
things at once; "add property which allows config of the
SCTLR.EE reset value" should definitely be its own patch,
and there may be other useful things that could be split
out of it.
thanks
-- PMM
^ permalink raw reply [flat|nested] 28+ messages in thread
end of thread, other threads:[~2016-12-06 16:16 UTC | newest]
Thread overview: 28+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2016-11-03 17:30 [Qemu-devel] [PATCH 0/5] ARM BE8/BE32 big-endian system-mode fixes (semihosting, gdbstub) Julian Brown
2016-11-03 17:30 ` [Qemu-devel] [PATCH 1/5] ARM BE8/BE32 semihosting and gdbstub support Julian Brown
2016-11-03 22:23 ` Peter Maydell
2016-11-03 23:34 ` Julian Brown
2016-11-04 8:48 ` Paolo Bonzini
2016-11-04 10:25 ` Julian Brown
2016-11-04 11:01 ` Paolo Bonzini
2016-11-04 9:03 ` Paolo Bonzini
2016-12-06 15:11 ` Julian Brown
2016-12-06 15:44 ` Peter Maydell
2016-12-06 15:51 ` Julian Brown
2016-12-06 16:14 ` Peter Maydell
2016-11-03 17:30 ` [Qemu-devel] [PATCH 2/5] Fix Thumb-1 BE32 execution and disassembly Julian Brown
2016-11-04 13:30 ` Peter Maydell
2016-11-04 14:04 ` Julian Brown
2016-12-06 15:12 ` Julian Brown
2016-11-03 17:30 ` [Qemu-devel] [PATCH 3/5] Fix arm_semi_flen_cb for BE32 system mode Julian Brown
2016-11-04 9:00 ` Paolo Bonzini
2016-12-06 15:11 ` Julian Brown
2016-11-03 17:30 ` [Qemu-devel] [PATCH 4/5] ARM BE32 watchpoint fix Julian Brown
2016-11-03 23:14 ` Peter Maydell
2016-11-03 23:20 ` Julian Brown
2016-11-04 8:55 ` Paolo Bonzini
2016-12-06 15:12 ` Julian Brown
2016-11-03 21:26 ` [Qemu-devel] [PATCH 5/5] Fix typo in arm_cpu_do_interrupt_aarch32 Julian Brown
2016-11-04 13:02 ` Peter Maydell
2016-11-03 21:29 ` [Qemu-devel] [PATCH 0/5] ARM BE8/BE32 big-endian system-mode fixes (semihosting, gdbstub) no-reply
2016-11-03 21:37 ` no-reply
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