From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45631) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c3R2k-0006kt-Lh for qemu-devel@nongnu.org; Sun, 06 Nov 2016 12:15:43 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1c3R2h-0001jl-Ha for qemu-devel@nongnu.org; Sun, 06 Nov 2016 12:15:42 -0500 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:59978) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1c3R2h-0001hy-9e for qemu-devel@nongnu.org; Sun, 06 Nov 2016 12:15:39 -0500 Received: from pps.filterd (m0098393.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.17/8.16.0.17) with SMTP id uA6HDcPw114807 for ; Sun, 6 Nov 2016 12:15:37 -0500 Received: from e24smtp05.br.ibm.com (e24smtp05.br.ibm.com [32.104.18.26]) by mx0a-001b2d01.pphosted.com with ESMTP id 26j6v342pm-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Sun, 06 Nov 2016 12:15:36 -0500 Received: from localhost by e24smtp05.br.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Sun, 6 Nov 2016 15:15:34 -0200 Received: from d24relay02.br.ibm.com (d24relay02.br.ibm.com [9.13.184.26]) by d24dlp02.br.ibm.com (Postfix) with ESMTP id 7C3A91DC0054 for ; Sun, 6 Nov 2016 12:15:32 -0500 (EST) Received: from d24av05.br.ibm.com (d24av05.br.ibm.com [9.18.232.44]) by d24relay02.br.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id uA6HFWUi24969664 for ; Sun, 6 Nov 2016 15:15:32 -0200 Received: from d24av05.br.ibm.com (localhost [127.0.0.1]) by d24av05.br.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id uA6HFWmT002937 for ; Sun, 6 Nov 2016 15:15:32 -0200 From: Jose Ricardo Ziviani Date: Sun, 6 Nov 2016 15:15:19 -0200 Message-Id: <1478452528-13684-1-git-send-email-joserz@linux.vnet.ibm.com> Subject: [Qemu-devel] [PATCH Risu v2 0/9] Risu support for PPC64LE List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org v2: - smaller commits - improved registers comparison - improved code style - fixed copyright lines TODOs: - improve load/store instruction generation (risugen) - improve initial random values for FP and Vector regs (risugen) - make write_test_code() generic (risugen) This is an initial effort to have RISU working for PPC64LE. I also made some changes to isolate risugen, creating two modules (risugen_arm.pm and risugen_ppc64le.pm) to implement specific instructions in it. Suggestions are welcome! :) Jose Ricardo Ziviani (9): Create risugen_arm.pm module for risugen Refactor risugen to remove ARM specific code Change mode directive of ARM risu files Implement lib to deal with PPC64 registers Implement basic test code for PPC64 Implement initial support for PPC64 Add PPC64 in risu build system Implement risugen module for PPC64 Implement risufile with all PPC64 instructions aarch64.risu | 2 +- arm.risu | 1 + configure | 8 +- ppc64.risu | 3448 ++++++++++++++++++++++++++++++++++++++++++++++++ risu_ppc64le.c | 158 +++ risu_reginfo_ppc64le.c | 200 +++ risu_reginfo_ppc64le.h | 40 + risugen | 1035 +-------------- risugen_arm.pm | 1086 +++++++++++++++ risugen_ppc64.pm | 460 +++++++ test_ppc64le.s | 51 + thumb.risu | 2 +- 12 files changed, 5478 insertions(+), 1013 deletions(-) create mode 100644 ppc64.risu create mode 100644 risu_ppc64le.c create mode 100644 risu_reginfo_ppc64le.c create mode 100644 risu_reginfo_ppc64le.h create mode 100644 risugen_arm.pm create mode 100644 risugen_ppc64.pm create mode 100644 test_ppc64le.s -- 2.7.4