From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45735) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c3R30-0006uN-J0 for qemu-devel@nongnu.org; Sun, 06 Nov 2016 12:16:01 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1c3R2x-0001xs-F0 for qemu-devel@nongnu.org; Sun, 06 Nov 2016 12:15:58 -0500 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:44773) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1c3R2w-0001wo-SN for qemu-devel@nongnu.org; Sun, 06 Nov 2016 12:15:55 -0500 Received: from pps.filterd (m0098409.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.17/8.16.0.17) with SMTP id uA6HDeW3052517 for ; Sun, 6 Nov 2016 12:15:54 -0500 Received: from e24smtp05.br.ibm.com (e24smtp05.br.ibm.com [32.104.18.26]) by mx0a-001b2d01.pphosted.com with ESMTP id 26haqwantv-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Sun, 06 Nov 2016 12:15:53 -0500 Received: from localhost by e24smtp05.br.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Sun, 6 Nov 2016 15:15:51 -0200 Received: from d24relay03.br.ibm.com (d24relay03.br.ibm.com [9.18.232.225]) by d24dlp01.br.ibm.com (Postfix) with ESMTP id 4D953352005C for ; Sun, 6 Nov 2016 12:15:20 -0500 (EST) Received: from d24av05.br.ibm.com (d24av05.br.ibm.com [9.18.232.44]) by d24relay03.br.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id uA6HFmZD33816578 for ; Sun, 6 Nov 2016 15:15:48 -0200 Received: from d24av05.br.ibm.com (localhost [127.0.0.1]) by d24av05.br.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id uA6HFlgf003157 for ; Sun, 6 Nov 2016 15:15:47 -0200 From: Jose Ricardo Ziviani Date: Sun, 6 Nov 2016 15:15:26 -0200 In-Reply-To: <1478452528-13684-1-git-send-email-joserz@linux.vnet.ibm.com> References: <1478452528-13684-1-git-send-email-joserz@linux.vnet.ibm.com> Message-Id: <1478452528-13684-8-git-send-email-joserz@linux.vnet.ibm.com> Subject: [Qemu-devel] [PATCH Risu v2 7/9] Add PPC64 in risu build system List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org Recognizes PPC64 as a valid architecture and setup the environment variables to compile code for that. Signed-off-by: Jose Ricardo Ziviani --- configure | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/configure b/configure index 748b48a..f81bdb5 100755 --- a/configure +++ b/configure @@ -22,6 +22,12 @@ guess_arch() { ARCH="arm" elif check_define __aarch64__ ; then ARCH="aarch64" + elif check_define __powerpc64__ ; then + if check_define __BIG_ENDIAN__; then + ARCH="ppc64" + else + ARCH="ppc64le" + fi else echo "This cpu is not supported by risu. Try -h. " >&2 exit 1 @@ -57,7 +63,7 @@ Some influential environment variables: prefixed with the given string. ARCH force target architecture instead of trying to detect it. - Valid values=[arm|aarch64] + Valid values=[arm|aarch64|ppc64|ppc64le] CC C compiler command CFLAGS C compiler flags -- 2.7.4