From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35073) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c3hSt-0007Fu-PS for qemu-devel@nongnu.org; Mon, 07 Nov 2016 05:47:48 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1c3hSr-0004kU-Rk for qemu-devel@nongnu.org; Mon, 07 Nov 2016 05:47:47 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:47500) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1c3hSr-0004hx-LH for qemu-devel@nongnu.org; Mon, 07 Nov 2016 05:47:45 -0500 From: Peter Maydell Date: Mon, 7 Nov 2016 10:47:30 +0000 Message-Id: <1478515653-6361-2-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1478515653-6361-1-git-send-email-peter.maydell@linaro.org> References: <1478515653-6361-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PULL 1/4] char: cadence: check baud rate generator and divider values List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Stefan Hajnoczi From: Prasad J Pandit The Cadence UART device emulator calculates speed by dividing the baud rate by a 'baud rate generator' & 'baud rate divider' value. The device specification defines these register values to be non-zero and within certain limits. Add checks for these limits to avoid errors like divide by zero. Reported-by: Huawei PSIRT Signed-off-by: Prasad J Pandit Reviewed-by: Alistair Francis Message-id: 1477596278-1470-1-git-send-email-ppandit@redhat.com Signed-off-by: Peter Maydell --- hw/char/cadence_uart.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c index def34cd..0215d65 100644 --- a/hw/char/cadence_uart.c +++ b/hw/char/cadence_uart.c @@ -1,6 +1,11 @@ /* * Device model for Cadence UART * + * Reference: Xilinx Zynq 7000 reference manual + * - http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf + * - Chapter 19 UART Controller + * - Appendix B for Register details + * * Copyright (c) 2010 Xilinx Inc. * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.crosthwaite@petalogix.com) * Copyright (c) 2012 PetaLogix Pty Ltd. @@ -402,6 +407,16 @@ static void uart_write(void *opaque, hwaddr offset, break; } break; + case R_BRGR: /* Baud rate generator */ + if (value >= 0x01) { + s->r[offset] = value & 0xFFFF; + } + break; + case R_BDIV: /* Baud rate divider */ + if (value >= 0x04) { + s->r[offset] = value & 0xFF; + } + break; default: s->r[offset] = value; } -- 2.7.4