From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50807) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c6B68-00066O-5A for qemu-devel@nongnu.org; Mon, 14 Nov 2016 01:50:33 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1c6B65-0003Oi-4H for qemu-devel@nongnu.org; Mon, 14 Nov 2016 01:50:32 -0500 Received: from 8.mo4.mail-out.ovh.net ([188.165.33.112]:46635) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1c6B64-0003OT-UW for qemu-devel@nongnu.org; Mon, 14 Nov 2016 01:50:29 -0500 Received: from player750.ha.ovh.net (b7.ovh.net [213.186.33.57]) by mo4.mail-out.ovh.net (Postfix) with ESMTP id 9DF321BDF8 for ; Mon, 14 Nov 2016 07:50:27 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Mon, 14 Nov 2016 07:50:10 +0100 Message-Id: <1479106212-18971-2-git-send-email-clg@kaod.org> In-Reply-To: <1479106212-18971-1-git-send-email-clg@kaod.org> References: <1479106212-18971-1-git-send-email-clg@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH 1/3] ppc/pnv: add a 'xscom_core_base' field to PnvChipClass List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-ppc@nongnu.org Cc: David Gibson , qemu-devel@nongnu.org, Alexander Graf , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= The XSCOM addresses for the core registers are encoded in a slightly different way on POWER8 and POWER9. Signed-off-by: C=C3=A9dric Le Goater --- hw/ppc/pnv.c | 8 +++++++- include/hw/ppc/pnv.h | 1 + include/hw/ppc/pnv_xscom.h | 5 ++--- 3 files changed, 10 insertions(+), 4 deletions(-) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 6af34241f248..e7779581545d 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -521,6 +521,7 @@ static void pnv_chip_power8e_class_init(ObjectClass *= klass, void *data) k->cores_mask =3D POWER8E_CORE_MASK; k->core_pir =3D pnv_chip_core_pir_p8; k->xscom_base =3D 0x003fc0000000000ull; + k->xscom_core_base =3D 0x10000000ull; dc->desc =3D "PowerNV Chip POWER8E"; } =20 @@ -542,6 +543,7 @@ static void pnv_chip_power8_class_init(ObjectClass *k= lass, void *data) k->cores_mask =3D POWER8_CORE_MASK; k->core_pir =3D pnv_chip_core_pir_p8; k->xscom_base =3D 0x003fc0000000000ull; + k->xscom_core_base =3D 0x10000000ull; dc->desc =3D "PowerNV Chip POWER8"; } =20 @@ -563,6 +565,7 @@ static void pnv_chip_power8nvl_class_init(ObjectClass= *klass, void *data) k->cores_mask =3D POWER8_CORE_MASK; k->core_pir =3D pnv_chip_core_pir_p8; k->xscom_base =3D 0x003fc0000000000ull; + k->xscom_core_base =3D 0x10000000ull; dc->desc =3D "PowerNV Chip POWER8NVL"; } =20 @@ -584,6 +587,7 @@ static void pnv_chip_power9_class_init(ObjectClass *k= lass, void *data) k->cores_mask =3D POWER9_CORE_MASK; k->core_pir =3D pnv_chip_core_pir_p9; k->xscom_base =3D 0x00603fc00000000ull; + k->xscom_core_base =3D 0x0ull; dc->desc =3D "PowerNV Chip POWER9"; } =20 @@ -691,7 +695,9 @@ static void pnv_chip_realize(DeviceState *dev, Error = **errp) object_unref(OBJECT(pnv_core)); =20 /* Each core has an XSCOM MMIO region */ - pnv_xscom_add_subregion(chip, PNV_XSCOM_EX_CORE_BASE(core_hwid), + pnv_xscom_add_subregion(chip, + PNV_XSCOM_EX_CORE_BASE(pcc->xscom_core_b= ase, + core_hwid), &PNV_CORE(pnv_core)->xscom_regs); i++; } diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index 7bee658733db..df98a72006e4 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -69,6 +69,7 @@ typedef struct PnvChipClass { uint64_t cores_mask; =20 hwaddr xscom_base; + hwaddr xscom_core_base; =20 uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id); } PnvChipClass; diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h index 41a5127a1907..0faa1847bf13 100644 --- a/include/hw/ppc/pnv_xscom.h +++ b/include/hw/ppc/pnv_xscom.h @@ -40,7 +40,7 @@ typedef struct PnvXScomInterfaceClass { } PnvXScomInterfaceClass; =20 /* - * Layout of the XSCOM PCB addresses of EX core 1 + * Layout of the XSCOM PCB addresses of EX core 1 (POWER 8) * * GPIO 0x1100xxxx * SCOM 0x1101xxxx @@ -54,8 +54,7 @@ typedef struct PnvXScomInterfaceClass { * PCB SLAVE 0x110Fxxxx */ =20 -#define PNV_XSCOM_EX_BASE 0x10000000 -#define PNV_XSCOM_EX_CORE_BASE(i) (PNV_XSCOM_EX_BASE | (((uint64_t)i) <<= 24)) +#define PNV_XSCOM_EX_CORE_BASE(base, i) (base | (((uint64_t)i) << 24)) #define PNV_XSCOM_EX_CORE_SIZE 0x100000 =20 #define PNV_XSCOM_LPC_BASE 0xb0020 --=20 2.7.4