From: David Gibson <david@gibson.dropbear.id.au>
To: peter.maydell@linaro.org
Cc: agraf@suse.de, aik@ozlabs.ru, mdroth@linux.vnet.ibm.com,
clg@kaod.org, qemu-ppc@nongnu.org, qemu-devel@nongnu.org,
Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>,
David Gibson <david@gibson.dropbear.id.au>
Subject: [Qemu-devel] [PULL 01/19] bitops: fix rol/ror when shift is zero
Date: Tue, 15 Nov 2016 13:48:46 +1100 [thread overview]
Message-ID: <1479178144-28153-2-git-send-email-david@gibson.dropbear.id.au> (raw)
In-Reply-To: <1479178144-28153-1-git-send-email-david@gibson.dropbear.id.au>
From: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
All the variants for rol/ror have a bug in case where the shift == 0.
For example rol32, would generate:
return (word << 0) | (word >> 32);
Which though works, would be flagged as a runtime error on clang's
sanitizer.
Suggested-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
include/qemu/bitops.h | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/include/qemu/bitops.h b/include/qemu/bitops.h
index 98fb005..1881284 100644
--- a/include/qemu/bitops.h
+++ b/include/qemu/bitops.h
@@ -218,7 +218,7 @@ static inline unsigned long hweight_long(unsigned long w)
*/
static inline uint8_t rol8(uint8_t word, unsigned int shift)
{
- return (word << shift) | (word >> (8 - shift));
+ return (word << shift) | (word >> ((8 - shift) & 7));
}
/**
@@ -228,7 +228,7 @@ static inline uint8_t rol8(uint8_t word, unsigned int shift)
*/
static inline uint8_t ror8(uint8_t word, unsigned int shift)
{
- return (word >> shift) | (word << (8 - shift));
+ return (word >> shift) | (word << ((8 - shift) & 7));
}
/**
@@ -238,7 +238,7 @@ static inline uint8_t ror8(uint8_t word, unsigned int shift)
*/
static inline uint16_t rol16(uint16_t word, unsigned int shift)
{
- return (word << shift) | (word >> (16 - shift));
+ return (word << shift) | (word >> ((16 - shift) & 15));
}
/**
@@ -248,7 +248,7 @@ static inline uint16_t rol16(uint16_t word, unsigned int shift)
*/
static inline uint16_t ror16(uint16_t word, unsigned int shift)
{
- return (word >> shift) | (word << (16 - shift));
+ return (word >> shift) | (word << ((16 - shift) & 15));
}
/**
@@ -258,7 +258,7 @@ static inline uint16_t ror16(uint16_t word, unsigned int shift)
*/
static inline uint32_t rol32(uint32_t word, unsigned int shift)
{
- return (word << shift) | (word >> (32 - shift));
+ return (word << shift) | (word >> ((32 - shift) & 31));
}
/**
@@ -268,7 +268,7 @@ static inline uint32_t rol32(uint32_t word, unsigned int shift)
*/
static inline uint32_t ror32(uint32_t word, unsigned int shift)
{
- return (word >> shift) | (word << (32 - shift));
+ return (word >> shift) | (word << ((32 - shift) & 31));
}
/**
@@ -278,7 +278,7 @@ static inline uint32_t ror32(uint32_t word, unsigned int shift)
*/
static inline uint64_t rol64(uint64_t word, unsigned int shift)
{
- return (word << shift) | (word >> (64 - shift));
+ return (word << shift) | (word >> ((64 - shift) & 63));
}
/**
@@ -288,7 +288,7 @@ static inline uint64_t rol64(uint64_t word, unsigned int shift)
*/
static inline uint64_t ror64(uint64_t word, unsigned int shift)
{
- return (word >> shift) | (word << (64 - shift));
+ return (word >> shift) | (word << ((64 - shift) & 63));
}
/**
--
2.7.4
next prev parent reply other threads:[~2016-11-15 2:49 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-11-15 2:48 [Qemu-devel] [PULL 00/19] ppc-for-2.8 queue 20161115 David Gibson
2016-11-15 2:48 ` David Gibson [this message]
2016-11-15 2:48 ` [Qemu-devel] [PULL 02/19] target-ppc: add vrldnmi and vrlwmi instructions David Gibson
2016-11-15 2:48 ` [Qemu-devel] [PULL 03/19] target-ppc: add vrldnm and vrlwnm instructions David Gibson
2016-11-15 2:48 ` [Qemu-devel] [PULL 04/19] target-ppc: add vprtyb[w/d/q] instructions David Gibson
2016-11-15 2:48 ` [Qemu-devel] [PULL 05/19] powernv: CPU compatibility modes don't make sense for powernv David Gibson
2016-11-15 2:48 ` [Qemu-devel] [PULL 06/19] ppc/pnv: fix compile breakage on old gcc David Gibson
2016-11-15 2:48 ` [Qemu-devel] [PULL 07/19] ppc: Remove some stub POWER6 models David Gibson
2016-11-15 2:48 ` [Qemu-devel] [PULL 08/19] target-ppc: Implement bcdcfn. instruction David Gibson
2016-11-15 2:48 ` [Qemu-devel] [PULL 09/19] target-ppc: Implement bcdctn. instruction David Gibson
2016-11-15 2:48 ` [Qemu-devel] [PULL 10/19] target-ppc: Implement bcdcfz. instruction David Gibson
2016-11-15 2:48 ` [Qemu-devel] [PULL 11/19] target-ppc: Implement bcdctz. instruction David Gibson
2016-11-15 2:48 ` [Qemu-devel] [PULL 12/19] spapr: Fix migration of PCI host bridges from qemu-2.7 David Gibson
2016-11-15 2:48 ` [Qemu-devel] [PULL 13/19] FU exceptions should carry a cause (IC) David Gibson
2016-11-15 2:48 ` [Qemu-devel] [PULL 14/19] spapr-vty: Fix bad assert() statement David Gibson
2016-11-15 2:49 ` [Qemu-devel] [PULL 15/19] ppc/pnv: add a 'xscom_core_base' field to PnvChipClass David Gibson
2016-11-15 2:49 ` [Qemu-devel] [PULL 16/19] ppc/pnv: fix xscom address translation for POWER9 David Gibson
2016-11-15 2:49 ` [Qemu-devel] [PULL 17/19] ppc/pnv: Fix fatal bug on 32-bit hosts David Gibson
2016-11-15 2:49 ` [Qemu-devel] [PULL 18/19] tests: add XSCOM tests for the PowerNV machine David Gibson
2016-11-15 2:49 ` [Qemu-devel] [PULL 19/19] boot-serial-test: Add a test for the powernv machine David Gibson
2016-11-15 11:18 ` [Qemu-devel] [PULL 00/19] ppc-for-2.8 queue 20161115 Stefan Hajnoczi
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