From: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com>
To: qemu-ppc@nongnu.org
Cc: qemu-devel@nongnu.org, david@gibson.dropbear.id.au,
nikunj@linux.vnet.ibm.com, bharata@linux.vnet.ibm.com
Subject: [Qemu-devel] [PATCH 4/4] target-ppc: Implement bcdsetsgn. instruction
Date: Wed, 16 Nov 2016 18:07:30 -0200 [thread overview]
Message-ID: <1479326850-8369-5-git-send-email-joserz@linux.vnet.ibm.com> (raw)
In-Reply-To: <1479326850-8369-1-git-send-email-joserz@linux.vnet.ibm.com>
bcdsetsgn.: Decimal set sign. This instruction copies the register
value to the result register but adjust the signal according to
the preferred sign value.
Signed-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com>
---
target-ppc/helper.h | 1 +
target-ppc/int_helper.c | 9 +++++++++
target-ppc/translate/vmx-impl.inc.c | 8 ++++++++
3 files changed, 18 insertions(+)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index dada48e..cddac8e 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -385,6 +385,7 @@ DEF_HELPER_3(bcdctz, i32, avr, avr, i32)
DEF_HELPER_3(bcdcfsq, i32, avr, avr, i32)
DEF_HELPER_3(bcdctsq, i32, avr, avr, i32)
DEF_HELPER_4(bcdcpsgn, i32, avr, avr, avr, i32)
+DEF_HELPER_3(bcdsetsgn, i32, avr, avr, i32)
DEF_HELPER_2(xsadddp, void, env, i32)
DEF_HELPER_2(xssubdp, void, env, i32)
diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
index a215bfe..38af503 100644
--- a/target-ppc/int_helper.c
+++ b/target-ppc/int_helper.c
@@ -2991,6 +2991,15 @@ uint32_t helper_bcdcpsgn(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t ps)
return cr;
}
+uint32_t helper_bcdsetsgn(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps)
+{
+ int sgnb = bcd_get_sgn(b);
+ ppc_avr_t ret = { .u64 = { 0, 0 } };
+
+ bcd_put_digit(&ret, bcd_preferred_sgn(sgnb, ps), 0);
+ return helper_bcdcpsgn(r, b, &ret, ps);
+}
+
void helper_vsbox(ppc_avr_t *r, ppc_avr_t *a)
{
int i;
diff --git a/target-ppc/translate/vmx-impl.inc.c b/target-ppc/translate/vmx-impl.inc.c
index c14b666..b188e60 100644
--- a/target-ppc/translate/vmx-impl.inc.c
+++ b/target-ppc/translate/vmx-impl.inc.c
@@ -991,6 +991,7 @@ GEN_BCD2(bcdcfz)
GEN_BCD2(bcdctz)
GEN_BCD2(bcdcfsq)
GEN_BCD2(bcdctsq)
+GEN_BCD2(bcdsetsgn)
GEN_BCD(bcdcpsgn);
static void gen_xpnd04_1(DisasContext *ctx)
@@ -1014,6 +1015,9 @@ static void gen_xpnd04_1(DisasContext *ctx)
case 7:
gen_bcdcfn(ctx);
break;
+ case 31:
+ gen_bcdsetsgn(ctx);
+ break;
default:
gen_invalid(ctx);
break;
@@ -1038,12 +1042,16 @@ static void gen_xpnd04_2(DisasContext *ctx)
case 7:
gen_bcdcfn(ctx);
break;
+ case 31:
+ gen_bcdsetsgn(ctx);
+ break;
default:
gen_invalid(ctx);
break;
}
}
+
GEN_VXFORM_DUAL(vsubcuw, PPC_ALTIVEC, PPC_NONE, \
xpnd04_1, PPC_NONE, PPC2_ISA300)
GEN_VXFORM_DUAL(vsubsws, PPC_ALTIVEC, PPC_NONE, \
--
2.7.4
next prev parent reply other threads:[~2016-11-16 20:08 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-11-16 20:07 [Qemu-devel] [PATCH 0/4] POWER9 TCG enablements - BCD functions part II Jose Ricardo Ziviani
2016-11-16 20:07 ` [Qemu-devel] [PATCH 1/4] target-ppc: Implement bcdcfsq. instruction Jose Ricardo Ziviani
2016-11-17 3:42 ` David Gibson
2016-11-17 17:31 ` joserz
2016-11-17 23:11 ` David Gibson
2016-11-16 20:07 ` [Qemu-devel] [PATCH 2/4] target-ppc: Implement bcdctsq. instruction Jose Ricardo Ziviani
2016-11-17 4:12 ` David Gibson
2016-11-16 20:07 ` [Qemu-devel] [PATCH 3/4] target-ppc: Implement bcdcpsgn. instruction Jose Ricardo Ziviani
2016-11-17 4:16 ` David Gibson
2016-11-16 20:07 ` Jose Ricardo Ziviani [this message]
2016-11-17 4:17 ` [Qemu-devel] [PATCH 4/4] target-ppc: Implement bcdsetsgn. instruction David Gibson
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