From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42084) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c99X7-0002mC-RO for qemu-devel@nongnu.org; Tue, 22 Nov 2016 06:46:42 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1c99X4-0005SZ-O3 for qemu-devel@nongnu.org; Tue, 22 Nov 2016 06:46:41 -0500 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:50175) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1c99X4-0005RT-FA for qemu-devel@nongnu.org; Tue, 22 Nov 2016 06:46:38 -0500 Received: from pps.filterd (m0098396.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.17/8.16.0.17) with SMTP id uAMBiPVc101403 for ; Tue, 22 Nov 2016 06:46:36 -0500 Received: from e28smtp05.in.ibm.com (e28smtp05.in.ibm.com [125.16.236.5]) by mx0a-001b2d01.pphosted.com with ESMTP id 26vn30samu-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Tue, 22 Nov 2016 06:46:36 -0500 Received: from localhost by e28smtp05.in.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Tue, 22 Nov 2016 17:16:32 +0530 From: Nikunj A Dadhania Date: Tue, 22 Nov 2016 17:15:56 +0530 Message-Id: <1479815165-31059-1-git-send-email-nikunj@linux.vnet.ibm.com> Subject: [Qemu-devel] [PATCH ppc-for-2.9 0/9] POWER9 TCG enablements - part8 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, rth@twiddle.net Cc: qemu-devel@nongnu.org, nikunj@linux.vnet.ibm.com, bharata@linux.vnet.ibm.com This series contains 18 new instructions for POWER9 ISA3.0 Vector Extract Left/Right Indexed VSX Scalar Compare Exponents VSX Scalar Compare Quad-Precision Load/Store VSX Vector Load/Store VSX Scalar Patches ======= 01-02: Consolidation/Fixes 03: xscmpexpdp: VSX Scalar Compare Exponents Double-Precision xscmpexpqp: VSX Scalar Compare Exponents Quad-Precision 04: xscmpoqp: VSX Scalar Compare Ordered Quad-Precision xscmpuqp: VSX Scalar Compare Unordered Quad-Precision 05: lxsd: Load VSX Scalar Dword lxssp: Load VSX Scalar Single Precision 06: stxsd: Store VSX Scalar Dword stxssp: Store VSX Scalar Single Precision 07: lxv: Load VSX Vector lxvx: Load VSX Vector Indexed stxv: Store VSX Vector stxvx: Store VSX Vector Indexed 08: vextublx: Vector Extract Unsigned Byte Left vextuhlx: Vector Extract Unsigned Halfword Left vextuwlx: Vector Extract Unsigned Word Left 09: vextubrx: Vector Extract Unsigned Byte Right-Indexed vextuhrx: Vector Extract Unsigned Halfword Right-Indexed vextuwrx: Vector Extract Unsigned Word Right-Indexed Avinesh Kumar (1): target-ppc: add vextu[bhw]lx instructions Bharata B Rao (4): target-ppc: Consolidate instruction decode helpers target-ppc: Fix xscmpodp and xscmpudp instructions target-ppc: Add xscmpexp[dp,qp] instructions target-ppc: Add xscmpoqp and xscmpuqp instructions Hariharan T.S (1): target-ppc: add vextu[bhw]rx instructions Nikunj A Dadhania (3): target-ppc: implement lxsd and lxssp instructions target-ppc: implement stxsd and stxssp target-ppc: implement lxv/lxvx and stxv/stxvx target-ppc/fpu_helper.c | 168 +++++++++++++++++++++++----- target-ppc/helper.h | 10 ++ target-ppc/int_helper.c | 123 +++++++++++++++++++++ target-ppc/internal.h | 152 ++++++++++++++++++++++++++ target-ppc/translate.c | 211 ++++++++++-------------------------- target-ppc/translate/fp-ops.inc.c | 2 - target-ppc/translate/vmx-impl.inc.c | 23 ++++ target-ppc/translate/vmx-ops.inc.c | 8 +- target-ppc/translate/vsx-impl.inc.c | 96 ++++++++++++++++ target-ppc/translate/vsx-ops.inc.c | 10 ++ 10 files changed, 622 insertions(+), 181 deletions(-) -- 2.7.4