From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54873) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c9NdH-0005VT-LN for qemu-devel@nongnu.org; Tue, 22 Nov 2016 21:50:01 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1c9NdE-0001tr-HY for qemu-devel@nongnu.org; Tue, 22 Nov 2016 21:49:59 -0500 From: David Gibson Date: Wed, 23 Nov 2016 13:49:35 +1100 Message-Id: <1479869383-16162-4-git-send-email-david@gibson.dropbear.id.au> In-Reply-To: <1479869383-16162-1-git-send-email-david@gibson.dropbear.id.au> References: <1479869383-16162-1-git-send-email-david@gibson.dropbear.id.au> Subject: [Qemu-devel] [PULL 03/11] ppc: BOOK3E: nothing should be done when MSR:PR is set List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: peter.maydell@linaro.org, stefanha@redhat.com Cc: agraf@suse.de, mdroth@linux.vnet.ibm.com, qemu-ppc@nongnu.org, qemu-devel@nongnu.org, Vladimir Svoboda , David Gibson From: Vladimir Svoboda The server architecture (BOOK3S) specifies that any instruction that sets MSR:PR will also set MSR:EE, IR and DR. However there is no such behavior specification for the embedded architecture (BOOK3E). Signed-off-by: Vladimir Svoboda Signed-off-by: David Gibson Reviewed-by: Thomas Huth --- target-ppc/helper_regs.h | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/target-ppc/helper_regs.h b/target-ppc/helper_regs.h index bb9ce60..6213816 100644 --- a/target-ppc/helper_regs.h +++ b/target-ppc/helper_regs.h @@ -131,11 +131,14 @@ static inline int hreg_store_msr(CPUPPCState *env, target_ulong value, } /* If PR=1 then EE, IR and DR must be 1 * - * Note: We only enforce this on 64-bit processors. It appears that - * 32-bit implementations supports PR=1 and EE/DR/IR=0 and MacOS - * exploits it. + * Note: We only enforce this on 64-bit server processors. + * It appears that: + * - 32-bit implementations supports PR=1 and EE/DR/IR=0 and MacOS + * exploits it. + * - 64-bit embedded implementations do not need any operation to be + * performed when PR is set. */ - if ((env->insns_flags & PPC_64B) && ((value >> MSR_PR) & 1)) { + if ((env->insns_flags & PPC_SEGMENT_64B) && ((value >> MSR_PR) & 1)) { value |= (1 << MSR_EE) | (1 << MSR_DR) | (1 << MSR_IR); } #endif -- 2.7.4