From: Richard Henderson <rth@twiddle.net>
To: qemu-devel@nongnu.org
Cc: stefanha@redhat.com
Subject: [Qemu-devel] [PULL for-2.8] target-alpha: Fix interrupt mask for cpu1
Date: Wed, 23 Nov 2016 13:46:35 +0100 [thread overview]
Message-ID: <1479905195-7424-2-git-send-email-rth@twiddle.net> (raw)
In-Reply-To: <1479905195-7424-1-git-send-email-rth@twiddle.net>
A typo prevents ISA interrupts from being recognized on cpu0,
which is where the smp kernel normally wants to see them.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
hw/alpha/typhoon.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/alpha/typhoon.c b/hw/alpha/typhoon.c
index 883db13..f50f5cf 100644
--- a/hw/alpha/typhoon.c
+++ b/hw/alpha/typhoon.c
@@ -376,7 +376,7 @@ static void cchip_write(void *opaque, hwaddr addr,
break;
case 0x0240: /* DIM1 */
/* DIM: Device Interrupt Mask Register, CPU1. */
- s->cchip.dim[0] = val;
+ s->cchip.dim[1] = val;
cpu_irq_change(s->cchip.cpu[1], val & s->cchip.drir);
break;
--
2.7.4
next prev parent reply other threads:[~2016-11-23 12:47 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-11-23 12:46 [Qemu-devel] [PULL for-2.8] target-alpha: fix smp interrupts Richard Henderson
2016-11-23 12:46 ` Richard Henderson [this message]
2016-11-24 9:50 ` Stefan Hajnoczi
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