From: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
To: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, rth@twiddle.net
Cc: qemu-devel@nongnu.org, nikunj@linux.vnet.ibm.com,
bharata@linux.vnet.ibm.com
Subject: [Qemu-devel] [PATCH ppc-for-2.9 v2 0/2] POWER9 TCG enablements - part8
Date: Thu, 24 Nov 2016 17:02:42 +0530 [thread overview]
Message-ID: <1479987164-8301-1-git-send-email-nikunj@linux.vnet.ibm.com> (raw)
This series contains 6 new instructions for POWER9 ISA3.0
Vector Extract Left/Right Indexed
Changelog:
v1:
* Rebase
* Implement vextub[r,l]x using int128_rshift
v0:
* Change dq/ds-form decoding for primary opcode 0x3D
* Rename CR Field defines, as at every place it was
using bit shifts.
* Use symbolic constants in xscmp*
* Fix bug in exception handling for QNaN
* Define EXTRACT128 within CONFIG_INT128
Patches
=======
01:
vextublx: Vector Extract Unsigned Byte Left
vextuhlx: Vector Extract Unsigned Halfword Left
vextuwlx: Vector Extract Unsigned Word Left
02:
vextubrx: Vector Extract Unsigned Byte Right-Indexed
vextuhrx: Vector Extract Unsigned Halfword Right-Indexed
vextuwrx: Vector Extract Unsigned Word Right-Indexed
Avinesh Kumar (1):
target-ppc: add vextu[bhw]lx instructions
Hariharan T.S (1):
target-ppc: add vextu[bhw]rx instructions
target-ppc/helper.h | 6 +++
target-ppc/int_helper.c | 95 +++++++++++++++++++++++++++++++++++++
target-ppc/translate/vmx-impl.inc.c | 23 +++++++++
target-ppc/translate/vmx-ops.inc.c | 8 +++-
4 files changed, 130 insertions(+), 2 deletions(-)
--
2.7.4
next reply other threads:[~2016-11-24 11:33 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-11-24 11:32 Nikunj A Dadhania [this message]
2016-11-24 11:32 ` [Qemu-devel] [PATCH v2 1/2] target-ppc: add vextu[bhw]lx instructions Nikunj A Dadhania
2016-11-24 14:42 ` Richard Henderson
2016-11-25 7:13 ` Nikunj A Dadhania
2016-11-25 11:15 ` Richard Henderson
2016-11-24 11:32 ` [Qemu-devel] [PATCH v2 2/2] target-ppc: add vextu[bhw]rx instructions Nikunj A Dadhania
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