From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44276) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c9sHF-0006oN-DF for qemu-devel@nongnu.org; Thu, 24 Nov 2016 06:33:22 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1c9sHA-0005Co-9r for qemu-devel@nongnu.org; Thu, 24 Nov 2016 06:33:16 -0500 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:52837 helo=mx0a-001b2d01.pphosted.com) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1c9sHA-0005CO-39 for qemu-devel@nongnu.org; Thu, 24 Nov 2016 06:33:12 -0500 Received: from pps.filterd (m0098419.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.17/8.16.0.17) with SMTP id uAOBTHju027330 for ; Thu, 24 Nov 2016 06:33:11 -0500 Received: from e23smtp02.au.ibm.com (e23smtp02.au.ibm.com [202.81.31.144]) by mx0b-001b2d01.pphosted.com with ESMTP id 26wt6tvgtj-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Thu, 24 Nov 2016 06:33:10 -0500 Received: from localhost by e23smtp02.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Thu, 24 Nov 2016 21:33:08 +1000 From: Nikunj A Dadhania Date: Thu, 24 Nov 2016 17:02:42 +0530 Message-Id: <1479987164-8301-1-git-send-email-nikunj@linux.vnet.ibm.com> Subject: [Qemu-devel] [PATCH ppc-for-2.9 v2 0/2] POWER9 TCG enablements - part8 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, rth@twiddle.net Cc: qemu-devel@nongnu.org, nikunj@linux.vnet.ibm.com, bharata@linux.vnet.ibm.com This series contains 6 new instructions for POWER9 ISA3.0 Vector Extract Left/Right Indexed Changelog: v1: * Rebase * Implement vextub[r,l]x using int128_rshift v0: * Change dq/ds-form decoding for primary opcode 0x3D * Rename CR Field defines, as at every place it was using bit shifts. * Use symbolic constants in xscmp* * Fix bug in exception handling for QNaN * Define EXTRACT128 within CONFIG_INT128 Patches ======= 01: vextublx: Vector Extract Unsigned Byte Left vextuhlx: Vector Extract Unsigned Halfword Left vextuwlx: Vector Extract Unsigned Word Left 02: vextubrx: Vector Extract Unsigned Byte Right-Indexed vextuhrx: Vector Extract Unsigned Halfword Right-Indexed vextuwrx: Vector Extract Unsigned Word Right-Indexed Avinesh Kumar (1): target-ppc: add vextu[bhw]lx instructions Hariharan T.S (1): target-ppc: add vextu[bhw]rx instructions target-ppc/helper.h | 6 +++ target-ppc/int_helper.c | 95 +++++++++++++++++++++++++++++++++++++ target-ppc/translate/vmx-impl.inc.c | 23 +++++++++ target-ppc/translate/vmx-ops.inc.c | 8 +++- 4 files changed, 130 insertions(+), 2 deletions(-) -- 2.7.4