From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44309) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c9sHI-0006qK-K4 for qemu-devel@nongnu.org; Thu, 24 Nov 2016 06:33:21 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1c9sHE-0005E7-It for qemu-devel@nongnu.org; Thu, 24 Nov 2016 06:33:20 -0500 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:49565 helo=mx0a-001b2d01.pphosted.com) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1c9sHE-0005DD-D4 for qemu-devel@nongnu.org; Thu, 24 Nov 2016 06:33:16 -0500 Received: from pps.filterd (m0098414.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.17/8.16.0.17) with SMTP id uAOBTKL9119574 for ; Thu, 24 Nov 2016 06:33:13 -0500 Received: from e23smtp07.au.ibm.com (e23smtp07.au.ibm.com [202.81.31.140]) by mx0b-001b2d01.pphosted.com with ESMTP id 26wt6umfby-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Thu, 24 Nov 2016 06:33:13 -0500 Received: from localhost by e23smtp07.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Thu, 24 Nov 2016 21:33:10 +1000 From: Nikunj A Dadhania Date: Thu, 24 Nov 2016 17:02:44 +0530 In-Reply-To: <1479987164-8301-1-git-send-email-nikunj@linux.vnet.ibm.com> References: <1479987164-8301-1-git-send-email-nikunj@linux.vnet.ibm.com> Message-Id: <1479987164-8301-3-git-send-email-nikunj@linux.vnet.ibm.com> Subject: [Qemu-devel] [PATCH v2 2/2] target-ppc: add vextu[bhw]rx instructions List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, rth@twiddle.net Cc: qemu-devel@nongnu.org, nikunj@linux.vnet.ibm.com, bharata@linux.vnet.ibm.com, "Hariharan T.S" , Avinesh Kumar From: "Hariharan T.S" vextubrx: Vector Extract Unsigned Byte Right-Indexed VX-form vextuhrx: Vector Extract Unsigned Halfword Right-Indexed VX-form vextuwrx: Vector Extract Unsigned Word Right-Indexed VX-form Signed-off-by: Hariharan T.S. Signed-off-by: Avinesh Kumar [ Implement using int128_rshift ] Signed-off-by: Nikunj A Dadhania --- target-ppc/helper.h | 3 +++ target-ppc/int_helper.c | 47 +++++++++++++++++++++++++++++++++++++ target-ppc/translate/vmx-impl.inc.c | 5 ++++ target-ppc/translate/vmx-ops.inc.c | 4 +++- 4 files changed, 58 insertions(+), 1 deletion(-) diff --git a/target-ppc/helper.h b/target-ppc/helper.h index d0a8fb2..a6e04cb 100644 --- a/target-ppc/helper.h +++ b/target-ppc/helper.h @@ -369,6 +369,9 @@ DEF_HELPER_3(vpmsumd, void, avr, avr, avr) DEF_HELPER_2(vextublx, tl, tl, avr) DEF_HELPER_2(vextuhlx, tl, tl, avr) DEF_HELPER_2(vextuwlx, tl, tl, avr) +DEF_HELPER_2(vextubrx, tl, tl, avr) +DEF_HELPER_2(vextuhrx, tl, tl, avr) +DEF_HELPER_2(vextuwrx, tl, tl, avr) DEF_HELPER_2(vsbox, void, avr, avr) DEF_HELPER_3(vcipher, void, avr, avr, avr) diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c index 2aa4474..406e23a 100644 --- a/target-ppc/int_helper.c +++ b/target-ppc/int_helper.c @@ -1853,6 +1853,53 @@ VEXTULX_DO(vextuhlx, 16) VEXTULX_DO(vextuwlx, 32) #undef VEXTULX_DO +#if defined(HOST_WORDS_BIGENDIAN) +# if defined(CONFIG_INT128) +# define VEXTURX_DO(name, size) \ + target_ulong glue(helper_, name)(target_ulong a, ppc_avr_t *b) \ + { \ + int index = (15 - (a & 0xf) + 1) * 8; \ + return int128_rshift(b->u128, index - size) & \ + MAKE_64BIT_MASK(0, size); \ + } +# else +# define VEXTURX_DO(name, size) \ + target_ulong glue(helper_, name)(target_ulong a, ppc_avr_t *b) \ + { \ + int index = (15 - (a & 0xf) + 1) * 8; \ + Int128 value = int128_make128(b->u64[LO_IDX], \ + b->u64[HI_IDX]); \ + return int128_rshift(value, index - size) & \ + MAKE_64BIT_MASK(0, size); \ + } +# endif +#else +# if defined(CONFIG_INT128) +# define VEXTURX_DO(name, size) \ + target_ulong glue(helper_, name)(target_ulong a, ppc_avr_t *b) \ + { \ + int index = (a & 0xf) * 8; \ + return int128_rshift(b->u128, index) & \ + MAKE_64BIT_MASK(0, size); \ + } +# else +# define VEXTURX_DO(name, size) \ + target_ulong glue(helper_, name)(target_ulong a, ppc_avr_t *b) \ + { \ + int index = (a & 0xf) * 8; \ + Int128 value = int128_make128(b->u64[LO_IDX], \ + b->u64[HI_IDX]); \ + return int128_rshift(value, index) & \ + MAKE_64BIT_MASK(0, size); \ + } +# endif +#endif + +VEXTURX_DO(vextubrx, 8) +VEXTURX_DO(vextuhrx, 16) +VEXTURX_DO(vextuwrx, 32) +#undef VEXTURX_DO + /* The specification says that the results are undefined if all of the * shift counts are not identical. We check to make sure that they are * to conform to what real hardware appears to do. */ diff --git a/target-ppc/translate/vmx-impl.inc.c b/target-ppc/translate/vmx-impl.inc.c index e91d10b..3dea465 100644 --- a/target-ppc/translate/vmx-impl.inc.c +++ b/target-ppc/translate/vmx-impl.inc.c @@ -543,6 +543,11 @@ GEN_VXFORM_HETRO(vextuhlx, 6, 25) GEN_VXFORM_HETRO(vextuwlx, 6, 26) GEN_VXFORM_DUAL(vmrgow, PPC_NONE, PPC2_ALTIVEC_207, vextuwlx, PPC_NONE, PPC2_ISA300) +GEN_VXFORM_HETRO(vextubrx, 6, 28) +GEN_VXFORM_HETRO(vextuhrx, 6, 29) +GEN_VXFORM_HETRO(vextuwrx, 6, 30) +GEN_VXFORM_DUAL(vmrgew, PPC_NONE, PPC2_ALTIVEC_207, \ + vextuwrx, PPC_NONE, PPC2_ISA300) #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \ static void glue(gen_, name)(DisasContext *ctx) \ diff --git a/target-ppc/translate/vmx-ops.inc.c b/target-ppc/translate/vmx-ops.inc.c index e62e564..a3c9d05 100644 --- a/target-ppc/translate/vmx-ops.inc.c +++ b/target-ppc/translate/vmx-ops.inc.c @@ -94,7 +94,9 @@ GEN_VXFORM(vmrglw, 6, 6), GEN_VXFORM_300(vextublx, 6, 24), GEN_VXFORM_300(vextuhlx, 6, 25), GEN_VXFORM_DUAL(vmrgow, vextuwlx, 6, 26, PPC_NONE, PPC2_ALTIVEC_207), -GEN_VXFORM_207(vmrgew, 6, 30), +GEN_VXFORM_300(vextubrx, 6, 28), +GEN_VXFORM_300(vextuhrx, 6, 29), +GEN_VXFORM_DUAL(vmrgew, vextuwrx, 6, 30, PPC_NONE, PPC2_ALTIVEC_207), GEN_VXFORM(vmuloub, 4, 0), GEN_VXFORM(vmulouh, 4, 1), GEN_VXFORM_DUAL(vmulouw, vmuluwm, 4, 2, PPC_ALTIVEC, PPC_NONE), -- 2.7.4