[Qemu-devel] [PATCH ppc-for-2.9 v2 0/2] POWER9 TCG enablements

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* [Qemu-devel] [PATCH ppc-for-2.9 v2 0/2] POWER9 TCG enablements - part8
@ 2016-11-24 11:32 Nikunj A Dadhania
  2016-11-24 11:32 ` [Qemu-devel] [PATCH v2 1/2] target-ppc: add vextu[bhw]lx instructions Nikunj A Dadhania
  2016-11-24 11:32 ` [Qemu-devel] [PATCH v2 2/2] target-ppc: add vextu[bhw]rx instructions Nikunj A Dadhania
  0 siblings, 2 replies; 6+ messages in thread
From: Nikunj A Dadhania @ 2016-11-24 11:32 UTC (permalink / raw)
  To: qemu-ppc, david, rth; +Cc: qemu-devel, nikunj, bharata

This series contains 6 new instructions for POWER9 ISA3.0
    Vector Extract Left/Right Indexed

Changelog:
v1:
* Rebase
* Implement vextub[r,l]x using int128_rshift

v0:
* Change dq/ds-form decoding for primary opcode 0x3D
* Rename CR Field defines, as at every place it was
  using bit shifts.
* Use symbolic constants in xscmp*
* Fix bug in exception handling for QNaN
* Define EXTRACT128 within CONFIG_INT128

Patches
=======
   01: 
      vextublx:  Vector Extract Unsigned Byte Left
      vextuhlx:  Vector Extract Unsigned Halfword Left
      vextuwlx:  Vector Extract Unsigned Word Left
   02: 
      vextubrx: Vector Extract Unsigned Byte Right-Indexed
      vextuhrx: Vector Extract Unsigned  Halfword Right-Indexed
      vextuwrx: Vector Extract Unsigned Word Right-Indexed


Avinesh Kumar (1):
  target-ppc: add vextu[bhw]lx instructions

Hariharan T.S (1):
  target-ppc: add vextu[bhw]rx instructions

 target-ppc/helper.h                 |  6 +++
 target-ppc/int_helper.c             | 95 +++++++++++++++++++++++++++++++++++++
 target-ppc/translate/vmx-impl.inc.c | 23 +++++++++
 target-ppc/translate/vmx-ops.inc.c  |  8 +++-
 4 files changed, 130 insertions(+), 2 deletions(-)

-- 
2.7.4

^ permalink raw reply	[flat|nested] 6+ messages in thread

* [Qemu-devel] [PATCH v2 1/2] target-ppc: add vextu[bhw]lx instructions
  2016-11-24 11:32 [Qemu-devel] [PATCH ppc-for-2.9 v2 0/2] POWER9 TCG enablements - part8 Nikunj A Dadhania
@ 2016-11-24 11:32 ` Nikunj A Dadhania
  2016-11-24 14:42   ` Richard Henderson
  2016-11-24 11:32 ` [Qemu-devel] [PATCH v2 2/2] target-ppc: add vextu[bhw]rx instructions Nikunj A Dadhania
  1 sibling, 1 reply; 6+ messages in thread
From: Nikunj A Dadhania @ 2016-11-24 11:32 UTC (permalink / raw)
  To: qemu-ppc, david, rth; +Cc: qemu-devel, nikunj, bharata, Avinesh Kumar

From: Avinesh Kumar <avinesku@linux.vnet.ibm.com>

vextublx:  Vector Extract Unsigned Byte Left
vextuhlx:  Vector Extract Unsigned Halfword Left
vextuwlx:  Vector Extract Unsigned Word Left

Signed-off-by: Avinesh Kumar <avinesku@linux.vnet.ibm.com>
[ implement using int128_rshift ]
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
 target-ppc/helper.h                 |  3 +++
 target-ppc/int_helper.c             | 48 +++++++++++++++++++++++++++++++++++++
 target-ppc/translate/vmx-impl.inc.c | 18 ++++++++++++++
 target-ppc/translate/vmx-ops.inc.c  |  4 +++-
 4 files changed, 72 insertions(+), 1 deletion(-)

diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 3b26678..d0a8fb2 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -366,6 +366,9 @@ DEF_HELPER_3(vpmsumb, void, avr, avr, avr)
 DEF_HELPER_3(vpmsumh, void, avr, avr, avr)
 DEF_HELPER_3(vpmsumw, void, avr, avr, avr)
 DEF_HELPER_3(vpmsumd, void, avr, avr, avr)
+DEF_HELPER_2(vextublx, tl, tl, avr)
+DEF_HELPER_2(vextuhlx, tl, tl, avr)
+DEF_HELPER_2(vextuwlx, tl, tl, avr)
 
 DEF_HELPER_2(vsbox, void, avr, avr)
 DEF_HELPER_3(vcipher, void, avr, avr, avr)
diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
index fbf477f..2aa4474 100644
--- a/target-ppc/int_helper.c
+++ b/target-ppc/int_helper.c
@@ -17,6 +17,7 @@
  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  */
 #include "qemu/osdep.h"
+#include "qemu/int128.h"
 #include "cpu.h"
 #include "internal.h"
 #include "exec/exec-all.h"
@@ -1805,6 +1806,53 @@ void helper_vlogefp(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *b)
     }
 }
 
+#if defined(HOST_WORDS_BIGENDIAN)
+# if defined(CONFIG_INT128)
+# define VEXTULX_DO(name, size)                                     \
+    target_ulong glue(helper_, name)(target_ulong a, ppc_avr_t *b)  \
+    {                                                               \
+        int index = (a & 0xf) * 8;                                  \
+        return int128_rshift(b->u128, index) &                      \
+            MAKE_64BIT_MASK(0, size);                               \
+    }
+# else
+# define VEXTULX_DO(name, size)                                     \
+    target_ulong glue(helper_, name)(target_ulong a, ppc_avr_t *b)  \
+    {                                                               \
+        int index = (a & 0xf) * 8;                                  \
+        Int128 value = int128_make128(b->u64[LO_IDX],               \
+                                      b->u64[HI_IDX]);              \
+        return int128_rshift(value, index) &                        \
+            MAKE_64BIT_MASK(0, size);                               \
+    }
+# endif
+#else
+# if defined(CONFIG_INT128)
+# define VEXTULX_DO(name, size)                                     \
+    target_ulong glue(helper_, name)(target_ulong a, ppc_avr_t *b)  \
+    {                                                               \
+        int index = (15 - (a & 0xf) + 1) * 8;                       \
+        return int128_rshift(b->u128, index - size) &               \
+            MAKE_64BIT_MASK(0, size);                               \
+    }
+# else
+# define VEXTULX_DO(name, size)                                     \
+    target_ulong glue(helper_, name)(target_ulong a, ppc_avr_t *b)  \
+    {                                                               \
+        int index = (15 - (a & 0xf) + 1) * 8;                       \
+        Int128 value = int128_make128(b->u64[LO_IDX],               \
+                                      b->u64[HI_IDX]);              \
+        return int128_rshift(value, index - size) &                 \
+            MAKE_64BIT_MASK(0, size);                               \
+    }
+# endif
+#endif
+
+VEXTULX_DO(vextublx, 8)
+VEXTULX_DO(vextuhlx, 16)
+VEXTULX_DO(vextuwlx, 32)
+#undef VEXTULX_DO
+
 /* The specification says that the results are undefined if all of the
  * shift counts are not identical.  We check to make sure that they are
  * to conform to what real hardware appears to do.  */
diff --git a/target-ppc/translate/vmx-impl.inc.c b/target-ppc/translate/vmx-impl.inc.c
index 7143eb3..e91d10b 100644
--- a/target-ppc/translate/vmx-impl.inc.c
+++ b/target-ppc/translate/vmx-impl.inc.c
@@ -340,6 +340,19 @@ static void glue(gen_, name0##_##name1)(DisasContext *ctx)              \
     }                                                                   \
 }
 
+#define GEN_VXFORM_HETRO(name, opc2, opc3)                              \
+static void glue(gen_, name)(DisasContext *ctx)                         \
+{                                                                       \
+    TCGv_ptr rb;                                                        \
+    if (unlikely(!ctx->altivec_enabled)) {                              \
+        gen_exception(ctx, POWERPC_EXCP_VPU);                           \
+        return;                                                         \
+    }                                                                   \
+    rb = gen_avr_ptr(rB(ctx->opcode));                                  \
+    gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], rb); \
+    tcg_temp_free_ptr(rb);                                              \
+}
+
 GEN_VXFORM(vaddubm, 0, 0);
 GEN_VXFORM_DUAL_EXT(vaddubm, PPC_ALTIVEC, PPC_NONE, 0,       \
                     vmul10cuq, PPC_NONE, PPC2_ISA300, 0x0000F800)
@@ -525,6 +538,11 @@ GEN_VXFORM_ENV(vaddfp, 5, 0);
 GEN_VXFORM_ENV(vsubfp, 5, 1);
 GEN_VXFORM_ENV(vmaxfp, 5, 16);
 GEN_VXFORM_ENV(vminfp, 5, 17);
+GEN_VXFORM_HETRO(vextublx, 6, 24)
+GEN_VXFORM_HETRO(vextuhlx, 6, 25)
+GEN_VXFORM_HETRO(vextuwlx, 6, 26)
+GEN_VXFORM_DUAL(vmrgow, PPC_NONE, PPC2_ALTIVEC_207,
+                vextuwlx, PPC_NONE, PPC2_ISA300)
 
 #define GEN_VXRFORM1(opname, name, str, opc2, opc3)                     \
 static void glue(gen_, name)(DisasContext *ctx)                         \
diff --git a/target-ppc/translate/vmx-ops.inc.c b/target-ppc/translate/vmx-ops.inc.c
index f02b3be..e62e564 100644
--- a/target-ppc/translate/vmx-ops.inc.c
+++ b/target-ppc/translate/vmx-ops.inc.c
@@ -91,8 +91,10 @@ GEN_VXFORM(vmrghw, 6, 2),
 GEN_VXFORM(vmrglb, 6, 4),
 GEN_VXFORM(vmrglh, 6, 5),
 GEN_VXFORM(vmrglw, 6, 6),
+GEN_VXFORM_300(vextublx, 6, 24),
+GEN_VXFORM_300(vextuhlx, 6, 25),
+GEN_VXFORM_DUAL(vmrgow, vextuwlx, 6, 26, PPC_NONE, PPC2_ALTIVEC_207),
 GEN_VXFORM_207(vmrgew, 6, 30),
-GEN_VXFORM_207(vmrgow, 6, 26),
 GEN_VXFORM(vmuloub, 4, 0),
 GEN_VXFORM(vmulouh, 4, 1),
 GEN_VXFORM_DUAL(vmulouw, vmuluwm, 4, 2, PPC_ALTIVEC, PPC_NONE),
-- 
2.7.4

^ permalink raw reply related	[flat|nested] 6+ messages in thread

* Re: [Qemu-devel] [PATCH v2 1/2] target-ppc: add vextu[bhw]lx instructions
  2016-11-24 11:32 ` [Qemu-devel] [PATCH v2 1/2] target-ppc: add vextu[bhw]lx instructions Nikunj A Dadhania
@ 2016-11-24 14:42   ` Richard Henderson
  2016-11-25  7:13     ` Nikunj A Dadhania
  0 siblings, 1 reply; 6+ messages in thread
From: Richard Henderson @ 2016-11-24 14:42 UTC (permalink / raw)
  To: Nikunj A Dadhania, qemu-ppc, david; +Cc: qemu-devel, bharata, Avinesh Kumar

On 11/24/2016 12:32 PM, Nikunj A Dadhania wrote:
> +#if defined(HOST_WORDS_BIGENDIAN)
> +# if defined(CONFIG_INT128)
> +# define VEXTULX_DO(name, size)                                     \
> +    target_ulong glue(helper_, name)(target_ulong a, ppc_avr_t *b)  \
> +    {                                                               \
> +        int index = (a & 0xf) * 8;                                  \
> +        return int128_rshift(b->u128, index) &                      \
> +            MAKE_64BIT_MASK(0, size);                               \
> +    }
> +# else
> +# define VEXTULX_DO(name, size)                                     \
> +    target_ulong glue(helper_, name)(target_ulong a, ppc_avr_t *b)  \
> +    {                                                               \
> +        int index = (a & 0xf) * 8;                                  \
> +        Int128 value = int128_make128(b->u64[LO_IDX],               \
> +                                      b->u64[HI_IDX]);              \
> +        return int128_rshift(value, index) &                        \
> +            MAKE_64BIT_MASK(0, size);                               \
> +    }
> +# endif

Why are these duplicated?

Clearly the missed trick is that you should *never* check CONFIG_INT128 and 
always rely on Int128.


r~

^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [Qemu-devel] [PATCH v2 1/2] target-ppc: add vextu[bhw]lx instructions
  2016-11-24 14:42   ` Richard Henderson
@ 2016-11-25  7:13     ` Nikunj A Dadhania
  2016-11-25 11:15       ` Richard Henderson
  0 siblings, 1 reply; 6+ messages in thread
From: Nikunj A Dadhania @ 2016-11-25  7:13 UTC (permalink / raw)
  To: Richard Henderson, qemu-ppc, david; +Cc: qemu-devel, bharata, Avinesh Kumar

Richard Henderson <rth@twiddle.net> writes:

> On 11/24/2016 12:32 PM, Nikunj A Dadhania wrote:
>> +#if defined(HOST_WORDS_BIGENDIAN)
>> +# if defined(CONFIG_INT128)
>> +# define VEXTULX_DO(name, size)                                     \
>> +    target_ulong glue(helper_, name)(target_ulong a, ppc_avr_t *b)  \
>> +    {                                                               \
>> +        int index = (a & 0xf) * 8;                                  \
>> +        return int128_rshift(b->u128, index) &                      \
>> +            MAKE_64BIT_MASK(0, size);                               \
>> +    }
>> +# else
>> +# define VEXTULX_DO(name, size)                                     \
>> +    target_ulong glue(helper_, name)(target_ulong a, ppc_avr_t *b)  \
>> +    {                                                               \
>> +        int index = (a & 0xf) * 8;                                  \
>> +        Int128 value = int128_make128(b->u64[LO_IDX],               \
>> +                                      b->u64[HI_IDX]);              \
>> +        return int128_rshift(value, index) &                        \
>> +            MAKE_64BIT_MASK(0, size);                               \
>> +    }
>> +# endif
>
> Why are these duplicated?
>
> Clearly the missed trick is that you should *never* check CONFIG_INT128 and 
> always rely on Int128.

Because of this:

/* Altivec registers (128 bits) */
union ppc_avr_t {

[ SNIP ]

    uint64_t u64[2];
    int64_t s64[2];
#ifdef CONFIG_INT128
    __uint128_t u128;
#endif
};

So I composed a Int128 using make128 with lo and hi to get a
Int128, and then call int128_rshift. 

I think I can use "Int128 u128" in that union and that should do the
trick ! I will try that out.

Regards
Nikunj

^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [Qemu-devel] [PATCH v2 1/2] target-ppc: add vextu[bhw]lx instructions
  2016-11-25  7:13     ` Nikunj A Dadhania
@ 2016-11-25 11:15       ` Richard Henderson
  0 siblings, 0 replies; 6+ messages in thread
From: Richard Henderson @ 2016-11-25 11:15 UTC (permalink / raw)
  To: Nikunj A Dadhania, qemu-ppc, david; +Cc: qemu-devel, bharata, Avinesh Kumar

On 11/25/2016 08:13 AM, Nikunj A Dadhania wrote:
> I think I can use "Int128 u128" in that union and that should do the
> trick ! I will try that out.

Yes, that's what I meant.


r~

^ permalink raw reply	[flat|nested] 6+ messages in thread

* [Qemu-devel] [PATCH v2 2/2] target-ppc: add vextu[bhw]rx instructions
  2016-11-24 11:32 [Qemu-devel] [PATCH ppc-for-2.9 v2 0/2] POWER9 TCG enablements - part8 Nikunj A Dadhania
  2016-11-24 11:32 ` [Qemu-devel] [PATCH v2 1/2] target-ppc: add vextu[bhw]lx instructions Nikunj A Dadhania
@ 2016-11-24 11:32 ` Nikunj A Dadhania
  1 sibling, 0 replies; 6+ messages in thread
From: Nikunj A Dadhania @ 2016-11-24 11:32 UTC (permalink / raw)
  To: qemu-ppc, david, rth
  Cc: qemu-devel, nikunj, bharata, Hariharan T.S, Avinesh Kumar

From: "Hariharan T.S" <hari@linux.vnet.ibm.com>

vextubrx: Vector Extract Unsigned Byte Right-Indexed VX-form
vextuhrx: Vector Extract Unsigned  Halfword Right-Indexed VX-form
vextuwrx: Vector Extract Unsigned Word Right-Indexed VX-form

Signed-off-by: Hariharan T.S. <hari@linux.vnet.ibm.com>
Signed-off-by: Avinesh Kumar <avinesku@linux.vnet.ibm.com>
[ Implement using int128_rshift ]
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
 target-ppc/helper.h                 |  3 +++
 target-ppc/int_helper.c             | 47 +++++++++++++++++++++++++++++++++++++
 target-ppc/translate/vmx-impl.inc.c |  5 ++++
 target-ppc/translate/vmx-ops.inc.c  |  4 +++-
 4 files changed, 58 insertions(+), 1 deletion(-)

diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index d0a8fb2..a6e04cb 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -369,6 +369,9 @@ DEF_HELPER_3(vpmsumd, void, avr, avr, avr)
 DEF_HELPER_2(vextublx, tl, tl, avr)
 DEF_HELPER_2(vextuhlx, tl, tl, avr)
 DEF_HELPER_2(vextuwlx, tl, tl, avr)
+DEF_HELPER_2(vextubrx, tl, tl, avr)
+DEF_HELPER_2(vextuhrx, tl, tl, avr)
+DEF_HELPER_2(vextuwrx, tl, tl, avr)
 
 DEF_HELPER_2(vsbox, void, avr, avr)
 DEF_HELPER_3(vcipher, void, avr, avr, avr)
diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
index 2aa4474..406e23a 100644
--- a/target-ppc/int_helper.c
+++ b/target-ppc/int_helper.c
@@ -1853,6 +1853,53 @@ VEXTULX_DO(vextuhlx, 16)
 VEXTULX_DO(vextuwlx, 32)
 #undef VEXTULX_DO
 
+#if defined(HOST_WORDS_BIGENDIAN)
+# if defined(CONFIG_INT128)
+# define VEXTURX_DO(name, size)                                     \
+    target_ulong glue(helper_, name)(target_ulong a, ppc_avr_t *b)  \
+    {                                                               \
+        int index = (15 - (a & 0xf) + 1) * 8;                       \
+        return int128_rshift(b->u128, index - size) &               \
+            MAKE_64BIT_MASK(0, size);                               \
+    }
+# else
+# define VEXTURX_DO(name, size)                                     \
+    target_ulong glue(helper_, name)(target_ulong a, ppc_avr_t *b)  \
+    {                                                               \
+        int index = (15 - (a & 0xf) + 1) * 8;                       \
+        Int128 value = int128_make128(b->u64[LO_IDX],               \
+                                      b->u64[HI_IDX]);              \
+        return int128_rshift(value, index - size) &                 \
+            MAKE_64BIT_MASK(0, size);                               \
+    }
+# endif
+#else
+# if defined(CONFIG_INT128)
+# define VEXTURX_DO(name, size)                                     \
+    target_ulong glue(helper_, name)(target_ulong a, ppc_avr_t *b)  \
+    {                                                               \
+        int index = (a & 0xf) * 8;                                  \
+        return int128_rshift(b->u128, index) &                      \
+            MAKE_64BIT_MASK(0, size);                               \
+    }
+# else
+# define VEXTURX_DO(name, size)                                     \
+    target_ulong glue(helper_, name)(target_ulong a, ppc_avr_t *b)  \
+    {                                                               \
+        int index = (a & 0xf) * 8;                                  \
+        Int128 value = int128_make128(b->u64[LO_IDX],               \
+                                      b->u64[HI_IDX]);              \
+        return int128_rshift(value, index) &                        \
+            MAKE_64BIT_MASK(0, size);                               \
+    }
+# endif
+#endif
+
+VEXTURX_DO(vextubrx, 8)
+VEXTURX_DO(vextuhrx, 16)
+VEXTURX_DO(vextuwrx, 32)
+#undef VEXTURX_DO
+
 /* The specification says that the results are undefined if all of the
  * shift counts are not identical.  We check to make sure that they are
  * to conform to what real hardware appears to do.  */
diff --git a/target-ppc/translate/vmx-impl.inc.c b/target-ppc/translate/vmx-impl.inc.c
index e91d10b..3dea465 100644
--- a/target-ppc/translate/vmx-impl.inc.c
+++ b/target-ppc/translate/vmx-impl.inc.c
@@ -543,6 +543,11 @@ GEN_VXFORM_HETRO(vextuhlx, 6, 25)
 GEN_VXFORM_HETRO(vextuwlx, 6, 26)
 GEN_VXFORM_DUAL(vmrgow, PPC_NONE, PPC2_ALTIVEC_207,
                 vextuwlx, PPC_NONE, PPC2_ISA300)
+GEN_VXFORM_HETRO(vextubrx, 6, 28)
+GEN_VXFORM_HETRO(vextuhrx, 6, 29)
+GEN_VXFORM_HETRO(vextuwrx, 6, 30)
+GEN_VXFORM_DUAL(vmrgew, PPC_NONE, PPC2_ALTIVEC_207, \
+                vextuwrx, PPC_NONE, PPC2_ISA300)
 
 #define GEN_VXRFORM1(opname, name, str, opc2, opc3)                     \
 static void glue(gen_, name)(DisasContext *ctx)                         \
diff --git a/target-ppc/translate/vmx-ops.inc.c b/target-ppc/translate/vmx-ops.inc.c
index e62e564..a3c9d05 100644
--- a/target-ppc/translate/vmx-ops.inc.c
+++ b/target-ppc/translate/vmx-ops.inc.c
@@ -94,7 +94,9 @@ GEN_VXFORM(vmrglw, 6, 6),
 GEN_VXFORM_300(vextublx, 6, 24),
 GEN_VXFORM_300(vextuhlx, 6, 25),
 GEN_VXFORM_DUAL(vmrgow, vextuwlx, 6, 26, PPC_NONE, PPC2_ALTIVEC_207),
-GEN_VXFORM_207(vmrgew, 6, 30),
+GEN_VXFORM_300(vextubrx, 6, 28),
+GEN_VXFORM_300(vextuhrx, 6, 29),
+GEN_VXFORM_DUAL(vmrgew, vextuwrx, 6, 30, PPC_NONE, PPC2_ALTIVEC_207),
 GEN_VXFORM(vmuloub, 4, 0),
 GEN_VXFORM(vmulouh, 4, 1),
 GEN_VXFORM_DUAL(vmulouw, vmuluwm, 4, 2, PPC_ALTIVEC, PPC_NONE),
-- 
2.7.4

^ permalink raw reply related	[flat|nested] 6+ messages in thread

end of thread, other threads:[~2016-11-25 11:16 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2016-11-24 11:32 [Qemu-devel] [PATCH ppc-for-2.9 v2 0/2] POWER9 TCG enablements - part8 Nikunj A Dadhania
2016-11-24 11:32 ` [Qemu-devel] [PATCH v2 1/2] target-ppc: add vextu[bhw]lx instructions Nikunj A Dadhania
2016-11-24 14:42   ` Richard Henderson
2016-11-25  7:13     ` Nikunj A Dadhania
2016-11-25 11:15       ` Richard Henderson
2016-11-24 11:32 ` [Qemu-devel] [PATCH v2 2/2] target-ppc: add vextu[bhw]rx instructions Nikunj A Dadhania

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