From: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com>
To: qemu-ppc@nongnu.org
Cc: qemu-devel@nongnu.org, david@gibson.dropbear.id.au,
nikunj@linux.vnet.ibm.com, bharata@linux.vnet.ibm.com
Subject: [Qemu-devel] [PATCH v3 3/4] target-ppc: Implement bcdcpsgn. instruction
Date: Fri, 25 Nov 2016 01:53:32 -0200 [thread overview]
Message-ID: <1480046013-24788-4-git-send-email-joserz@linux.vnet.ibm.com> (raw)
In-Reply-To: <1480046013-24788-1-git-send-email-joserz@linux.vnet.ibm.com>
bcdcpsgn.: Decimal copy sign. Given two registers vra and vrb, it
copies the vra value with vrb sign to the result register vrt.
Signed-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
---
target-ppc/helper.h | 1 +
target-ppc/int_helper.c | 23 +++++++++++++++++++++++
target-ppc/translate/vmx-impl.inc.c | 3 +++
target-ppc/translate/vmx-ops.inc.c | 2 +-
4 files changed, 28 insertions(+), 1 deletion(-)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index d404e0b..2974101 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -384,6 +384,7 @@ DEF_HELPER_3(bcdcfz, i32, avr, avr, i32)
DEF_HELPER_3(bcdctz, i32, avr, avr, i32)
DEF_HELPER_3(bcdcfsq, i32, avr, avr, i32)
DEF_HELPER_3(bcdctsq, i32, avr, avr, i32)
+DEF_HELPER_4(bcdcpsgn, i32, avr, avr, avr, i32)
DEF_HELPER_2(xsadddp, void, env, i32)
DEF_HELPER_2(xssubdp, void, env, i32)
diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
index 4153f19..e69a5a4 100644
--- a/target-ppc/int_helper.c
+++ b/target-ppc/int_helper.c
@@ -2952,6 +2952,29 @@ uint32_t helper_bcdctsq(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps)
return cr;
}
+uint32_t helper_bcdcpsgn(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t ps)
+{
+ int i;
+ int invalid = 0;
+
+ if (bcd_get_sgn(a) == 0 || bcd_get_sgn(b) == 0) {
+ return CRF_SO;
+ }
+
+ *r = *a;
+ bcd_put_digit(r, b->u8[BCD_DIG_BYTE(0)] & 0xF, 0);
+
+ for (i = 1; i < 32; i++) {
+ bcd_get_digit(a, i, &invalid);
+ bcd_get_digit(b, i, &invalid);
+ if (unlikely(invalid)) {
+ return CRF_SO;
+ }
+ }
+
+ return bcd_cmp_zero(r);
+}
+
void helper_vsbox(ppc_avr_t *r, ppc_avr_t *a)
{
int i;
diff --git a/target-ppc/translate/vmx-impl.inc.c b/target-ppc/translate/vmx-impl.inc.c
index 1579b58..c14b666 100644
--- a/target-ppc/translate/vmx-impl.inc.c
+++ b/target-ppc/translate/vmx-impl.inc.c
@@ -991,6 +991,7 @@ GEN_BCD2(bcdcfz)
GEN_BCD2(bcdctz)
GEN_BCD2(bcdcfsq)
GEN_BCD2(bcdctsq)
+GEN_BCD(bcdcpsgn);
static void gen_xpnd04_1(DisasContext *ctx)
{
@@ -1056,6 +1057,8 @@ GEN_VXFORM_DUAL(vsubuhm, PPC_ALTIVEC, PPC_NONE, \
bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
GEN_VXFORM_DUAL(vsubuhs, PPC_ALTIVEC, PPC_NONE, \
bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
+GEN_VXFORM_DUAL(vaddshs, PPC_ALTIVEC, PPC_NONE, \
+ bcdcpsgn, PPC_NONE, PPC2_ISA300)
static void gen_vsbox(DisasContext *ctx)
{
diff --git a/target-ppc/translate/vmx-ops.inc.c b/target-ppc/translate/vmx-ops.inc.c
index f02b3be..70d7d2b 100644
--- a/target-ppc/translate/vmx-ops.inc.c
+++ b/target-ppc/translate/vmx-ops.inc.c
@@ -131,7 +131,7 @@ GEN_VXFORM_DUAL(vaddubs, vmul10uq, 0, 8, PPC_ALTIVEC, PPC_NONE),
GEN_VXFORM_DUAL(vadduhs, vmul10euq, 0, 9, PPC_ALTIVEC, PPC_NONE),
GEN_VXFORM(vadduws, 0, 10),
GEN_VXFORM(vaddsbs, 0, 12),
-GEN_VXFORM(vaddshs, 0, 13),
+GEN_VXFORM_DUAL(vaddshs, bcdcpsgn, 0, 13, PPC_ALTIVEC, PPC_NONE),
GEN_VXFORM(vaddsws, 0, 14),
GEN_VXFORM_DUAL(vsububs, bcdadd, 0, 24, PPC_ALTIVEC, PPC_NONE),
GEN_VXFORM_DUAL(vsubuhs, bcdsub, 0, 25, PPC_ALTIVEC, PPC_NONE),
--
2.7.4
next prev parent reply other threads:[~2016-11-25 3:54 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-11-25 3:53 [Qemu-devel] [PATCH v3 0/4] POWER9 TCG enablements - BCD functions part II Jose Ricardo Ziviani
2016-11-25 3:53 ` [Qemu-devel] [PATCH v3 1/4] target-ppc: Implement bcdcfsq. instruction Jose Ricardo Ziviani
2016-11-25 4:52 ` David Gibson
2016-11-25 3:53 ` [Qemu-devel] [PATCH v3 2/4] target-ppc: Implement bcdctsq. instruction Jose Ricardo Ziviani
2016-11-25 3:53 ` Jose Ricardo Ziviani [this message]
2016-11-25 3:53 ` [Qemu-devel] [PATCH v3 4/4] target-ppc: Implement bcdsetsgn. instruction Jose Ricardo Ziviani
2016-11-25 4:52 ` [Qemu-devel] [PATCH v3 0/4] POWER9 TCG enablements - BCD functions part II David Gibson
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