From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42636) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cBmBQ-0001Q9-1K for qemu-devel@nongnu.org; Tue, 29 Nov 2016 12:27:09 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cBmBK-0004tC-CW for qemu-devel@nongnu.org; Tue, 29 Nov 2016 12:27:08 -0500 Received: from 1.mo69.mail-out.ovh.net ([178.33.251.173]:48071) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1cBmBK-0004sv-6I for qemu-devel@nongnu.org; Tue, 29 Nov 2016 12:27:02 -0500 Received: from player699.ha.ovh.net (b9.ovh.net [213.186.33.59]) by mo69.mail-out.ovh.net (Postfix) with ESMTP id 55645C4B3 for ; Tue, 29 Nov 2016 18:26:59 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Tue, 29 Nov 2016 18:26:47 +0100 Message-Id: <1480440408-30674-1-git-send-email-clg@kaod.org> In-Reply-To: <1480434248-27138-1-git-send-email-clg@kaod.org> References: <1480434248-27138-1-git-send-email-clg@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH for-2.9 29/30] aspeed/scu: add a aspeed_scu_get_clk() helper List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org, Andrew Jeffery , Marcin Krzeminski , Peter Crosthwaite , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= The clock frequency is defined in the HW STRAP1 register of the SCU device. Signed-off-by: C=C3=A9dric Le Goater Reviewed-by: Joel Stanley --- hw/misc/aspeed_scu.c | 12 ++++++++++++ include/hw/misc/aspeed_scu.h | 1 + 2 files changed, 13 insertions(+) diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c index 95022d3607ad..351b8f79aca0 100644 --- a/hw/misc/aspeed_scu.c +++ b/hw/misc/aspeed_scu.c @@ -268,6 +268,18 @@ bool is_supported_silicon_rev(uint32_t silicon_rev) return false; } =20 +#define ASPEED_PLL_25MHZ 25000000 +#define ASPEED_PLL_24MHZ 24000000 +#define ASPEED_PLL_12MHZ 12000000 + +uint32_t aspeed_scu_get_clk(AspeedSCUState *scu) +{ + if (scu->hw_strap1 & AST2400_CLK_25M_IN) + return ASPEED_PLL_25MHZ; + else + return ASPEED_PLL_24MHZ; +} + static void aspeed_scu_realize(DeviceState *dev, Error **errp) { SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h index bd4ac013f997..067f9f01819d 100644 --- a/include/hw/misc/aspeed_scu.h +++ b/include/hw/misc/aspeed_scu.h @@ -37,6 +37,7 @@ typedef struct AspeedSCUState { #define AST2500_A1_SILICON_REV 0x04010303U =20 extern bool is_supported_silicon_rev(uint32_t silicon_rev); +extern uint32_t aspeed_scu_get_clk(AspeedSCUState *scu); =20 /* * Extracted from Aspeed SDK v00.03.21. Fixes and extra definitions --=20 2.7.4