[Qemu-devel] [PATCH 0/2] target-arm aarch64 big-endian fixes

[Qemu-devel] [PATCH 0/2] target-arm aarch64 big-endian fixes

[Richard Henderson]

I ran Alex's risu tests on an s390x host, and ran into two
problems not related to the s390 backend.


r~


Richard Henderson (2):
  target-arm: Fix aarch64 disas_ldst_single_struct
  target-arm: Fix aarch64 vec_reg_offset

 target-arm/translate-a64.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

-- 
2.7.4

[Qemu-devel] [PATCH 1/2] target-arm: Fix aarch64 vec_reg_offset

[Richard Henderson]

Since CPUARMState.vfp.regs is not 16 byte aligned, the ^ 8 fixup used
for a big-endian host doesn't do what's intended.  Fix this by adding
in the vfp.regs offset after computing the inter-register offset.

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 target-arm/translate-a64.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 6dc27a6..ef7601b 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -527,7 +527,7 @@ static inline void assert_fp_access_checked(DisasContext *s)
 static inline int vec_reg_offset(DisasContext *s, int regno,
                                  int element, TCGMemOp size)
 {
-    int offs = offsetof(CPUARMState, vfp.regs[regno * 2]);
+    int offs = 0;
 #ifdef HOST_WORDS_BIGENDIAN
     /* This is complicated slightly because vfp.regs[2n] is
      * still the low half and  vfp.regs[2n+1] the high half
@@ -540,6 +540,7 @@ static inline int vec_reg_offset(DisasContext *s, int regno,
 #else
     offs += element * (1 << size);
 #endif
+    offs += offsetof(CPUARMState, vfp.regs[regno * 2]);
     assert_fp_access_checked(s);
     return offs;
 }
-- 
2.7.4

[Qemu-devel] [PATCH 2/2] target-arm: Fix aarch64 disas_ldst_single_struct

[Richard Henderson]

We add s->be_data within do_vec_ld/st.  Adding it here means that
we have the wrong bits set in SIZE for a big-endian host, leading
to g_assert_not_reached in write_vec_element and read_vec_element.

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 target-arm/translate-a64.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index ef7601b..f673d93 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -2830,9 +2830,9 @@ static void disas_ldst_single_struct(DisasContext *s, uint32_t insn)
         } else {
             /* Load/store one element per register */
             if (is_load) {
-                do_vec_ld(s, rt, index, tcg_addr, s->be_data + scale);
+                do_vec_ld(s, rt, index, tcg_addr, scale);
             } else {
-                do_vec_st(s, rt, index, tcg_addr, s->be_data + scale);
+                do_vec_st(s, rt, index, tcg_addr, scale);
             }
         }
         tcg_gen_addi_i64(tcg_addr, tcg_addr, ebytes);
-- 
2.7.4

Re: [Qemu-devel] [PATCH 0/2] target-arm aarch64 big-endian fixes

[Peter Maydell]

On 7 December 2016 at 04:30, Richard Henderson <rth@twiddle.net> wrote:
> I ran Alex's risu tests on an s390x host, and ran into two
> problems not related to the s390 backend.
>
>
> r~
>
>
> Richard Henderson (2):
>   target-arm: Fix aarch64 disas_ldst_single_struct
>   target-arm: Fix aarch64 vec_reg_offset
>
>  target-arm/translate-a64.c | 7 ++++---
>  1 file changed, 4 insertions(+), 3 deletions(-)



Applied to target-arm.next for 2.9, thanks.

-- PMM