From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-arm@nongnu.org, qemu-devel@nongnu.org
Cc: patches@linaro.org,
"Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
Christoffer Dall <christoffer.dall@linaro.org>,
Andrew Jones <drjones@redhat.com>
Subject: [Qemu-devel] [PATCH 08/23] hw/intc/arm_gicv3: Add external IRQ lines for VIRQ and VFIQ
Date: Tue, 13 Dec 2016 10:36:09 +0000 [thread overview]
Message-ID: <1481625384-15077-9-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1481625384-15077-1-git-send-email-peter.maydell@linaro.org>
Augment the GICv3's QOM device interface by adding two
new sets of sysbus IRQ lines, to signal VIRQ and VFIQ to
each CPU.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/intc/arm_gicv3_common.h | 2 ++
hw/intc/arm_gicv3_common.c | 6 ++++++
2 files changed, 8 insertions(+)
diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3_common.h
index 341a311..beb2c77 100644
--- a/include/hw/intc/arm_gicv3_common.h
+++ b/include/hw/intc/arm_gicv3_common.h
@@ -145,6 +145,8 @@ struct GICv3CPUState {
CPUState *cpu;
qemu_irq parent_irq;
qemu_irq parent_fiq;
+ qemu_irq parent_virq;
+ qemu_irq parent_vfiq;
/* Redistributor */
uint32_t level; /* Current IRQ level */
diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c
index 0f8c4b8..9bb8d01 100644
--- a/hw/intc/arm_gicv3_common.c
+++ b/hw/intc/arm_gicv3_common.c
@@ -126,6 +126,12 @@ void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler,
for (i = 0; i < s->num_cpu; i++) {
sysbus_init_irq(sbd, &s->cpu[i].parent_fiq);
}
+ for (i = 0; i < s->num_cpu; i++) {
+ sysbus_init_irq(sbd, &s->cpu[i].parent_virq);
+ }
+ for (i = 0; i < s->num_cpu; i++) {
+ sysbus_init_irq(sbd, &s->cpu[i].parent_vfiq);
+ }
memory_region_init_io(&s->iomem_dist, OBJECT(s), ops, s,
"gicv3_dist", 0x10000);
--
2.7.4
next prev parent reply other threads:[~2016-12-13 10:37 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-12-13 10:36 [Qemu-devel] [PATCH 00/23] arm: Add virtualization to GICv3, and enable EL2 on 64-bit CPUs Peter Maydell
2016-12-13 10:36 ` [Qemu-devel] [PATCH 01/23] target-arm: Log AArch64 exception returns Peter Maydell
2016-12-19 21:51 ` Alistair Francis
2016-12-20 15:31 ` Andrew Jones
2016-12-27 15:13 ` Peter Maydell
2016-12-13 10:36 ` [Qemu-devel] [PATCH 02/23] hw/intc/arm_gicv3: Remove incorrect usage of fieldoffset Peter Maydell
2016-12-13 10:36 ` [Qemu-devel] [PATCH 03/23] hw/intc/arm_gicv3: Don't signal Pending+Active interrupts to CPU Peter Maydell
2016-12-13 10:36 ` [Qemu-devel] [PATCH 04/23] hw/arm/virt: add 2.9 machine type Peter Maydell
2016-12-13 10:36 ` [Qemu-devel] [PATCH 05/23] hw/arm/virt: Merge VirtBoardInfo and VirtMachineState Peter Maydell
2016-12-13 10:36 ` [Qemu-devel] [PATCH 06/23] hw/arm/virt: Rename 'vbi' variables to 'vms' Peter Maydell
2016-12-20 15:46 ` Andrew Jones
2016-12-13 10:36 ` [Qemu-devel] [PATCH 07/23] hw/arm/virt: Don't incorrectly claim architectural timer to be edge-triggered Peter Maydell
2016-12-13 10:36 ` Peter Maydell [this message]
2016-12-13 10:36 ` [Qemu-devel] [PATCH 09/23] hw/intc/arm_gic: Add external IRQ lines for VIRQ and VFIQ Peter Maydell
2016-12-19 21:54 ` Alistair Francis
2016-12-13 10:36 ` [Qemu-devel] [PATCH 10/23] target-arm: Expose output GPIO line for VCPU maintenance interrupt Peter Maydell
2016-12-13 12:37 ` Edgar E. Iglesias
2016-12-13 10:36 ` [Qemu-devel] [PATCH 11/23] hw/arm/virt: Wire VIRQ, VFIQ, maintenance irq lines from GIC to CPU Peter Maydell
2016-12-13 10:36 ` [Qemu-devel] [PATCH 12/23] target-arm: Add ARMCPU fields for GIC CPU i/f config Peter Maydell
2016-12-13 10:36 ` [Qemu-devel] [PATCH 13/23] hw/intc/gicv3: Add defines for ICH system register fields Peter Maydell
2016-12-13 10:36 ` [Qemu-devel] [PATCH 14/23] hw/intc/gicv3: Add data fields for virtualization support Peter Maydell
2016-12-13 10:36 ` [Qemu-devel] [PATCH 15/23] hw/intc/arm_gicv3: Add accessors for ICH_ system registers Peter Maydell
2016-12-13 10:36 ` [Qemu-devel] [PATCH 16/23] hw/intc/arm_gicv3: Implement ICV_ registers which are just accessors Peter Maydell
2016-12-13 10:36 ` [Qemu-devel] [PATCH 17/23] hw/intc/arm_gicv3: Implement ICV_ HPPIR, DIR and RPR registers Peter Maydell
2016-12-13 10:36 ` [Qemu-devel] [PATCH 18/23] hw/intc/arm_gicv3: Implement ICV_ registers EOIR and IAR Peter Maydell
2016-12-13 10:36 ` [Qemu-devel] [PATCH 19/23] hw/intc/arm_gicv3: Implement gicv3_cpuif_virt_update() Peter Maydell
2016-12-13 10:36 ` [Qemu-devel] [PATCH 20/23] hw/intc/arm_gicv3: Implement EL2 traps for CPU i/f regs Peter Maydell
2016-12-13 10:36 ` [Qemu-devel] [PATCH 21/23] hw/arm/virt: Support using SMC for PSCI Peter Maydell
2016-12-13 12:36 ` Edgar E. Iglesias
2016-12-28 13:14 ` Andrew Jones
2016-12-13 10:36 ` [Qemu-devel] [PATCH 22/23] target-arm: Enable EL2 feature bit on A53 and A57 Peter Maydell
2016-12-13 16:11 ` Edgar E. Iglesias
2016-12-19 22:04 ` Alistair Francis
2016-12-20 13:32 ` Peter Maydell
2016-12-20 17:46 ` Alistair Francis
2016-12-28 13:14 ` Andrew Jones
2016-12-13 10:36 ` [Qemu-devel] [PATCH 23/23] hw/arm/virt: Add board property to enable EL2 Peter Maydell
2016-12-28 13:14 ` Andrew Jones
2017-01-17 22:15 ` Alistair Francis
2016-12-13 21:16 ` [Qemu-devel] [PATCH 00/23] arm: Add virtualization to GICv3, and enable EL2 on 64-bit CPUs Andrew Jones
2016-12-14 10:18 ` Peter Maydell
2017-01-09 15:08 ` Peter Maydell
2016-12-16 21:42 ` Andrew Jones
2016-12-19 22:20 ` Alistair Francis
2017-01-09 15:57 ` Peter Maydell
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