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Violators will be prosecuted for from ; Wed, 14 Dec 2016 19:46:48 -0500 From: Michael Roth Date: Wed, 14 Dec 2016 18:43:58 -0600 In-Reply-To: <1481762701-4587-1-git-send-email-mdroth@linux.vnet.ibm.com> References: <1481762701-4587-1-git-send-email-mdroth@linux.vnet.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Message-Id: <1481762701-4587-5-git-send-email-mdroth@linux.vnet.ibm.com> Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH 04/67] ppc: Check the availability of transactional memory List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: qemu-stable@nongnu.org, Thomas Huth , David Gibson From: Thomas Huth KVM-PR currently does not support transactional memory, and the implementation in TCG is just a fake. We should not announce TM support in the ibm,pa-features property when running on such a system, so disable it by default and only enable it if the KVM implementation supports it (i.e. recent versions of KVM-HV). These changes are based on some earlier work from Anton Blanchard (thanks!). Signed-off-by: Thomas Huth Reviewed-by: C=C3=A9dric Le Goater Signed-off-by: David Gibson (cherry picked from commit bac3bf287ab60e264b636f5f00c116a19b655762) --- hw/ppc/spapr.c | 5 ++++- target-ppc/kvm.c | 7 +++++++ target-ppc/kvm_ppc.h | 6 ++++++ 3 files changed, 17 insertions(+), 1 deletion(-) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 9f0d99b..82723d1 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -603,7 +603,7 @@ static void spapr_populate_pa_features(CPUPPCState *e= nv, void *fdt, int offset) 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, - 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; + 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; uint8_t *pa_features; size_t pa_size; =20 @@ -632,6 +632,9 @@ static void spapr_populate_pa_features(CPUPPCState *e= nv, void *fdt, int offset) */ pa_features[3] |=3D 0x20; } + if (kvmppc_has_cap_htm() && pa_size > 24) { + pa_features[24] |=3D 0x80; /* Transactional memory support */ + } =20 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_si= ze))); } diff --git a/target-ppc/kvm.c b/target-ppc/kvm.c index dcb68b9..f26a141 100644 --- a/target-ppc/kvm.c +++ b/target-ppc/kvm.c @@ -79,6 +79,7 @@ static int cap_ppc_watchdog; static int cap_papr; static int cap_htab_fd; static int cap_fixup_hcalls; +static int cap_htm; /* Hardware transactional memory support= */ =20 static uint32_t debug_inst_opcode; =20 @@ -121,6 +122,7 @@ int kvm_arch_init(MachineState *ms, KVMState *s) * only activated after this by kvmppc_set_papr() */ cap_htab_fd =3D kvm_check_extension(s, KVM_CAP_PPC_HTAB_FD); cap_fixup_hcalls =3D kvm_check_extension(s, KVM_CAP_PPC_FIXUP_HCALL)= ; + cap_htm =3D kvm_vm_check_extension(s, KVM_CAP_PPC_HTM); =20 if (!cap_interrupt_level) { fprintf(stderr, "KVM: Couldn't find level irq capability. Expect= the " @@ -2339,6 +2341,11 @@ bool kvmppc_has_cap_fixup_hcalls(void) return cap_fixup_hcalls; } =20 +bool kvmppc_has_cap_htm(void) +{ + return cap_htm; +} + static PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc) { ObjectClass *oc =3D OBJECT_CLASS(pcc); diff --git a/target-ppc/kvm_ppc.h b/target-ppc/kvm_ppc.h index 5461d10..e45c815 100644 --- a/target-ppc/kvm_ppc.h +++ b/target-ppc/kvm_ppc.h @@ -54,6 +54,7 @@ void kvmppc_hash64_free_pteg(uint64_t token); void kvmppc_hash64_write_pte(CPUPPCState *env, target_ulong pte_index, target_ulong pte0, target_ulong pte1); bool kvmppc_has_cap_fixup_hcalls(void); +bool kvmppc_has_cap_htm(void); int kvmppc_enable_hwrng(void); int kvmppc_put_books_sregs(PowerPCCPU *cpu); PowerPCCPUClass *kvm_ppc_get_host_cpu_class(void); @@ -244,6 +245,11 @@ static inline bool kvmppc_has_cap_fixup_hcalls(void) abort(); } =20 +static inline bool kvmppc_has_cap_htm(void) +{ + return false; +} + static inline int kvmppc_enable_hwrng(void) { return -1; --=20 1.9.1