[Qemu-devel] [kvm-unit-tests PATCH 0/8] VT-d ioapic irq test

[Qemu-devel] [kvm-unit-tests PATCH 0/8] VT-d ioapic irq test

[Peter Xu]

The previous vt-d unittest series only contains the very basic tests.
Let's enlarge it step by step.

This series expanded it with IOAPIC irq test.

Peter Xu (8):
  pci: introduce pci_intx_line()
  pci: introduce pci_msi_set_enable()
  lib/asm-generic: add atomic.h
  x86: ioapic: generalize trigger mode
  intel-iommu: add report prefixes
  intel-iommu: use atomic ops for irte index alloc
  intel-iommu: allow setup trigger mode for irte
  intel-iommu: add ioapic irq test

 lib/asm-generic/atomic.h | 21 ++++++++++++++++++
 lib/pci.c                | 24 ++++++++++++++++++--
 lib/pci.h                |  2 ++
 lib/x86/apic.h           |  6 +++++
 lib/x86/atomic.h         |  2 ++
 lib/x86/intel-iommu.c    | 58 +++++++++++++++++++++++++++++++++++++++++++-----
 lib/x86/intel-iommu.h    |  3 +++
 x86/intel-iommu.c        | 50 ++++++++++++++++++++++++++++++++++++-----
 x86/ioapic.c             | 34 +++++++++++++---------------
 9 files changed, 169 insertions(+), 31 deletions(-)
 create mode 100644 lib/asm-generic/atomic.h

-- 
2.7.4

[Qemu-devel] [kvm-unit-tests PATCH 1/8] pci: introduce pci_intx_line()

[Peter Xu]

To fetch INTx irq line number.

Signed-off-by: Peter Xu <peterx@redhat.com>
---
 lib/pci.c | 5 +++++
 lib/pci.h | 1 +
 2 files changed, 6 insertions(+)

diff --git a/lib/pci.c b/lib/pci.c
index 6416191..a7cfacb 100644
--- a/lib/pci.c
+++ b/lib/pci.c
@@ -327,6 +327,11 @@ void pci_scan_bars(struct pci_dev *dev)
 	}
 }
 
+uint8_t pci_intx_line(struct pci_dev *dev)
+{
+	return pci_config_readb(dev->bdf, PCI_INTERRUPT_LINE);
+}
+
 void pci_enable_defaults(struct pci_dev *dev)
 {
 	pci_scan_bars(dev);
diff --git a/lib/pci.h b/lib/pci.h
index e71a05d..df86951 100644
--- a/lib/pci.h
+++ b/lib/pci.h
@@ -64,6 +64,7 @@ extern bool pci_bar_is_memory(struct pci_dev *dev, int bar_num);
 extern bool pci_bar_is_valid(struct pci_dev *dev, int bar_num);
 extern void pci_bar_print(struct pci_dev *dev, int bar_num);
 extern void pci_dev_print_id(pcidevaddr_t dev);
+extern uint8_t pci_intx_line(struct pci_dev *dev);
 
 extern int pci_testdev(void);
 
-- 
2.7.4

[Qemu-devel] [kvm-unit-tests PATCH 2/8] pci: introduce pci_msi_set_enable()

[Peter Xu]

Generalize this function out of pci_setup_msi(), then it can be further
used to enable INTx (or, disable MSI).

Signed-off-by: Peter Xu <peterx@redhat.com>
---
 lib/pci.c | 19 +++++++++++++++++--
 lib/pci.h |  1 +
 2 files changed, 18 insertions(+), 2 deletions(-)

diff --git a/lib/pci.c b/lib/pci.c
index a7cfacb..5062036 100644
--- a/lib/pci.c
+++ b/lib/pci.c
@@ -39,6 +39,22 @@ void pci_cap_walk(struct pci_dev *dev)
 	}
 }
 
+void pci_msi_set_enable(struct pci_dev *dev, bool enabled)
+{
+	uint16_t msi_control;
+	uint16_t offset;
+
+	offset = dev->msi_offset;
+	msi_control = pci_config_readw(dev->bdf, offset + PCI_MSI_FLAGS);
+
+	if (enabled)
+		msi_control |= PCI_MSI_FLAGS_ENABLE;
+	else
+		msi_control &= ~PCI_MSI_FLAGS_ENABLE;
+
+	pci_config_writew(dev->bdf, offset + PCI_MSI_FLAGS, msi_control);
+}
+
 bool pci_setup_msi(struct pci_dev *dev, uint64_t msi_addr, uint32_t msi_data)
 {
 	uint16_t msi_control;
@@ -69,8 +85,7 @@ bool pci_setup_msi(struct pci_dev *dev, uint64_t msi_addr, uint32_t msi_data)
 	}
 	printf("addr=0x%lx, data=0x%x\n", msi_addr, msi_data);
 
-	msi_control |= PCI_MSI_FLAGS_ENABLE;
-	pci_config_writew(addr, offset + PCI_MSI_FLAGS, msi_control);
+	pci_msi_set_enable(dev, true);
 
 	return true;
 }
diff --git a/lib/pci.h b/lib/pci.h
index df86951..0815754 100644
--- a/lib/pci.h
+++ b/lib/pci.h
@@ -65,6 +65,7 @@ extern bool pci_bar_is_valid(struct pci_dev *dev, int bar_num);
 extern void pci_bar_print(struct pci_dev *dev, int bar_num);
 extern void pci_dev_print_id(pcidevaddr_t dev);
 extern uint8_t pci_intx_line(struct pci_dev *dev);
+void pci_msi_set_enable(struct pci_dev *dev, bool enabled);
 
 extern int pci_testdev(void);
 
-- 
2.7.4

[Qemu-devel] [kvm-unit-tests PATCH 3/8] lib/asm-generic: add atomic.h

[Peter Xu]

Provide some gcc-builtin atomic ops.

Signed-off-by: Peter Xu <peterx@redhat.com>
---
 lib/asm-generic/atomic.h | 21 +++++++++++++++++++++
 lib/x86/atomic.h         |  2 ++
 2 files changed, 23 insertions(+)
 create mode 100644 lib/asm-generic/atomic.h

diff --git a/lib/asm-generic/atomic.h b/lib/asm-generic/atomic.h
new file mode 100644
index 0000000..26b645a
--- /dev/null
+++ b/lib/asm-generic/atomic.h
@@ -0,0 +1,21 @@
+#ifndef __ASM_GENERIC_ATOMIC_H__
+#define __ASM_GENERIC_ATOMIC_H__
+
+/* From QEMU include/qemu/atomic.h */
+#define atomic_fetch_inc(ptr)  __sync_fetch_and_add(ptr, 1)
+#define atomic_fetch_dec(ptr)  __sync_fetch_and_add(ptr, -1)
+#define atomic_fetch_add(ptr, n) __sync_fetch_and_add(ptr, n)
+#define atomic_fetch_sub(ptr, n) __sync_fetch_and_sub(ptr, n)
+#define atomic_fetch_and(ptr, n) __sync_fetch_and_and(ptr, n)
+#define atomic_fetch_or(ptr, n) __sync_fetch_and_or(ptr, n)
+#define atomic_fetch_xor(ptr, n) __sync_fetch_and_xor(ptr, n)
+
+#define atomic_inc_fetch(ptr)  __sync_add_and_fetch(ptr, 1)
+#define atomic_dec_fetch(ptr)  __sync_add_and_fetch(ptr, -1)
+#define atomic_add_fetch(ptr, n) __sync_add_and_fetch(ptr, n)
+#define atomic_sub_fetch(ptr, n) __sync_sub_and_fetch(ptr, n)
+#define atomic_and_fetch(ptr, n) __sync_and_and_fetch(ptr, n)
+#define atomic_or_fetch(ptr, n) __sync_or_and_fetch(ptr, n)
+#define atomic_xor_fetch(ptr, n) __sync_xor_and_fetch(ptr, n)
+
+#endif
diff --git a/lib/x86/atomic.h b/lib/x86/atomic.h
index de2f033..c9ce489 100644
--- a/lib/x86/atomic.h
+++ b/lib/x86/atomic.h
@@ -1,6 +1,8 @@
 #ifndef __ATOMIC_H
 #define __ATOMIC_H
 
+#include "asm-generic/atomic.h"
+
 typedef struct {
 	volatile int counter;
 } atomic_t;
-- 
2.7.4

[Qemu-devel] [kvm-unit-tests PATCH 4/8] x86: ioapic: generalize trigger mode

[Peter Xu]

Move it out of x86/ioapic.c since it can be further re-used. Also,
renaming into TRIGGER_*.

Signed-off-by: Peter Xu <peterx@redhat.com>
---
 lib/x86/apic.h |  6 ++++++
 x86/ioapic.c   | 34 ++++++++++++++++------------------
 2 files changed, 22 insertions(+), 18 deletions(-)

diff --git a/lib/x86/apic.h b/lib/x86/apic.h
index 192268c..699102c 100644
--- a/lib/x86/apic.h
+++ b/lib/x86/apic.h
@@ -18,6 +18,12 @@ typedef struct {
     uint8_t dest_id;
 } ioapic_redir_entry_t;
 
+typedef enum trigger_mode {
+	TRIGGER_EDGE = 0,
+	TRIGGER_LEVEL,
+	TRIGGER_MAX,
+} trigger_mode_t;
+
 void mask_pic_interrupts(void);
 
 void eoi(void);
diff --git a/x86/ioapic.c b/x86/ioapic.c
index 314c9bb..e5cc259 100644
--- a/x86/ioapic.c
+++ b/x86/ioapic.c
@@ -5,10 +5,8 @@
 #include "desc.h"
 #include "isr.h"
 
-#define EDGE_TRIGGERED 0
-#define LEVEL_TRIGGERED 1
-
-static void set_ioapic_redir(unsigned line, unsigned vec, unsigned trig_mode)
+static void set_ioapic_redir(unsigned line, unsigned vec,
+			     trigger_mode_t trig_mode)
 {
 	ioapic_redir_entry_t e = {
 		.vector = vec,
@@ -89,7 +87,7 @@ static void ioapic_isr_76(isr_regs_t *regs)
 static void test_ioapic_edge_intr(void)
 {
 	handle_irq(0x76, ioapic_isr_76);
-	set_ioapic_redir(0x0e, 0x76, EDGE_TRIGGERED);
+	set_ioapic_redir(0x0e, 0x76, TRIGGER_EDGE);
 	toggle_irq_line(0x0e);
 	asm volatile ("nop");
 	report("edge triggered intr", g_isr_76 == 1);
@@ -107,7 +105,7 @@ static void ioapic_isr_77(isr_regs_t *regs)
 static void test_ioapic_level_intr(void)
 {
 	handle_irq(0x77, ioapic_isr_77);
-	set_ioapic_redir(0x0e, 0x77, LEVEL_TRIGGERED);
+	set_ioapic_redir(0x0e, 0x77, TRIGGER_LEVEL);
 	set_irq_line(0x0e, 1);
 	asm volatile ("nop");
 	report("level triggered intr", g_isr_77 == 1);
@@ -136,8 +134,8 @@ static void test_ioapic_simultaneous(void)
 {
 	handle_irq(0x78, ioapic_isr_78);
 	handle_irq(0x66, ioapic_isr_66);
-	set_ioapic_redir(0x0e, 0x78, EDGE_TRIGGERED);
-	set_ioapic_redir(0x0f, 0x66, EDGE_TRIGGERED);
+	set_ioapic_redir(0x0e, 0x78, TRIGGER_EDGE);
+	set_ioapic_redir(0x0f, 0x66, TRIGGER_EDGE);
 	irq_disable();
 	toggle_irq_line(0x0f);
 	toggle_irq_line(0x0e);
@@ -161,7 +159,7 @@ static void test_ioapic_edge_tmr(bool expected_tmr_before)
 	int tmr_before;
 
 	handle_irq(0x79, ioapic_isr_79);
-	set_ioapic_redir(0x0e, 0x79, EDGE_TRIGGERED);
+	set_ioapic_redir(0x0e, 0x79, TRIGGER_EDGE);
 	tmr_before = apic_read_bit(APIC_TMR, 0x79);
 	toggle_irq_line(0x0e);
 	asm volatile ("nop");
@@ -175,7 +173,7 @@ static void test_ioapic_level_tmr(bool expected_tmr_before)
 	int tmr_before;
 
 	handle_irq(0x79, ioapic_isr_79);
-	set_ioapic_redir(0x0e, 0x79, LEVEL_TRIGGERED);
+	set_ioapic_redir(0x0e, 0x79, TRIGGER_LEVEL);
 	tmr_before = apic_read_bit(APIC_TMR, 0x79);
 	set_irq_line(0x0e, 1);
 	asm volatile ("nop");
@@ -206,7 +204,7 @@ static void test_ioapic_edge_tmr_smp(bool expected_tmr_before)
 
 	g_tmr_79 = -1;
 	handle_irq(0x79, ioapic_isr_79);
-	set_ioapic_redir(0x0e, 0x79, EDGE_TRIGGERED);
+	set_ioapic_redir(0x0e, 0x79, TRIGGER_EDGE);
 	tmr_before = apic_read_bit(APIC_TMR, 0x79);
 	on_cpu_async(1, toggle_irq_line_0x0e, 0);
 	i = 0;
@@ -231,7 +229,7 @@ static void test_ioapic_level_tmr_smp(bool expected_tmr_before)
 
 	g_tmr_79 = -1;
 	handle_irq(0x79, ioapic_isr_79);
-	set_ioapic_redir(0x0e, 0x79, LEVEL_TRIGGERED);
+	set_ioapic_redir(0x0e, 0x79, TRIGGER_LEVEL);
 	tmr_before = apic_read_bit(APIC_TMR, 0x79);
 	on_cpu_async(1, set_irq_line_0x0e, 0);
 	i = 0;
@@ -258,7 +256,7 @@ static void ioapic_isr_98(isr_regs_t *regs)
 static void test_ioapic_level_coalesce(void)
 {
 	handle_irq(0x98, ioapic_isr_98);
-	set_ioapic_redir(0x0e, 0x98, LEVEL_TRIGGERED);
+	set_ioapic_redir(0x0e, 0x98, TRIGGER_LEVEL);
 	set_irq_line(0x0e, 1);
 	asm volatile ("nop");
 	report("coalesce simultaneous level interrupts", g_isr_98 == 1);
@@ -276,7 +274,7 @@ static void ioapic_isr_99(isr_regs_t *regs)
 static void test_ioapic_level_sequential(void)
 {
 	handle_irq(0x99, ioapic_isr_99);
-	set_ioapic_redir(0x0e, 0x99, LEVEL_TRIGGERED);
+	set_ioapic_redir(0x0e, 0x99, TRIGGER_LEVEL);
 	set_irq_line(0x0e, 1);
 	set_irq_line(0x0e, 1);
 	asm volatile ("nop");
@@ -298,7 +296,7 @@ static void test_ioapic_level_retrigger(void)
 	int i;
 
 	handle_irq(0x9a, ioapic_isr_9a);
-	set_ioapic_redir(0x0e, 0x9a, LEVEL_TRIGGERED);
+	set_ioapic_redir(0x0e, 0x9a, TRIGGER_LEVEL);
 
 	asm volatile ("cli");
 	set_irq_line(0x0e, 1);
@@ -327,7 +325,7 @@ static void ioapic_isr_81(isr_regs_t *regs)
 static void test_ioapic_edge_mask(void)
 {
 	handle_irq(0x81, ioapic_isr_81);
-	set_ioapic_redir(0x0e, 0x81, EDGE_TRIGGERED);
+	set_ioapic_redir(0x0e, 0x81, TRIGGER_EDGE);
 
 	set_mask(0x0e, true);
 	set_irq_line(0x0e, 1);
@@ -355,7 +353,7 @@ static void ioapic_isr_82(isr_regs_t *regs)
 static void test_ioapic_level_mask(void)
 {
 	handle_irq(0x82, ioapic_isr_82);
-	set_ioapic_redir(0x0e, 0x82, LEVEL_TRIGGERED);
+	set_ioapic_redir(0x0e, 0x82, TRIGGER_LEVEL);
 
 	set_mask(0x0e, true);
 	set_irq_line(0x0e, 1);
@@ -381,7 +379,7 @@ static void ioapic_isr_83(isr_regs_t *regs)
 static void test_ioapic_level_retrigger_mask(void)
 {
 	handle_irq(0x83, ioapic_isr_83);
-	set_ioapic_redir(0x0e, 0x83, LEVEL_TRIGGERED);
+	set_ioapic_redir(0x0e, 0x83, TRIGGER_LEVEL);
 
 	set_irq_line(0x0e, 1);
 	asm volatile ("nop");
-- 
2.7.4

[Qemu-devel] [kvm-unit-tests PATCH 5/8] intel-iommu: add report prefixes

[Peter Xu]

Signed-off-by: Peter Xu <peterx@redhat.com>
---
 x86/intel-iommu.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/x86/intel-iommu.c b/x86/intel-iommu.c
index 753f90e..59171a1 100644
--- a/x86/intel-iommu.c
+++ b/x86/intel-iommu.c
@@ -21,6 +21,8 @@ void vtd_test_dmar(struct pci_edu_dev *dev)
 {
 	void *page = alloc_page();
 
+	report_prefix_push("vtd_dmar");
+
 #define DMA_TEST_WORD (0x12345678)
 	/* Modify the first 4 bytes of the page */
 	*(uint32_t *)page = DMA_TEST_WORD;
@@ -51,6 +53,8 @@ void vtd_test_dmar(struct pci_edu_dev *dev)
 	report(VTD_TEST_DMAR_4B, *((uint32_t *)page + 1) == DMA_TEST_WORD);
 
 	free_page(page);
+
+	report_prefix_pop();
 }
 
 static volatile bool edu_intr_recved;
@@ -64,6 +68,8 @@ static void edu_isr(isr_regs_t *regs)
 static void vtd_test_ir(struct pci_edu_dev *dev)
 {
 #define VTD_TEST_VECTOR (0xee)
+	report_prefix_push("vtd_ir");
+
 	/*
 	 * Setup EDU PCI device MSI, using interrupt remapping. By
 	 * default, EDU device is using INTx.
@@ -88,6 +94,8 @@ static void vtd_test_ir(struct pci_edu_dev *dev)
 
 	/* We are good as long as we reach here */
 	report(VTD_TEST_IR_MSI, true);
+
+	report_prefix_pop();
 }
 
 int main(int argc, char *argv[])
@@ -96,6 +104,8 @@ int main(int argc, char *argv[])
 
 	vtd_init();
 
+	report_prefix_push("vtd_init");
+
 	report("fault status check", vtd_readl(DMAR_FSTS_REG) == 0);
 	report("QI enablement", vtd_readl(DMAR_GSTS_REG) & VTD_GCMD_QI);
 	report("DMAR table setup", vtd_readl(DMAR_GSTS_REG) & VTD_GCMD_ROOT);
@@ -106,6 +116,8 @@ int main(int argc, char *argv[])
 	       vtd_readq(DMAR_CAP_REG) & VTD_CAP_SAGAW);
 	report("DMAR support huge pages", vtd_readq(DMAR_CAP_REG) & VTD_CAP_SLLPS);
 
+	report_prefix_pop();
+
 	if (!edu_init(&dev)) {
 		printf("Please specify \"-device edu\" to do "
 		       "further IOMMU tests.\n");
-- 
2.7.4

[Qemu-devel] [kvm-unit-tests PATCH 6/8] intel-iommu: use atomic ops for irte index alloc

[Peter Xu]

To allow concurrent allocation of irte index. Meanwhile, move the IRTE
setup debug line into the alloc since vtd_setup_msi() might not be the
only one to dump this info in the future.

Signed-off-by: Peter Xu <peterx@redhat.com>
---
 lib/x86/intel-iommu.c | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/lib/x86/intel-iommu.c b/lib/x86/intel-iommu.c
index 20b9240..a3ce678 100644
--- a/lib/x86/intel-iommu.c
+++ b/lib/x86/intel-iommu.c
@@ -13,6 +13,7 @@
 #include "intel-iommu.h"
 #include "libcflat.h"
 #include "pci.h"
+#include "atomic.h"
 
 /*
  * VT-d in QEMU currently only support 39 bits address width, which is
@@ -239,9 +240,13 @@ void vtd_map_range(uint16_t sid, iova_t iova, phys_addr_t pa, size_t size)
 
 static uint16_t vtd_intr_index_alloc(void)
 {
-	static int index_ctr = 0;
+	static volatile int index_ctr = 0;
+	int ctr;
+
 	assert(index_ctr < 65535);
-	return index_ctr++;
+	ctr = atomic_inc_fetch(&index_ctr);
+	printf("INTR: alloc IRTE index %d\n", ctr);
+	return ctr;
 }
 
 static void vtd_setup_irte(struct pci_dev *dev, vtd_irte_t *irte,
@@ -296,7 +301,6 @@ bool vtd_setup_msi(struct pci_dev *dev, int vector, int dest_id)
 	assert(sizeof(vtd_msi_addr_t) == 8);
 	assert(sizeof(vtd_msi_data_t) == 4);
 
-	printf("INTR: setup IRTE index %d\n", index);
 	vtd_setup_irte(dev, irte + index, vector, dest_id);
 
 	msi_addr.handle_15 = index >> 15 & 1;
-- 
2.7.4

[Qemu-devel] [kvm-unit-tests PATCH 7/8] intel-iommu: allow setup trigger mode for irte

[Peter Xu]

IOAPIC interrupts need this. Let's be prepared.

Signed-off-by: Peter Xu <peterx@redhat.com>
---
 lib/x86/intel-iommu.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/lib/x86/intel-iommu.c b/lib/x86/intel-iommu.c
index a3ce678..0585248 100644
--- a/lib/x86/intel-iommu.c
+++ b/lib/x86/intel-iommu.c
@@ -250,13 +250,13 @@ static uint16_t vtd_intr_index_alloc(void)
 }
 
 static void vtd_setup_irte(struct pci_dev *dev, vtd_irte_t *irte,
-			   int vector, int dest_id)
+			   int vector, int dest_id, trigger_mode_t trigger)
 {
 	assert(sizeof(vtd_irte_t) == 16);
 	memset(irte, 0, sizeof(*irte));
 	irte->fault_disable = 1;
 	irte->dest_mode = 0;	 /* physical */
-	irte->trigger_mode = 0;	 /* edge */
+	irte->trigger_mode = trigger;
 	irte->delivery_mode = 0; /* fixed */
 	irte->irte_mode = 0;	 /* remapped */
 	irte->vector = vector;
@@ -301,7 +301,9 @@ bool vtd_setup_msi(struct pci_dev *dev, int vector, int dest_id)
 	assert(sizeof(vtd_msi_addr_t) == 8);
 	assert(sizeof(vtd_msi_data_t) == 4);
 
-	vtd_setup_irte(dev, irte + index, vector, dest_id);
+	/* Use edge irq as default */
+	vtd_setup_irte(dev, irte + index, vector,
+		       dest_id, TRIGGER_EDGE);
 
 	msi_addr.handle_15 = index >> 15 & 1;
 	msi_addr.shv = 0;
-- 
2.7.4

[Qemu-devel] [kvm-unit-tests PATCH 8/8] intel-iommu: add ioapic irq test

[Peter Xu]

IOAPIC irqs are line-based irqs comparing to MSI ones (which are
memory-based). To make it complete, let's also test IOAPIC interrupts
in the IR testcase.

Signed-off-by: Peter Xu <peterx@redhat.com>
---
 lib/x86/intel-iommu.c | 40 ++++++++++++++++++++++++++++++++++++++++
 lib/x86/intel-iommu.h |  3 +++
 x86/intel-iommu.c     | 38 +++++++++++++++++++++++++++++++++-----
 3 files changed, 76 insertions(+), 5 deletions(-)

diff --git a/lib/x86/intel-iommu.c b/lib/x86/intel-iommu.c
index 0585248..1629920 100644
--- a/lib/x86/intel-iommu.c
+++ b/lib/x86/intel-iommu.c
@@ -284,6 +284,21 @@ struct vtd_msi_data {
 } __attribute__ ((packed));
 typedef struct vtd_msi_data vtd_msi_data_t;
 
+struct vtd_ioapic_entry {
+	uint64_t vector:8;
+	uint64_t __zeros:3;
+	uint64_t index_15:1;
+	uint64_t delivery_status:1;
+	uint64_t polarity:1;
+	uint64_t remote_irr:1;
+	uint64_t trigger_mode:1;
+	uint64_t mask:1;
+	uint64_t __zeros_2:31;
+	uint64_t interrupt_format:1;
+	uint64_t index_0_14:15;
+} __attribute__ ((packed));
+typedef struct vtd_ioapic_entry vtd_ioapic_entry_t;
+
 /**
  * vtd_setup_msi - setup MSI message for a device
  *
@@ -316,6 +331,31 @@ bool vtd_setup_msi(struct pci_dev *dev, int vector, int dest_id)
 			     *(uint32_t *)&msi_data);
 }
 
+void vtd_setup_ioapic_irq(struct pci_dev *dev, int vector,
+			  int dest_id, trigger_mode_t trigger)
+{
+	vtd_ioapic_entry_t entry = {};
+	vtd_irte_t *irte = phys_to_virt(vtd_ir_table());
+	ioapic_redir_entry_t *entry_2 = (ioapic_redir_entry_t *)&entry;
+	uint16_t index = vtd_intr_index_alloc();
+	uint8_t line;
+
+	assert(dev);
+	assert(sizeof(vtd_ioapic_entry_t) == 8);
+
+	vtd_setup_irte(dev, irte + index, vector,
+		       dest_id, trigger);
+
+	entry.vector = vector;
+	entry.trigger_mode = trigger;
+	entry.index_15 = (index >> 15) & 1;
+	entry.interrupt_format = 1;
+	entry.index_0_14 = index & 0x7fff;
+
+	line = pci_intx_line(dev);
+	ioapic_write_redir(line, *entry_2);
+}
+
 void vtd_init(void)
 {
 	setup_vm();
diff --git a/lib/x86/intel-iommu.h b/lib/x86/intel-iommu.h
index e3e956d..885be53 100644
--- a/lib/x86/intel-iommu.h
+++ b/lib/x86/intel-iommu.h
@@ -22,6 +22,7 @@
 #include "desc.h"
 #include "pci.h"
 #include "asm/io.h"
+#include "apic.h"
 
 #define Q35_HOST_BRIDGE_IOMMU_ADDR  0xfed90000ULL
 #define VTD_PAGE_SHIFT              PAGE_SHIFT
@@ -142,5 +143,7 @@ static inline uint64_t vtd_readq(unsigned int reg)
 void vtd_init(void);
 void vtd_map_range(uint16_t sid, phys_addr_t iova, phys_addr_t pa, size_t size);
 bool vtd_setup_msi(struct pci_dev *dev, int vector, int dest_id);
+void vtd_setup_ioapic_irq(struct pci_dev *dev, int vector,
+			  int dest_id, trigger_mode_t trigger);
 
 #endif
diff --git a/x86/intel-iommu.c b/x86/intel-iommu.c
index 59171a1..5a65232 100644
--- a/x86/intel-iommu.c
+++ b/x86/intel-iommu.c
@@ -16,6 +16,7 @@
 
 #define VTD_TEST_DMAR_4B ("DMAR 4B memcpy test")
 #define VTD_TEST_IR_MSI ("IR MSI")
+#define VTD_TEST_IR_IOAPIC ("IR IOAPIC")
 
 void vtd_test_dmar(struct pci_edu_dev *dev)
 {
@@ -67,22 +68,48 @@ static void edu_isr(isr_regs_t *regs)
 
 static void vtd_test_ir(struct pci_edu_dev *dev)
 {
-#define VTD_TEST_VECTOR (0xee)
+#define VTD_TEST_VECTOR_IOAPIC (0xed)
+#define VTD_TEST_VECTOR_MSI (0xee)
+	struct pci_dev *pci_dev = &dev->pci_dev;
+
 	report_prefix_push("vtd_ir");
 
+	irq_enable();
+
+	/* This will enable INTx */
+	pci_msi_set_enable(pci_dev, false);
+	vtd_setup_ioapic_irq(pci_dev, VTD_TEST_VECTOR_IOAPIC,
+			     0, TRIGGER_EDGE);
+	handle_irq(VTD_TEST_VECTOR_IOAPIC, edu_isr);
+
+	edu_intr_recved = false;
+	wmb();
+	/* Manually trigger INTR */
+	edu_reg_writel(dev, EDU_REG_INTR_RAISE, 1);
+
+	while (!edu_intr_recved)
+		cpu_relax();
+
+	/* Clear INTR bits */
+	edu_reg_writel(dev, EDU_REG_INTR_RAISE, 0);
+
+	/* We are good as long as we reach here */
+	report(VTD_TEST_IR_IOAPIC, edu_intr_recved == true);
+
 	/*
 	 * Setup EDU PCI device MSI, using interrupt remapping. By
 	 * default, EDU device is using INTx.
 	 */
-	if (!vtd_setup_msi(&dev->pci_dev, VTD_TEST_VECTOR, 0)) {
+	if (!vtd_setup_msi(pci_dev, VTD_TEST_VECTOR_MSI, 0)) {
 		printf("edu device does not support MSI, skip test\n");
 		report_skip(VTD_TEST_IR_MSI);
 		return;
 	}
 
-	handle_irq(VTD_TEST_VECTOR, edu_isr);
-	irq_enable();
+	handle_irq(VTD_TEST_VECTOR_MSI, edu_isr);
 
+	edu_intr_recved = false;
+	wmb();
 	/* Manually trigger INTR */
 	edu_reg_writel(dev, EDU_REG_INTR_RAISE, 1);
 
@@ -93,7 +120,7 @@ static void vtd_test_ir(struct pci_edu_dev *dev)
 	edu_reg_writel(dev, EDU_REG_INTR_RAISE, 0);
 
 	/* We are good as long as we reach here */
-	report(VTD_TEST_IR_MSI, true);
+	report(VTD_TEST_IR_MSI, edu_intr_recved == true);
 
 	report_prefix_pop();
 }
@@ -122,6 +149,7 @@ int main(int argc, char *argv[])
 		printf("Please specify \"-device edu\" to do "
 		       "further IOMMU tests.\n");
 		report_skip(VTD_TEST_DMAR_4B);
+		report_skip(VTD_TEST_IR_IOAPIC);
 		report_skip(VTD_TEST_IR_MSI);
 	} else {
 		vtd_test_dmar(&dev);
-- 
2.7.4

Re: [Qemu-devel] [kvm-unit-tests PATCH 0/8] VT-d ioapic irq test

[Paolo Bonzini]

On 30/12/2016 09:55, Peter Xu wrote:
> The previous vt-d unittest series only contains the very basic tests.
> Let's enlarge it step by step.
> 
> This series expanded it with IOAPIC irq test.
> 
> Peter Xu (8):
>   pci: introduce pci_intx_line()
>   pci: introduce pci_msi_set_enable()
>   lib/asm-generic: add atomic.h
>   x86: ioapic: generalize trigger mode
>   intel-iommu: add report prefixes
>   intel-iommu: use atomic ops for irte index alloc
>   intel-iommu: allow setup trigger mode for irte
>   intel-iommu: add ioapic irq test
> 
>  lib/asm-generic/atomic.h | 21 ++++++++++++++++++
>  lib/pci.c                | 24 ++++++++++++++++++--
>  lib/pci.h                |  2 ++
>  lib/x86/apic.h           |  6 +++++
>  lib/x86/atomic.h         |  2 ++
>  lib/x86/intel-iommu.c    | 58 +++++++++++++++++++++++++++++++++++++++++++-----
>  lib/x86/intel-iommu.h    |  3 +++
>  x86/intel-iommu.c        | 50 ++++++++++++++++++++++++++++++++++++-----
>  x86/ioapic.c             | 34 +++++++++++++---------------
>  9 files changed, 169 insertions(+), 31 deletions(-)
>  create mode 100644 lib/asm-generic/atomic.h
> 

Queued, thanks.

Paolo