* [Qemu-devel] [PATCH v2 1/4] prep: do not use global variable to access nvram
2017-01-05 21:56 [Qemu-devel] [PATCH v2 0/4] ppc: add a IBM 40p machine (RS/6000, PReP) Hervé Poussineau
@ 2017-01-05 21:56 ` Hervé Poussineau
2017-01-05 21:56 ` [Qemu-devel] [PATCH v2 2/4] prep: add PReP System I/O Hervé Poussineau
` (2 subsequent siblings)
3 siblings, 0 replies; 9+ messages in thread
From: Hervé Poussineau @ 2017-01-05 21:56 UTC (permalink / raw)
To: qemu-devel
Cc: David Gibson, Alexander Graf, qemu-ppc, Thomas Huth,
Giancarlo Teodori, Hervé Poussineau
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
---
hw/ppc/prep.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/ppc/prep.c b/hw/ppc/prep.c
index 054af1e..9fb89d3 100644
--- a/hw/ppc/prep.c
+++ b/hw/ppc/prep.c
@@ -339,13 +339,13 @@ static PortioList prep_port_list;
/* NVRAM helpers */
static inline uint32_t nvram_read(Nvram *nvram, uint32_t addr)
{
- NvramClass *k = NVRAM_GET_CLASS(sysctrl->nvram);
+ NvramClass *k = NVRAM_GET_CLASS(nvram);
return (k->read)(nvram, addr);
}
static inline void nvram_write(Nvram *nvram, uint32_t addr, uint32_t val)
{
- NvramClass *k = NVRAM_GET_CLASS(sysctrl->nvram);
+ NvramClass *k = NVRAM_GET_CLASS(nvram);
(k->write)(nvram, addr, val);
}
--
2.1.4
^ permalink raw reply related [flat|nested] 9+ messages in thread* [Qemu-devel] [PATCH v2 2/4] prep: add PReP System I/O
2017-01-05 21:56 [Qemu-devel] [PATCH v2 0/4] ppc: add a IBM 40p machine (RS/6000, PReP) Hervé Poussineau
2017-01-05 21:56 ` [Qemu-devel] [PATCH v2 1/4] prep: do not use global variable to access nvram Hervé Poussineau
@ 2017-01-05 21:56 ` Hervé Poussineau
2017-01-05 23:14 ` David Gibson
2017-01-05 21:56 ` [Qemu-devel] [PATCH v2 3/4] prep: add IBM RS/6000 7020 (40p) memory controller Hervé Poussineau
2017-01-05 21:56 ` [Qemu-devel] [PATCH v2 4/4] prep: add IBM RS/6000 7020 (40p) machine emulation Hervé Poussineau
3 siblings, 1 reply; 9+ messages in thread
From: Hervé Poussineau @ 2017-01-05 21:56 UTC (permalink / raw)
To: qemu-devel
Cc: David Gibson, Alexander Graf, qemu-ppc, Thomas Huth,
Giancarlo Teodori, Hervé Poussineau
This device is a partial duplicate of System I/O device available in hw/ppc/prep.c
This new one doesn't have all the Motorola-specific registers.
The old one should be deprecated and removed with the 'prep' machine.
Partial documentation available at
ftp://ftp.software.ibm.com/rs6000/technology/spec/srp1_1.exe
section 6.1.5 (I/O Device Mapping)
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
---
hw/ppc/Makefile.objs | 1 +
hw/ppc/prep_systemio.c | 309 +++++++++++++++++++++++++++++++++++++++++++++++++
hw/ppc/trace-events | 4 +
3 files changed, 314 insertions(+)
create mode 100644 hw/ppc/prep_systemio.c
diff --git a/hw/ppc/Makefile.objs b/hw/ppc/Makefile.objs
index 8025129..db72297 100644
--- a/hw/ppc/Makefile.objs
+++ b/hw/ppc/Makefile.objs
@@ -16,6 +16,7 @@ obj-y += ppc405_boards.o ppc4xx_devs.o ppc405_uc.o ppc440_bamboo.o
obj-y += ppc4xx_pci.o
# PReP
obj-$(CONFIG_PREP) += prep.o
+obj-$(CONFIG_PREP) += prep_systemio.o
# OldWorld PowerMac
obj-$(CONFIG_MAC) += mac_oldworld.o
# NewWorld PowerMac
diff --git a/hw/ppc/prep_systemio.c b/hw/ppc/prep_systemio.c
new file mode 100644
index 0000000..fa05cb0
--- /dev/null
+++ b/hw/ppc/prep_systemio.c
@@ -0,0 +1,309 @@
+/*
+ * QEMU PReP System I/O emulation
+ *
+ * Copyright (c) 2017 Hervé Poussineau
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/isa/isa.h"
+#include "exec/address-spaces.h"
+#include "qemu/error-report.h" /* for error_report() */
+#include "sysemu/sysemu.h" /* for vm_stop() */
+#include "cpu.h"
+#include "trace.h"
+
+#define TYPE_PREP_SYSTEMIO "prep-systemio"
+#define PREP_SYSTEMIO(obj) \
+ OBJECT_CHECK(PrepSystemIoState, (obj), TYPE_PREP_SYSTEMIO)
+
+/* Bit as defined in PowerPC Reference Plaform v1.1, sect. 6.1.5, p. 132 */
+#define PREP_BIT(n) (1 << (7 - (n)))
+
+typedef struct PrepSystemIoState {
+ ISADevice parent_obj;
+ MemoryRegion ppc_parity_mem;
+
+ qemu_irq non_contiguous_io_map_irq;
+ uint8_t sreset; /* 0x0092 */
+ uint8_t equipment; /* 0x080c */
+ uint8_t system_control; /* 0x081c */
+ uint8_t iomap_type; /* 0x0850 */
+ uint8_t ibm_planar_id; /* 0x0852 */
+ qemu_irq softreset_irq;
+ PortioList portio;
+} PrepSystemIoState;
+
+/* PORT 0092 -- Special Port 92 (Read/Write) */
+
+enum {
+ PORT0092_SOFTRESET = PREP_BIT(7),
+ PORT0092_LE_MODE = PREP_BIT(6),
+};
+
+static void prep_port0092_write(void *opaque, uint32_t addr, uint32_t val)
+{
+ PrepSystemIoState *s = opaque;
+
+ trace_prep_systemio_write(addr, val);
+
+ s->sreset = val & PORT0092_SOFTRESET;
+ qemu_set_irq(s->softreset_irq, s->sreset);
+
+ if ((val & PORT0092_LE_MODE) != 0) {
+ /* XXX Not supported yet */
+ error_report("little-endian mode not supported");
+ vm_stop(RUN_STATE_PAUSED);
+ } else {
+ /* Nothing to do */
+ }
+}
+
+static uint32_t prep_port0092_read(void *opaque, uint32_t addr)
+{
+ PrepSystemIoState *s = opaque;
+ uint8_t ret = 0;
+
+ /* XXX LE mode unsupported */
+ if (s->sreset) {
+ ret |= PORT0092_SOFTRESET;
+ }
+ trace_prep_systemio_read(addr, ret);
+ return ret;
+}
+
+/* PORT 0808 -- Hardfile Light Register (Write Only) */
+
+enum {
+ PORT0808_HARDFILE_LIGHT_ON = PREP_BIT(7),
+};
+
+static void prep_port0808_write(void *opaque, uint32_t addr, uint32_t val)
+{
+ trace_prep_systemio_write(addr, val);
+}
+
+/* PORT 0810 -- Password Protect 1 Register (Write Only) */
+
+/* reset by port 0x4D in the SIO */
+static void prep_port0810_write(void *opaque, uint32_t addr, uint32_t val)
+{
+ trace_prep_systemio_write(addr, val);
+}
+
+/* PORT 0812 -- Password Protect 2 Register (Write Only) */
+
+/* reset by port 0x4D in the SIO */
+static void prep_port0812_write(void *opaque, uint32_t addr, uint32_t val)
+{
+ trace_prep_systemio_write(addr, val);
+}
+
+/* PORT 0814 -- L2 Invalidate Register (Write Only) */
+
+static void prep_port0814_write(void *opaque, uint32_t addr, uint32_t val)
+{
+ trace_prep_systemio_write(addr, val);
+}
+
+/* PORT 0818 -- Reserved for Keylock (Read Only) */
+
+enum {
+ PORT0818_KEYLOCK_SIGNAL_HIGH = PREP_BIT(7),
+};
+
+static uint32_t prep_port0818_read(void *opaque, uint32_t addr)
+{
+ uint32_t val = 0;
+ trace_prep_systemio_read(addr, val);
+ return val;
+}
+
+/* PORT 080C -- Equipment */
+
+enum {
+ PORT080C_SCSIFUSE = PREP_BIT(1),
+ PORT080C_L2_COPYBACK = PREP_BIT(4),
+ PORT080C_L2_256 = PREP_BIT(5),
+ PORT080C_UPGRADE_CPU = PREP_BIT(6),
+ PORT080C_L2 = PREP_BIT(7),
+};
+
+static uint32_t prep_port080c_read(void *opaque, uint32_t addr)
+{
+ PrepSystemIoState *s = opaque;
+ trace_prep_systemio_read(addr, s->equipment);
+ return s->equipment;
+}
+
+/* PORT 081C -- System Control Register (Read/Write) */
+
+enum {
+ PORT081C_FLOPPY_MOTOR_INHIBIT = PREP_BIT(3),
+ PORT081C_MASK_TEA = PREP_BIT(2),
+ PORT081C_L2_UPDATE_INHIBIT = PREP_BIT(1),
+ PORT081C_L2_CACHEMISS_INHIBIT = PREP_BIT(0),
+};
+
+static void prep_port081c_write(void *opaque, uint32_t addr, uint32_t val)
+{
+ static const uint8_t mask = PORT081C_FLOPPY_MOTOR_INHIBIT |
+ PORT081C_MASK_TEA |
+ PORT081C_L2_UPDATE_INHIBIT |
+ PORT081C_L2_CACHEMISS_INHIBIT;
+ PrepSystemIoState *s = opaque;
+ trace_prep_systemio_write(addr, val);
+ s->system_control = val & mask;
+}
+
+static uint32_t prep_port081c_read(void *opaque, uint32_t addr)
+{
+ PrepSystemIoState *s = opaque;
+ trace_prep_systemio_read(addr, s->system_control);
+ return s->system_control;
+}
+
+/* System Board Identification */
+
+static uint32_t prep_port0852_read(void *opaque, uint32_t addr)
+{
+ PrepSystemIoState *s = opaque;
+ trace_prep_systemio_read(addr, s->ibm_planar_id);
+ return s->ibm_planar_id;
+}
+
+/* PORT 0850 -- I/O Map Type Register (Read/Write) */
+
+enum {
+ PORT0850_IOMAP_NONCONTIGUOUS = PREP_BIT(7),
+};
+
+static uint32_t prep_port0850_read(void *opaque, uint32_t addr)
+{
+ PrepSystemIoState *s = opaque;
+ trace_prep_systemio_read(addr, s->iomap_type);
+ return s->iomap_type;
+}
+
+static void prep_port0850_write(void *opaque, uint32_t addr, uint32_t val)
+{
+ PrepSystemIoState *s = opaque;
+
+ trace_prep_systemio_write(addr, val);
+ qemu_set_irq(s->non_contiguous_io_map_irq,
+ val & PORT0850_IOMAP_NONCONTIGUOUS);
+ s->iomap_type = val & PORT0850_IOMAP_NONCONTIGUOUS;
+}
+
+static const MemoryRegionPortio ppc_io800_port_list[] = {
+ { 0x092, 1, 1, .read = prep_port0092_read,
+ .write = prep_port0092_write, },
+ { 0x808, 1, 1, .write = prep_port0808_write, },
+ { 0x80c, 1, 1, .read = prep_port080c_read, },
+ { 0x810, 1, 1, .write = prep_port0810_write, },
+ { 0x812, 1, 1, .write = prep_port0812_write, },
+ { 0x814, 1, 1, .write = prep_port0814_write, },
+ { 0x818, 1, 1, .read = prep_port0818_read },
+ { 0x81c, 1, 1, .read = prep_port081c_read,
+ .write = prep_port081c_write, },
+ { 0x850, 1, 1, .read = prep_port0850_read,
+ .write = prep_port0850_write, },
+ { 0x852, 1, 1, .read = prep_port0852_read, },
+ PORTIO_END_OF_LIST()
+};
+
+static uint64_t ppc_parity_error_readl(void *opaque, hwaddr addr,
+ unsigned int size)
+{
+ uint32_t val = 0;
+ trace_prep_systemio_read((unsigned int)addr, val);
+ return val;
+}
+
+static const MemoryRegionOps ppc_parity_error_ops = {
+ .read = ppc_parity_error_readl,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
+};
+
+static void prep_systemio_realize(DeviceState *dev, Error **errp)
+{
+ ISADevice *isa = ISA_DEVICE(dev);
+ PrepSystemIoState *s = PREP_SYSTEMIO(dev);
+ PowerPCCPU *cpu;
+
+ qdev_init_gpio_out(dev, &s->non_contiguous_io_map_irq, 1);
+ s->iomap_type = PORT0850_IOMAP_NONCONTIGUOUS;
+ qemu_set_irq(s->non_contiguous_io_map_irq,
+ s->iomap_type & PORT0850_IOMAP_NONCONTIGUOUS);
+ cpu = POWERPC_CPU(first_cpu);
+ s->softreset_irq = cpu->env.irq_inputs[PPC6xx_INPUT_HRESET];
+
+ isa_register_portio_list(isa, &s->portio, 0x0, ppc_io800_port_list, s,
+ "systemio800");
+
+ memory_region_init_io(&s->ppc_parity_mem, OBJECT(dev),
+ &ppc_parity_error_ops, s, "ppc-parity", 0x4);
+ memory_region_add_subregion(get_system_memory(), 0xbfffeff0,
+ &s->ppc_parity_mem);
+}
+
+static const VMStateDescription vmstate_prep_systemio = {
+ .name = "prep_systemio",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT8(sreset, PrepSystemIoState),
+ VMSTATE_UINT8(system_control, PrepSystemIoState),
+ VMSTATE_UINT8(iomap_type, PrepSystemIoState),
+ VMSTATE_END_OF_LIST()
+ },
+};
+
+static Property prep_systemio_properties[] = {
+ DEFINE_PROP_UINT8("ibm-planar-id", PrepSystemIoState, ibm_planar_id, 0),
+ DEFINE_PROP_UINT8("equipment", PrepSystemIoState, equipment, 0),
+ DEFINE_PROP_END_OF_LIST()
+};
+
+static void prep_systemio_class_initfn(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->realize = prep_systemio_realize;
+ dc->vmsd = &vmstate_prep_systemio;
+ dc->props = prep_systemio_properties;
+}
+
+static TypeInfo prep_systemio800_info = {
+ .name = TYPE_PREP_SYSTEMIO,
+ .parent = TYPE_ISA_DEVICE,
+ .instance_size = sizeof(PrepSystemIoState),
+ .class_init = prep_systemio_class_initfn,
+};
+
+static void prep_systemio_register_types(void)
+{
+ type_register_static(&prep_systemio800_info);
+}
+
+type_init(prep_systemio_register_types)
diff --git a/hw/ppc/trace-events b/hw/ppc/trace-events
index 2297ead..2ba6166 100644
--- a/hw/ppc/trace-events
+++ b/hw/ppc/trace-events
@@ -74,3 +74,7 @@ ppc_tb_adjust(uint64_t offs1, uint64_t offs2, int64_t diff, int64_t seconds) "ad
# hw/ppc/prep.c
prep_io_800_writeb(uint32_t addr, uint32_t val) "0x%08" PRIx32 " => 0x%02" PRIx32
prep_io_800_readb(uint32_t addr, uint32_t retval) "0x%08" PRIx32 " <= 0x%02" PRIx32
+
+# hw/ppc/prep_systemio.c
+prep_systemio_read(uint32_t addr, uint32_t val) "read addr=%x val=%x"
+prep_systemio_write(uint32_t addr, uint32_t val) "write addr=%x val=%x"
--
2.1.4
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [Qemu-devel] [PATCH v2 2/4] prep: add PReP System I/O
2017-01-05 21:56 ` [Qemu-devel] [PATCH v2 2/4] prep: add PReP System I/O Hervé Poussineau
@ 2017-01-05 23:14 ` David Gibson
0 siblings, 0 replies; 9+ messages in thread
From: David Gibson @ 2017-01-05 23:14 UTC (permalink / raw)
To: Hervé Poussineau
Cc: qemu-devel, Alexander Graf, qemu-ppc, Thomas Huth,
Giancarlo Teodori
[-- Attachment #1: Type: text/plain, Size: 13525 bytes --]
On Thu, Jan 05, 2017 at 10:56:55PM +0100, Hervé Poussineau wrote:
> This device is a partial duplicate of System I/O device available in hw/ppc/prep.c
> This new one doesn't have all the Motorola-specific registers.
> The old one should be deprecated and removed with the 'prep' machine.
>
> Partial documentation available at
> ftp://ftp.software.ibm.com/rs6000/technology/spec/srp1_1.exe
> section 6.1.5 (I/O Device Mapping)
>
> Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
With one exception noted below,
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
> ---
> hw/ppc/Makefile.objs | 1 +
> hw/ppc/prep_systemio.c | 309 +++++++++++++++++++++++++++++++++++++++++++++++++
> hw/ppc/trace-events | 4 +
> 3 files changed, 314 insertions(+)
> create mode 100644 hw/ppc/prep_systemio.c
>
> diff --git a/hw/ppc/Makefile.objs b/hw/ppc/Makefile.objs
> index 8025129..db72297 100644
> --- a/hw/ppc/Makefile.objs
> +++ b/hw/ppc/Makefile.objs
> @@ -16,6 +16,7 @@ obj-y += ppc405_boards.o ppc4xx_devs.o ppc405_uc.o ppc440_bamboo.o
> obj-y += ppc4xx_pci.o
> # PReP
> obj-$(CONFIG_PREP) += prep.o
> +obj-$(CONFIG_PREP) += prep_systemio.o
> # OldWorld PowerMac
> obj-$(CONFIG_MAC) += mac_oldworld.o
> # NewWorld PowerMac
> diff --git a/hw/ppc/prep_systemio.c b/hw/ppc/prep_systemio.c
> new file mode 100644
> index 0000000..fa05cb0
> --- /dev/null
> +++ b/hw/ppc/prep_systemio.c
> @@ -0,0 +1,309 @@
> +/*
> + * QEMU PReP System I/O emulation
> + *
> + * Copyright (c) 2017 Hervé Poussineau
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a copy
> + * of this software and associated documentation files (the "Software"), to deal
> + * in the Software without restriction, including without limitation the rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "hw/isa/isa.h"
> +#include "exec/address-spaces.h"
> +#include "qemu/error-report.h" /* for error_report() */
> +#include "sysemu/sysemu.h" /* for vm_stop() */
> +#include "cpu.h"
> +#include "trace.h"
> +
> +#define TYPE_PREP_SYSTEMIO "prep-systemio"
> +#define PREP_SYSTEMIO(obj) \
> + OBJECT_CHECK(PrepSystemIoState, (obj), TYPE_PREP_SYSTEMIO)
> +
> +/* Bit as defined in PowerPC Reference Plaform v1.1, sect. 6.1.5, p. 132 */
> +#define PREP_BIT(n) (1 << (7 - (n)))
> +
> +typedef struct PrepSystemIoState {
> + ISADevice parent_obj;
> + MemoryRegion ppc_parity_mem;
> +
> + qemu_irq non_contiguous_io_map_irq;
> + uint8_t sreset; /* 0x0092 */
> + uint8_t equipment; /* 0x080c */
> + uint8_t system_control; /* 0x081c */
> + uint8_t iomap_type; /* 0x0850 */
> + uint8_t ibm_planar_id; /* 0x0852 */
> + qemu_irq softreset_irq;
> + PortioList portio;
> +} PrepSystemIoState;
> +
> +/* PORT 0092 -- Special Port 92 (Read/Write) */
> +
> +enum {
> + PORT0092_SOFTRESET = PREP_BIT(7),
> + PORT0092_LE_MODE = PREP_BIT(6),
> +};
> +
> +static void prep_port0092_write(void *opaque, uint32_t addr, uint32_t val)
> +{
> + PrepSystemIoState *s = opaque;
> +
> + trace_prep_systemio_write(addr, val);
> +
> + s->sreset = val & PORT0092_SOFTRESET;
> + qemu_set_irq(s->softreset_irq, s->sreset);
> +
> + if ((val & PORT0092_LE_MODE) != 0) {
> + /* XXX Not supported yet */
> + error_report("little-endian mode not supported");
> + vm_stop(RUN_STATE_PAUSED);
> + } else {
> + /* Nothing to do */
> + }
> +}
> +
> +static uint32_t prep_port0092_read(void *opaque, uint32_t addr)
> +{
> + PrepSystemIoState *s = opaque;
> + uint8_t ret = 0;
> +
> + /* XXX LE mode unsupported */
> + if (s->sreset) {
> + ret |= PORT0092_SOFTRESET;
> + }
So, I asked you to change this to make read and write match logically,
but now you've changed both sides so they still don't match.
Now that write sets s->sreset directly to (masked) val, read should
just return it plain as well.
Basically it needs to be clear whether s->sreset represents the
register value itself, or is just a boolean flag. In the previous
version, write treated it like a boolean and read treated it like a
register value. Now write treats it like a register value and read
treats it like a boolean. Pick one.
> + trace_prep_systemio_read(addr, ret);
> + return ret;
> +}
> +
> +/* PORT 0808 -- Hardfile Light Register (Write Only) */
> +
> +enum {
> + PORT0808_HARDFILE_LIGHT_ON = PREP_BIT(7),
> +};
> +
> +static void prep_port0808_write(void *opaque, uint32_t addr, uint32_t val)
> +{
> + trace_prep_systemio_write(addr, val);
> +}
> +
> +/* PORT 0810 -- Password Protect 1 Register (Write Only) */
> +
> +/* reset by port 0x4D in the SIO */
> +static void prep_port0810_write(void *opaque, uint32_t addr, uint32_t val)
> +{
> + trace_prep_systemio_write(addr, val);
> +}
> +
> +/* PORT 0812 -- Password Protect 2 Register (Write Only) */
> +
> +/* reset by port 0x4D in the SIO */
> +static void prep_port0812_write(void *opaque, uint32_t addr, uint32_t val)
> +{
> + trace_prep_systemio_write(addr, val);
> +}
> +
> +/* PORT 0814 -- L2 Invalidate Register (Write Only) */
> +
> +static void prep_port0814_write(void *opaque, uint32_t addr, uint32_t val)
> +{
> + trace_prep_systemio_write(addr, val);
> +}
> +
> +/* PORT 0818 -- Reserved for Keylock (Read Only) */
> +
> +enum {
> + PORT0818_KEYLOCK_SIGNAL_HIGH = PREP_BIT(7),
> +};
> +
> +static uint32_t prep_port0818_read(void *opaque, uint32_t addr)
> +{
> + uint32_t val = 0;
> + trace_prep_systemio_read(addr, val);
> + return val;
> +}
> +
> +/* PORT 080C -- Equipment */
> +
> +enum {
> + PORT080C_SCSIFUSE = PREP_BIT(1),
> + PORT080C_L2_COPYBACK = PREP_BIT(4),
> + PORT080C_L2_256 = PREP_BIT(5),
> + PORT080C_UPGRADE_CPU = PREP_BIT(6),
> + PORT080C_L2 = PREP_BIT(7),
> +};
> +
> +static uint32_t prep_port080c_read(void *opaque, uint32_t addr)
> +{
> + PrepSystemIoState *s = opaque;
> + trace_prep_systemio_read(addr, s->equipment);
> + return s->equipment;
> +}
> +
> +/* PORT 081C -- System Control Register (Read/Write) */
> +
> +enum {
> + PORT081C_FLOPPY_MOTOR_INHIBIT = PREP_BIT(3),
> + PORT081C_MASK_TEA = PREP_BIT(2),
> + PORT081C_L2_UPDATE_INHIBIT = PREP_BIT(1),
> + PORT081C_L2_CACHEMISS_INHIBIT = PREP_BIT(0),
> +};
> +
> +static void prep_port081c_write(void *opaque, uint32_t addr, uint32_t val)
> +{
> + static const uint8_t mask = PORT081C_FLOPPY_MOTOR_INHIBIT |
> + PORT081C_MASK_TEA |
> + PORT081C_L2_UPDATE_INHIBIT |
> + PORT081C_L2_CACHEMISS_INHIBIT;
> + PrepSystemIoState *s = opaque;
> + trace_prep_systemio_write(addr, val);
> + s->system_control = val & mask;
> +}
> +
> +static uint32_t prep_port081c_read(void *opaque, uint32_t addr)
> +{
> + PrepSystemIoState *s = opaque;
> + trace_prep_systemio_read(addr, s->system_control);
> + return s->system_control;
> +}
> +
> +/* System Board Identification */
> +
> +static uint32_t prep_port0852_read(void *opaque, uint32_t addr)
> +{
> + PrepSystemIoState *s = opaque;
> + trace_prep_systemio_read(addr, s->ibm_planar_id);
> + return s->ibm_planar_id;
> +}
> +
> +/* PORT 0850 -- I/O Map Type Register (Read/Write) */
> +
> +enum {
> + PORT0850_IOMAP_NONCONTIGUOUS = PREP_BIT(7),
> +};
> +
> +static uint32_t prep_port0850_read(void *opaque, uint32_t addr)
> +{
> + PrepSystemIoState *s = opaque;
> + trace_prep_systemio_read(addr, s->iomap_type);
> + return s->iomap_type;
> +}
> +
> +static void prep_port0850_write(void *opaque, uint32_t addr, uint32_t val)
> +{
> + PrepSystemIoState *s = opaque;
> +
> + trace_prep_systemio_write(addr, val);
> + qemu_set_irq(s->non_contiguous_io_map_irq,
> + val & PORT0850_IOMAP_NONCONTIGUOUS);
> + s->iomap_type = val & PORT0850_IOMAP_NONCONTIGUOUS;
> +}
> +
> +static const MemoryRegionPortio ppc_io800_port_list[] = {
> + { 0x092, 1, 1, .read = prep_port0092_read,
> + .write = prep_port0092_write, },
> + { 0x808, 1, 1, .write = prep_port0808_write, },
> + { 0x80c, 1, 1, .read = prep_port080c_read, },
> + { 0x810, 1, 1, .write = prep_port0810_write, },
> + { 0x812, 1, 1, .write = prep_port0812_write, },
> + { 0x814, 1, 1, .write = prep_port0814_write, },
> + { 0x818, 1, 1, .read = prep_port0818_read },
> + { 0x81c, 1, 1, .read = prep_port081c_read,
> + .write = prep_port081c_write, },
> + { 0x850, 1, 1, .read = prep_port0850_read,
> + .write = prep_port0850_write, },
> + { 0x852, 1, 1, .read = prep_port0852_read, },
> + PORTIO_END_OF_LIST()
> +};
> +
> +static uint64_t ppc_parity_error_readl(void *opaque, hwaddr addr,
> + unsigned int size)
> +{
> + uint32_t val = 0;
> + trace_prep_systemio_read((unsigned int)addr, val);
> + return val;
> +}
> +
> +static const MemoryRegionOps ppc_parity_error_ops = {
> + .read = ppc_parity_error_readl,
> + .valid = {
> + .min_access_size = 4,
> + .max_access_size = 4,
> + },
> +};
> +
> +static void prep_systemio_realize(DeviceState *dev, Error **errp)
> +{
> + ISADevice *isa = ISA_DEVICE(dev);
> + PrepSystemIoState *s = PREP_SYSTEMIO(dev);
> + PowerPCCPU *cpu;
> +
> + qdev_init_gpio_out(dev, &s->non_contiguous_io_map_irq, 1);
> + s->iomap_type = PORT0850_IOMAP_NONCONTIGUOUS;
> + qemu_set_irq(s->non_contiguous_io_map_irq,
> + s->iomap_type & PORT0850_IOMAP_NONCONTIGUOUS);
> + cpu = POWERPC_CPU(first_cpu);
> + s->softreset_irq = cpu->env.irq_inputs[PPC6xx_INPUT_HRESET];
> +
> + isa_register_portio_list(isa, &s->portio, 0x0, ppc_io800_port_list, s,
> + "systemio800");
> +
> + memory_region_init_io(&s->ppc_parity_mem, OBJECT(dev),
> + &ppc_parity_error_ops, s, "ppc-parity", 0x4);
> + memory_region_add_subregion(get_system_memory(), 0xbfffeff0,
> + &s->ppc_parity_mem);
> +}
> +
> +static const VMStateDescription vmstate_prep_systemio = {
> + .name = "prep_systemio",
> + .version_id = 1,
> + .minimum_version_id = 1,
> + .fields = (VMStateField[]) {
> + VMSTATE_UINT8(sreset, PrepSystemIoState),
> + VMSTATE_UINT8(system_control, PrepSystemIoState),
> + VMSTATE_UINT8(iomap_type, PrepSystemIoState),
> + VMSTATE_END_OF_LIST()
> + },
> +};
> +
> +static Property prep_systemio_properties[] = {
> + DEFINE_PROP_UINT8("ibm-planar-id", PrepSystemIoState, ibm_planar_id, 0),
> + DEFINE_PROP_UINT8("equipment", PrepSystemIoState, equipment, 0),
> + DEFINE_PROP_END_OF_LIST()
> +};
> +
> +static void prep_systemio_class_initfn(ObjectClass *klass, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(klass);
> +
> + dc->realize = prep_systemio_realize;
> + dc->vmsd = &vmstate_prep_systemio;
> + dc->props = prep_systemio_properties;
> +}
> +
> +static TypeInfo prep_systemio800_info = {
> + .name = TYPE_PREP_SYSTEMIO,
> + .parent = TYPE_ISA_DEVICE,
> + .instance_size = sizeof(PrepSystemIoState),
> + .class_init = prep_systemio_class_initfn,
> +};
> +
> +static void prep_systemio_register_types(void)
> +{
> + type_register_static(&prep_systemio800_info);
> +}
> +
> +type_init(prep_systemio_register_types)
> diff --git a/hw/ppc/trace-events b/hw/ppc/trace-events
> index 2297ead..2ba6166 100644
> --- a/hw/ppc/trace-events
> +++ b/hw/ppc/trace-events
> @@ -74,3 +74,7 @@ ppc_tb_adjust(uint64_t offs1, uint64_t offs2, int64_t diff, int64_t seconds) "ad
> # hw/ppc/prep.c
> prep_io_800_writeb(uint32_t addr, uint32_t val) "0x%08" PRIx32 " => 0x%02" PRIx32
> prep_io_800_readb(uint32_t addr, uint32_t retval) "0x%08" PRIx32 " <= 0x%02" PRIx32
> +
> +# hw/ppc/prep_systemio.c
> +prep_systemio_read(uint32_t addr, uint32_t val) "read addr=%x val=%x"
> +prep_systemio_write(uint32_t addr, uint32_t val) "write addr=%x val=%x"
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
^ permalink raw reply [flat|nested] 9+ messages in thread
* [Qemu-devel] [PATCH v2 3/4] prep: add IBM RS/6000 7020 (40p) memory controller
2017-01-05 21:56 [Qemu-devel] [PATCH v2 0/4] ppc: add a IBM 40p machine (RS/6000, PReP) Hervé Poussineau
2017-01-05 21:56 ` [Qemu-devel] [PATCH v2 1/4] prep: do not use global variable to access nvram Hervé Poussineau
2017-01-05 21:56 ` [Qemu-devel] [PATCH v2 2/4] prep: add PReP System I/O Hervé Poussineau
@ 2017-01-05 21:56 ` Hervé Poussineau
2017-01-05 23:15 ` David Gibson
2017-01-05 21:56 ` [Qemu-devel] [PATCH v2 4/4] prep: add IBM RS/6000 7020 (40p) machine emulation Hervé Poussineau
3 siblings, 1 reply; 9+ messages in thread
From: Hervé Poussineau @ 2017-01-05 21:56 UTC (permalink / raw)
To: qemu-devel
Cc: David Gibson, Alexander Graf, qemu-ppc, Thomas Huth,
Giancarlo Teodori, Hervé Poussineau
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
---
default-configs/ppc-softmmu.mak | 1 +
hw/ppc/Makefile.objs | 1 +
hw/ppc/rs6000_mc.c | 232 ++++++++++++++++++++++++++++++++++++++++
hw/ppc/trace-events | 7 ++
4 files changed, 241 insertions(+)
create mode 100644 hw/ppc/rs6000_mc.c
diff --git a/default-configs/ppc-softmmu.mak b/default-configs/ppc-softmmu.mak
index d4d0f9b..e567658 100644
--- a/default-configs/ppc-softmmu.mak
+++ b/default-configs/ppc-softmmu.mak
@@ -47,3 +47,4 @@ CONFIG_LIBDECNUMBER=y
# For PReP
CONFIG_MC146818RTC=y
CONFIG_ISA_TESTDEV=y
+CONFIG_RS6000_MC=y
diff --git a/hw/ppc/Makefile.objs b/hw/ppc/Makefile.objs
index db72297..0012934 100644
--- a/hw/ppc/Makefile.objs
+++ b/hw/ppc/Makefile.objs
@@ -17,6 +17,7 @@ obj-y += ppc4xx_pci.o
# PReP
obj-$(CONFIG_PREP) += prep.o
obj-$(CONFIG_PREP) += prep_systemio.o
+obj-${CONFIG_RS6000_MC} += rs6000_mc.o
# OldWorld PowerMac
obj-$(CONFIG_MAC) += mac_oldworld.o
# NewWorld PowerMac
diff --git a/hw/ppc/rs6000_mc.c b/hw/ppc/rs6000_mc.c
new file mode 100644
index 0000000..b613565
--- /dev/null
+++ b/hw/ppc/rs6000_mc.c
@@ -0,0 +1,232 @@
+/*
+ * QEMU RS/6000 memory controller
+ *
+ * Copyright (c) 2017 Hervé Poussineau
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) version 3 or any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/isa/isa.h"
+#include "exec/address-spaces.h"
+#include "hw/boards.h"
+#include "qapi/error.h"
+#include "trace.h"
+
+#define TYPE_RS6000MC "rs6000-mc"
+#define RS6000MC_DEVICE(obj) \
+ OBJECT_CHECK(RS6000MCState, (obj), TYPE_RS6000MC)
+
+typedef struct RS6000MCState {
+ ISADevice parent_obj;
+ /* see US patent 5,684,979 for details (expired 2001-11-04) */
+ uint32_t ram_size;
+ bool autoconfigure;
+ MemoryRegion simm[6];
+ unsigned int simm_size[6];
+ uint32_t end_address[8];
+ uint8_t port0820_index;
+ PortioList portio;
+} RS6000MCState;
+
+/* P0RT 0803 -- SIMM ID Register (32/8 MB) (Read Only) */
+
+static uint32_t rs6000mc_port0803_read(void *opaque, uint32_t addr)
+{
+ RS6000MCState *s = opaque;
+ uint32_t val = 0;
+ int socket;
+
+ /* (1 << socket) indicates 32 MB SIMM at given socket */
+ for (socket = 0; socket < 6; socket++) {
+ if (s->simm_size[socket] == 32) {
+ val |= (1 << socket);
+ }
+ }
+
+ trace_rs6000mc_id_read(addr, val);
+ return val;
+}
+
+/* PORT 0804 -- SIMM Presence Register (Read Only) */
+
+static uint32_t rs6000mc_port0804_read(void *opaque, uint32_t addr)
+{
+ RS6000MCState *s = opaque;
+ uint32_t val = 0xff;
+ int socket;
+
+ /* (1 << socket) indicates SIMM absence at given socket */
+ for (socket = 0; socket < 6; socket++) {
+ if (s->simm_size[socket]) {
+ val &= ~(1 << socket);
+ }
+ }
+ s->port0820_index = 0;
+
+ trace_rs6000mc_presence_read(addr, val);
+ return val;
+}
+
+/* Memory Controller Size Programming Register */
+
+static uint32_t rs6000mc_port0820_read(void *opaque, uint32_t addr)
+{
+ RS6000MCState *s = opaque;
+ uint32_t val = s->end_address[s->port0820_index] & 0x1f;
+ s->port0820_index = (s->port0820_index + 1) & 7;
+ trace_rs6000mc_size_read(addr, val);
+ return val;
+}
+
+static void rs6000mc_port0820_write(void *opaque, uint32_t addr, uint32_t val)
+{
+ RS6000MCState *s = opaque;
+ uint8_t socket = val >> 5;
+ uint32_t end_address = val & 0x1f;
+
+ trace_rs6000mc_size_write(addr, val);
+ s->end_address[socket] = end_address;
+ if (socket > 0 && socket < 7) {
+ if (s->simm_size[socket - 1]) {
+ uint32_t size;
+ uint32_t start_address = 0;
+ if (socket > 1) {
+ start_address = s->end_address[socket - 1];
+ }
+
+ size = end_address - start_address;
+ memory_region_set_enabled(&s->simm[socket - 1], size != 0);
+ memory_region_set_address(&s->simm[socket - 1],
+ start_address * 8 * 1024 * 1024);
+ }
+ }
+}
+
+/* Read Memory Parity Error */
+
+enum {
+ PORT0841_NO_ERROR_DETECTED = 0x01,
+};
+
+static uint32_t rs6000mc_port0841_read(void *opaque, uint32_t addr)
+{
+ uint32_t val = PORT0841_NO_ERROR_DETECTED;
+ trace_rs6000mc_parity_read(addr, val);
+ return val;
+}
+
+static const MemoryRegionPortio rs6000mc_port_list[] = {
+ { 0x803, 1, 1, .read = rs6000mc_port0803_read },
+ { 0x804, 1, 1, .read = rs6000mc_port0804_read },
+ { 0x820, 1, 1, .read = rs6000mc_port0820_read,
+ .write = rs6000mc_port0820_write, },
+ { 0x841, 1, 1, .read = rs6000mc_port0841_read },
+ PORTIO_END_OF_LIST()
+};
+
+static void rs6000mc_realize(DeviceState *dev, Error **errp)
+{
+ RS6000MCState *s = RS6000MC_DEVICE(dev);
+ int socket = 0;
+ unsigned int ram_size = s->ram_size / (1024 * 1024);
+
+ while (socket < 6) {
+ if (ram_size >= 64) {
+ s->simm_size[socket] = 32;
+ s->simm_size[socket + 1] = 32;
+ ram_size -= 64;
+ } else if (ram_size >= 16) {
+ s->simm_size[socket] = 8;
+ s->simm_size[socket + 1] = 8;
+ ram_size -= 16;
+ } else {
+ /* Not enough memory */
+ break;
+ }
+ socket += 2;
+ }
+
+ for (socket = 0; socket < 6; socket++) {
+ if (s->simm_size[socket]) {
+ char name[] = "simm.?";
+ name[5] = socket + '0';
+ memory_region_allocate_system_memory(&s->simm[socket], OBJECT(dev),
+ name, s->simm_size[socket]
+ * 1024 * 1024);
+ memory_region_add_subregion_overlap(get_system_memory(), 0,
+ &s->simm[socket], socket);
+ }
+ }
+ if (ram_size) {
+ /* unable to push all requested RAM in SIMMs */
+ error_setg(errp, "RAM size incompatible with this board. "
+ "Try again with something else, like %d MB",
+ s->ram_size / 1024 / 1024 - ram_size);
+ return;
+ }
+
+ if (s->autoconfigure) {
+ uint32_t start_address = 0;
+ for (socket = 0; socket < 6; socket++) {
+ if (s->simm_size[socket]) {
+ memory_region_set_enabled(&s->simm[socket], true);
+ memory_region_set_address(&s->simm[socket], start_address);
+ start_address += memory_region_size(&s->simm[socket]);
+ }
+ }
+ }
+
+ isa_register_portio_list(ISA_DEVICE(dev), &s->portio, 0x0,
+ rs6000mc_port_list, s, "rs6000mc");
+}
+
+static const VMStateDescription vmstate_rs6000mc = {
+ .name = "rs6000-mc",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT8(port0820_index, RS6000MCState),
+ VMSTATE_END_OF_LIST()
+ },
+};
+
+static Property rs6000mc_properties[] = {
+ DEFINE_PROP_UINT32("ram-size", RS6000MCState, ram_size, 0),
+ DEFINE_PROP_BOOL("auto-configure", RS6000MCState, autoconfigure, true),
+ DEFINE_PROP_END_OF_LIST()
+};
+
+static void rs6000mc_class_initfn(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->realize = rs6000mc_realize;
+ dc->vmsd = &vmstate_rs6000mc;
+ dc->props = rs6000mc_properties;
+}
+
+static const TypeInfo rs6000mc_info = {
+ .name = TYPE_RS6000MC,
+ .parent = TYPE_ISA_DEVICE,
+ .instance_size = sizeof(RS6000MCState),
+ .class_init = rs6000mc_class_initfn,
+};
+
+static void rs6000mc_types(void)
+{
+ type_register_static(&rs6000mc_info);
+}
+
+type_init(rs6000mc_types)
diff --git a/hw/ppc/trace-events b/hw/ppc/trace-events
index 2ba6166..42b8ec0 100644
--- a/hw/ppc/trace-events
+++ b/hw/ppc/trace-events
@@ -78,3 +78,10 @@ prep_io_800_readb(uint32_t addr, uint32_t retval) "0x%08" PRIx32 " <= 0x%02" PRI
# hw/ppc/prep_systemio.c
prep_systemio_read(uint32_t addr, uint32_t val) "read addr=%x val=%x"
prep_systemio_write(uint32_t addr, uint32_t val) "write addr=%x val=%x"
+
+# hw/ppc/rs6000_mc.c
+rs6000mc_id_read(uint32_t addr, uint32_t val) "read addr=%x val=%x"
+rs6000mc_presence_read(uint32_t addr, uint32_t val) "read addr=%x val=%x"
+rs6000mc_size_read(uint32_t addr, uint32_t val) "read addr=%x val=%x"
+rs6000mc_size_write(uint32_t addr, uint32_t val) "write addr=%x val=%x"
+rs6000mc_parity_read(uint32_t addr, uint32_t val) "read addr=%x val=%x"
--
2.1.4
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [Qemu-devel] [PATCH v2 3/4] prep: add IBM RS/6000 7020 (40p) memory controller
2017-01-05 21:56 ` [Qemu-devel] [PATCH v2 3/4] prep: add IBM RS/6000 7020 (40p) memory controller Hervé Poussineau
@ 2017-01-05 23:15 ` David Gibson
0 siblings, 0 replies; 9+ messages in thread
From: David Gibson @ 2017-01-05 23:15 UTC (permalink / raw)
To: Hervé Poussineau
Cc: qemu-devel, Alexander Graf, qemu-ppc, Thomas Huth,
Giancarlo Teodori
[-- Attachment #1: Type: text/plain, Size: 10340 bytes --]
On Thu, Jan 05, 2017 at 10:56:56PM +0100, Hervé Poussineau wrote:
> Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
> ---
> default-configs/ppc-softmmu.mak | 1 +
> hw/ppc/Makefile.objs | 1 +
> hw/ppc/rs6000_mc.c | 232 ++++++++++++++++++++++++++++++++++++++++
> hw/ppc/trace-events | 7 ++
> 4 files changed, 241 insertions(+)
> create mode 100644 hw/ppc/rs6000_mc.c
>
> diff --git a/default-configs/ppc-softmmu.mak b/default-configs/ppc-softmmu.mak
> index d4d0f9b..e567658 100644
> --- a/default-configs/ppc-softmmu.mak
> +++ b/default-configs/ppc-softmmu.mak
> @@ -47,3 +47,4 @@ CONFIG_LIBDECNUMBER=y
> # For PReP
> CONFIG_MC146818RTC=y
> CONFIG_ISA_TESTDEV=y
> +CONFIG_RS6000_MC=y
> diff --git a/hw/ppc/Makefile.objs b/hw/ppc/Makefile.objs
> index db72297..0012934 100644
> --- a/hw/ppc/Makefile.objs
> +++ b/hw/ppc/Makefile.objs
> @@ -17,6 +17,7 @@ obj-y += ppc4xx_pci.o
> # PReP
> obj-$(CONFIG_PREP) += prep.o
> obj-$(CONFIG_PREP) += prep_systemio.o
> +obj-${CONFIG_RS6000_MC} += rs6000_mc.o
> # OldWorld PowerMac
> obj-$(CONFIG_MAC) += mac_oldworld.o
> # NewWorld PowerMac
> diff --git a/hw/ppc/rs6000_mc.c b/hw/ppc/rs6000_mc.c
> new file mode 100644
> index 0000000..b613565
> --- /dev/null
> +++ b/hw/ppc/rs6000_mc.c
> @@ -0,0 +1,232 @@
> +/*
> + * QEMU RS/6000 memory controller
> + *
> + * Copyright (c) 2017 Hervé Poussineau
> + *
> + * This program is free software: you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation, either version 2 of the License, or
> + * (at your option) version 3 or any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "hw/isa/isa.h"
> +#include "exec/address-spaces.h"
> +#include "hw/boards.h"
> +#include "qapi/error.h"
> +#include "trace.h"
> +
> +#define TYPE_RS6000MC "rs6000-mc"
> +#define RS6000MC_DEVICE(obj) \
> + OBJECT_CHECK(RS6000MCState, (obj), TYPE_RS6000MC)
> +
> +typedef struct RS6000MCState {
> + ISADevice parent_obj;
> + /* see US patent 5,684,979 for details (expired 2001-11-04) */
> + uint32_t ram_size;
> + bool autoconfigure;
> + MemoryRegion simm[6];
> + unsigned int simm_size[6];
> + uint32_t end_address[8];
> + uint8_t port0820_index;
> + PortioList portio;
> +} RS6000MCState;
> +
> +/* P0RT 0803 -- SIMM ID Register (32/8 MB) (Read Only) */
> +
> +static uint32_t rs6000mc_port0803_read(void *opaque, uint32_t addr)
> +{
> + RS6000MCState *s = opaque;
> + uint32_t val = 0;
> + int socket;
> +
> + /* (1 << socket) indicates 32 MB SIMM at given socket */
> + for (socket = 0; socket < 6; socket++) {
> + if (s->simm_size[socket] == 32) {
> + val |= (1 << socket);
> + }
> + }
> +
> + trace_rs6000mc_id_read(addr, val);
> + return val;
> +}
> +
> +/* PORT 0804 -- SIMM Presence Register (Read Only) */
> +
> +static uint32_t rs6000mc_port0804_read(void *opaque, uint32_t addr)
> +{
> + RS6000MCState *s = opaque;
> + uint32_t val = 0xff;
> + int socket;
> +
> + /* (1 << socket) indicates SIMM absence at given socket */
> + for (socket = 0; socket < 6; socket++) {
> + if (s->simm_size[socket]) {
> + val &= ~(1 << socket);
> + }
> + }
> + s->port0820_index = 0;
> +
> + trace_rs6000mc_presence_read(addr, val);
> + return val;
> +}
> +
> +/* Memory Controller Size Programming Register */
> +
> +static uint32_t rs6000mc_port0820_read(void *opaque, uint32_t addr)
> +{
> + RS6000MCState *s = opaque;
> + uint32_t val = s->end_address[s->port0820_index] & 0x1f;
> + s->port0820_index = (s->port0820_index + 1) & 7;
> + trace_rs6000mc_size_read(addr, val);
> + return val;
> +}
> +
> +static void rs6000mc_port0820_write(void *opaque, uint32_t addr, uint32_t val)
> +{
> + RS6000MCState *s = opaque;
> + uint8_t socket = val >> 5;
> + uint32_t end_address = val & 0x1f;
> +
> + trace_rs6000mc_size_write(addr, val);
> + s->end_address[socket] = end_address;
> + if (socket > 0 && socket < 7) {
> + if (s->simm_size[socket - 1]) {
> + uint32_t size;
> + uint32_t start_address = 0;
> + if (socket > 1) {
> + start_address = s->end_address[socket - 1];
> + }
> +
> + size = end_address - start_address;
> + memory_region_set_enabled(&s->simm[socket - 1], size != 0);
> + memory_region_set_address(&s->simm[socket - 1],
> + start_address * 8 * 1024 * 1024);
> + }
> + }
> +}
> +
> +/* Read Memory Parity Error */
> +
> +enum {
> + PORT0841_NO_ERROR_DETECTED = 0x01,
> +};
> +
> +static uint32_t rs6000mc_port0841_read(void *opaque, uint32_t addr)
> +{
> + uint32_t val = PORT0841_NO_ERROR_DETECTED;
> + trace_rs6000mc_parity_read(addr, val);
> + return val;
> +}
> +
> +static const MemoryRegionPortio rs6000mc_port_list[] = {
> + { 0x803, 1, 1, .read = rs6000mc_port0803_read },
> + { 0x804, 1, 1, .read = rs6000mc_port0804_read },
> + { 0x820, 1, 1, .read = rs6000mc_port0820_read,
> + .write = rs6000mc_port0820_write, },
> + { 0x841, 1, 1, .read = rs6000mc_port0841_read },
> + PORTIO_END_OF_LIST()
> +};
> +
> +static void rs6000mc_realize(DeviceState *dev, Error **errp)
> +{
> + RS6000MCState *s = RS6000MC_DEVICE(dev);
> + int socket = 0;
> + unsigned int ram_size = s->ram_size / (1024 * 1024);
> +
> + while (socket < 6) {
> + if (ram_size >= 64) {
> + s->simm_size[socket] = 32;
> + s->simm_size[socket + 1] = 32;
> + ram_size -= 64;
> + } else if (ram_size >= 16) {
> + s->simm_size[socket] = 8;
> + s->simm_size[socket + 1] = 8;
> + ram_size -= 16;
> + } else {
> + /* Not enough memory */
> + break;
> + }
> + socket += 2;
> + }
> +
> + for (socket = 0; socket < 6; socket++) {
> + if (s->simm_size[socket]) {
> + char name[] = "simm.?";
> + name[5] = socket + '0';
> + memory_region_allocate_system_memory(&s->simm[socket], OBJECT(dev),
> + name, s->simm_size[socket]
> + * 1024 * 1024);
> + memory_region_add_subregion_overlap(get_system_memory(), 0,
> + &s->simm[socket], socket);
> + }
> + }
> + if (ram_size) {
> + /* unable to push all requested RAM in SIMMs */
> + error_setg(errp, "RAM size incompatible with this board. "
> + "Try again with something else, like %d MB",
> + s->ram_size / 1024 / 1024 - ram_size);
> + return;
> + }
> +
> + if (s->autoconfigure) {
> + uint32_t start_address = 0;
> + for (socket = 0; socket < 6; socket++) {
> + if (s->simm_size[socket]) {
> + memory_region_set_enabled(&s->simm[socket], true);
> + memory_region_set_address(&s->simm[socket], start_address);
> + start_address += memory_region_size(&s->simm[socket]);
> + }
> + }
> + }
> +
> + isa_register_portio_list(ISA_DEVICE(dev), &s->portio, 0x0,
> + rs6000mc_port_list, s, "rs6000mc");
> +}
> +
> +static const VMStateDescription vmstate_rs6000mc = {
> + .name = "rs6000-mc",
> + .version_id = 1,
> + .minimum_version_id = 1,
> + .fields = (VMStateField[]) {
> + VMSTATE_UINT8(port0820_index, RS6000MCState),
> + VMSTATE_END_OF_LIST()
> + },
> +};
> +
> +static Property rs6000mc_properties[] = {
> + DEFINE_PROP_UINT32("ram-size", RS6000MCState, ram_size, 0),
> + DEFINE_PROP_BOOL("auto-configure", RS6000MCState, autoconfigure, true),
> + DEFINE_PROP_END_OF_LIST()
> +};
> +
> +static void rs6000mc_class_initfn(ObjectClass *klass, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(klass);
> +
> + dc->realize = rs6000mc_realize;
> + dc->vmsd = &vmstate_rs6000mc;
> + dc->props = rs6000mc_properties;
> +}
> +
> +static const TypeInfo rs6000mc_info = {
> + .name = TYPE_RS6000MC,
> + .parent = TYPE_ISA_DEVICE,
> + .instance_size = sizeof(RS6000MCState),
> + .class_init = rs6000mc_class_initfn,
> +};
> +
> +static void rs6000mc_types(void)
> +{
> + type_register_static(&rs6000mc_info);
> +}
> +
> +type_init(rs6000mc_types)
> diff --git a/hw/ppc/trace-events b/hw/ppc/trace-events
> index 2ba6166..42b8ec0 100644
> --- a/hw/ppc/trace-events
> +++ b/hw/ppc/trace-events
> @@ -78,3 +78,10 @@ prep_io_800_readb(uint32_t addr, uint32_t retval) "0x%08" PRIx32 " <= 0x%02" PRI
> # hw/ppc/prep_systemio.c
> prep_systemio_read(uint32_t addr, uint32_t val) "read addr=%x val=%x"
> prep_systemio_write(uint32_t addr, uint32_t val) "write addr=%x val=%x"
> +
> +# hw/ppc/rs6000_mc.c
> +rs6000mc_id_read(uint32_t addr, uint32_t val) "read addr=%x val=%x"
> +rs6000mc_presence_read(uint32_t addr, uint32_t val) "read addr=%x val=%x"
> +rs6000mc_size_read(uint32_t addr, uint32_t val) "read addr=%x val=%x"
> +rs6000mc_size_write(uint32_t addr, uint32_t val) "write addr=%x val=%x"
> +rs6000mc_parity_read(uint32_t addr, uint32_t val) "read addr=%x val=%x"
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
^ permalink raw reply [flat|nested] 9+ messages in thread
* [Qemu-devel] [PATCH v2 4/4] prep: add IBM RS/6000 7020 (40p) machine emulation
2017-01-05 21:56 [Qemu-devel] [PATCH v2 0/4] ppc: add a IBM 40p machine (RS/6000, PReP) Hervé Poussineau
` (2 preceding siblings ...)
2017-01-05 21:56 ` [Qemu-devel] [PATCH v2 3/4] prep: add IBM RS/6000 7020 (40p) memory controller Hervé Poussineau
@ 2017-01-05 21:56 ` Hervé Poussineau
2017-01-05 23:21 ` David Gibson
3 siblings, 1 reply; 9+ messages in thread
From: Hervé Poussineau @ 2017-01-05 21:56 UTC (permalink / raw)
To: qemu-devel
Cc: David Gibson, Alexander Graf, qemu-ppc, Thomas Huth,
Giancarlo Teodori, Hervé Poussineau
Machine supports both Open Hack'Ware and OpenBIOS.
Open Hack'Ware is the default because OpenBIOS is currently unable to boot
PReP boot partitions or PReP kernels.
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
---
default-configs/ppc-softmmu.mak | 1 +
hw/ppc/prep.c | 227 ++++++++++++++++++++++++++++++++++++++++
2 files changed, 228 insertions(+)
diff --git a/default-configs/ppc-softmmu.mak b/default-configs/ppc-softmmu.mak
index e567658..7dd004e 100644
--- a/default-configs/ppc-softmmu.mak
+++ b/default-configs/ppc-softmmu.mak
@@ -18,6 +18,7 @@ CONFIG_I82378=y
CONFIG_PC87312=y
CONFIG_MACIO=y
CONFIG_PCSPK=y
+CONFIG_CS4231A=y
CONFIG_CUDA=y
CONFIG_ADB=y
CONFIG_MAC_NVRAM=y
diff --git a/hw/ppc/prep.c b/hw/ppc/prep.c
index 9fb89d3..ec252de 100644
--- a/hw/ppc/prep.c
+++ b/hw/ppc/prep.c
@@ -2,6 +2,7 @@
* QEMU PPC PREP hardware System Emulator
*
* Copyright (c) 2003-2007 Jocelyn Mayer
+ * Copyright (c) 2017 Hervé Poussineau
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -43,6 +44,7 @@
#include "hw/isa/pc87312.h"
#include "sysemu/block-backend.h"
#include "sysemu/arch_init.h"
+#include "sysemu/kvm.h"
#include "sysemu/qtest.h"
#include "exec/address-spaces.h"
#include "trace.h"
@@ -54,6 +56,8 @@
#define MAX_IDE_BUS 2
+#define CFG_ADDR 0xf0000510
+
#define BIOS_SIZE (1024 * 1024)
#define BIOS_FILENAME "ppc_rom.bin"
#define KERNEL_LOAD_ADDR 0x01000000
@@ -316,6 +320,12 @@ static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr)
#define NVRAM_SIZE 0x2000
+static void fw_cfg_boot_set(void *opaque, const char *boot_device,
+ Error **errp)
+{
+ fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
+}
+
static void ppc_prep_reset(void *opaque)
{
PowerPCCPU *cpu = opaque;
@@ -677,4 +687,221 @@ static void prep_machine_init(MachineClass *mc)
mc->default_boot_order = "cad";
}
+static int prep_set_cmos_checksum(DeviceState *dev, void *opaque)
+{
+ uint16_t checksum = *(uint16_t *)opaque;
+ ISADevice *rtc;
+
+ if (object_dynamic_cast(OBJECT(dev), "mc146818rtc")) {
+ rtc = ISA_DEVICE(dev);
+ rtc_set_memory(rtc, 0x2e, checksum & 0xff);
+ rtc_set_memory(rtc, 0x3e, checksum & 0xff);
+ rtc_set_memory(rtc, 0x2f, checksum >> 8);
+ rtc_set_memory(rtc, 0x3f, checksum >> 8);
+ }
+ return 0;
+}
+
+static void ibm_40p_init(MachineState *machine)
+{
+ CPUPPCState *env = NULL;
+ uint16_t cmos_checksum;
+ PowerPCCPU *cpu;
+ DeviceState *dev;
+ SysBusDevice *pcihost;
+ Nvram *m48t59 = NULL;
+ PCIBus *pci_bus;
+ ISABus *isa_bus;
+ void *fw_cfg;
+ int i;
+ uint32_t kernel_base = 0, initrd_base = 0;
+ long kernel_size = 0, initrd_size = 0;
+ char boot_device;
+
+ /* init CPU */
+ if (!machine->cpu_model) {
+ machine->cpu_model = "604";
+ }
+ cpu = cpu_ppc_init(machine->cpu_model);
+ if (cpu == NULL) {
+ fprintf(stderr, "Unable to find PowerPC CPU definition\n");
+ exit(1);
+ }
+ env = &cpu->env;
+
+ if (env->flags & POWERPC_FLAG_RTC_CLK) {
+ /* POWER / PowerPC 601 RTC clock frequency is 7.8125 MHz */
+ cpu_ppc_tb_init(env, 7812500UL);
+ } else {
+ /* Set time-base frequency to 100 Mhz */
+ cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
+ }
+ qemu_register_reset(ppc_prep_reset, cpu);
+ if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
+ hw_error("Only 6xx bus is supported on PREP machine\n");
+ }
+
+ /* PCI host */
+ dev = qdev_create(NULL, "raven-pcihost");
+ if (!bios_name) {
+ bios_name = BIOS_FILENAME;
+ }
+ qdev_prop_set_string(dev, "bios-name", bios_name);
+ qdev_prop_set_uint32(dev, "elf-machine", PPC_ELF_MACHINE);
+ pcihost = SYS_BUS_DEVICE(dev);
+ object_property_add_child(qdev_get_machine(), "raven", OBJECT(dev), NULL);
+ qdev_init_nofail(dev);
+ pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci.0"));
+ if (pci_bus == NULL) {
+ fprintf(stderr, "Couldn't create PCI host controller.\n");
+ exit(1);
+ }
+
+ /* PCI -> ISA bridge */
+ dev = DEVICE(pci_create_simple(pci_bus, PCI_DEVFN(11, 0), "i82378"));
+ qdev_connect_gpio_out(dev, 0,
+ cpu->env.irq_inputs[PPC6xx_INPUT_INT]);
+ sysbus_connect_irq(pcihost, 0, qdev_get_gpio_in(dev, 15));
+ sysbus_connect_irq(pcihost, 1, qdev_get_gpio_in(dev, 13));
+ sysbus_connect_irq(pcihost, 2, qdev_get_gpio_in(dev, 15));
+ sysbus_connect_irq(pcihost, 3, qdev_get_gpio_in(dev, 13));
+ isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
+
+ /* Memory controller */
+ dev = DEVICE(isa_create(isa_bus, "rs6000-mc"));
+ qdev_prop_set_uint32(dev, "ram-size", machine->ram_size);
+ qdev_init_nofail(dev);
+
+ /* initialize CMOS checksums */
+ cmos_checksum = 0x6aa9;
+ qbus_walk_children(BUS(isa_bus), prep_set_cmos_checksum, NULL, NULL, NULL,
+ &cmos_checksum);
+
+ /* initialize audio subsystem */
+ audio_init();
+
+ /* add some more devices */
+ if (defaults_enabled()) {
+ isa_create_simple(isa_bus, "i8042");
+ m48t59 = NVRAM(isa_create_simple(isa_bus, "isa-m48t59"));
+
+ dev = DEVICE(isa_create(isa_bus, "cs4231a"));
+ qdev_prop_set_uint32(dev, "iobase", 0x830);
+ qdev_prop_set_uint32(dev, "irq", 10);
+ qdev_init_nofail(dev);
+
+ dev = DEVICE(isa_create(isa_bus, "pc87312"));
+ qdev_prop_set_uint32(dev, "config", 12);
+ qdev_init_nofail(dev);
+
+ dev = DEVICE(isa_create(isa_bus, "prep-systemio"));
+ qdev_prop_set_uint32(dev, "ibm-planar-id", 0xfc);
+ qdev_prop_set_uint32(dev, "equipment", 0xc0);
+ qdev_init_nofail(dev);
+
+ pci_create_simple(pci_bus, PCI_DEVFN(1, 0), "lsi53c810");
+
+ /* XXX: s3-trio at PCI_DEVFN(2, 0) */
+ pci_vga_init(pci_bus);
+
+ for (i = 0; i < nb_nics; i++) {
+ pci_nic_init_nofail(&nd_table[i], pci_bus, "pcnet",
+ i == 0 ? "3" : NULL);
+ }
+ }
+
+ /* Prepare firmware configuration for OpenBIOS */
+ fw_cfg = fw_cfg_init_mem(CFG_ADDR, CFG_ADDR + 2);
+
+ if (machine->kernel_filename) {
+ /* load kernel */
+ kernel_base = KERNEL_LOAD_ADDR;
+ kernel_size = load_image_targphys(machine->kernel_filename,
+ kernel_base,
+ machine->ram_size - kernel_base);
+ if (kernel_size < 0) {
+ error_report("could not load kernel '%s'",
+ machine->kernel_filename);
+ exit(1);
+ }
+ fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base);
+ fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
+ /* load initrd */
+ if (machine->initrd_filename) {
+ initrd_base = INITRD_LOAD_ADDR;
+ initrd_size = load_image_targphys(machine->initrd_filename,
+ initrd_base,
+ machine->ram_size - initrd_base);
+ if (initrd_size < 0) {
+ error_report("could not load initial ram disk '%s'",
+ machine->initrd_filename);
+ exit(1);
+ }
+ fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base);
+ fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
+ }
+ if (machine->kernel_cmdline && *machine->kernel_cmdline) {
+ fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
+ pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE,
+ machine->kernel_cmdline);
+ fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA,
+ machine->kernel_cmdline);
+ fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
+ strlen(machine->kernel_cmdline) + 1);
+ }
+ boot_device = 'm';
+ } else {
+ boot_device = machine->boot_order[0];
+ }
+
+ fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
+ fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size);
+ fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_PREP);
+
+ fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width);
+ fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height);
+ fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth);
+
+ fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled());
+ if (kvm_enabled()) {
+#ifdef CONFIG_KVM
+ uint8_t *hypercall;
+
+ fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, kvmppc_get_tbfreq());
+ hypercall = g_malloc(16);
+ kvmppc_get_hypercall(env, hypercall, 16);
+ fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16);
+ fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid());
+#endif
+ } else {
+ fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, NANOSECONDS_PER_SECOND);
+ }
+ fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device);
+ qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
+
+ /* Prepare firmware configuration for Open Hack'Ware */
+ if (m48t59) {
+ PPC_NVRAM_set_params(m48t59, NVRAM_SIZE, "PREP", ram_size,
+ boot_device,
+ kernel_base, kernel_size,
+ machine->kernel_cmdline,
+ initrd_base, initrd_size,
+ /* XXX: need an option to load a NVRAM image */
+ 0,
+ graphic_width, graphic_height, graphic_depth);
+ }
+}
+
+static void ibm_40p_machine_init(MachineClass *mc)
+{
+ mc->desc = "IBM RS/6000 7020 (40p)",
+ mc->init = ibm_40p_init;
+ mc->max_cpus = 1;
+ mc->pci_allow_0_address = true;
+ mc->default_ram_size = 128 * M_BYTE;
+ mc->block_default_type = IF_SCSI;
+ mc->default_boot_order = "c";
+}
+
+DEFINE_MACHINE("40p", ibm_40p_machine_init)
DEFINE_MACHINE("prep", prep_machine_init)
--
2.1.4
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [Qemu-devel] [PATCH v2 4/4] prep: add IBM RS/6000 7020 (40p) machine emulation
2017-01-05 21:56 ` [Qemu-devel] [PATCH v2 4/4] prep: add IBM RS/6000 7020 (40p) machine emulation Hervé Poussineau
@ 2017-01-05 23:21 ` David Gibson
2017-01-06 21:51 ` Hervé Poussineau
0 siblings, 1 reply; 9+ messages in thread
From: David Gibson @ 2017-01-05 23:21 UTC (permalink / raw)
To: Hervé Poussineau
Cc: qemu-devel, Alexander Graf, qemu-ppc, Thomas Huth,
Giancarlo Teodori
[-- Attachment #1: Type: text/plain, Size: 11804 bytes --]
On Thu, Jan 05, 2017 at 10:56:57PM +0100, Hervé Poussineau wrote:
> Machine supports both Open Hack'Ware and OpenBIOS.
> Open Hack'Ware is the default because OpenBIOS is currently unable to boot
> PReP boot partitions or PReP kernels.
>
> Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
> ---
> default-configs/ppc-softmmu.mak | 1 +
> hw/ppc/prep.c | 227 ++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 228 insertions(+)
>
> diff --git a/default-configs/ppc-softmmu.mak b/default-configs/ppc-softmmu.mak
> index e567658..7dd004e 100644
> --- a/default-configs/ppc-softmmu.mak
> +++ b/default-configs/ppc-softmmu.mak
> @@ -18,6 +18,7 @@ CONFIG_I82378=y
> CONFIG_PC87312=y
> CONFIG_MACIO=y
> CONFIG_PCSPK=y
> +CONFIG_CS4231A=y
> CONFIG_CUDA=y
> CONFIG_ADB=y
> CONFIG_MAC_NVRAM=y
> diff --git a/hw/ppc/prep.c b/hw/ppc/prep.c
> index 9fb89d3..ec252de 100644
> --- a/hw/ppc/prep.c
> +++ b/hw/ppc/prep.c
> @@ -2,6 +2,7 @@
> * QEMU PPC PREP hardware System Emulator
> *
> * Copyright (c) 2003-2007 Jocelyn Mayer
> + * Copyright (c) 2017 Hervé Poussineau
> *
> * Permission is hereby granted, free of charge, to any person obtaining a copy
> * of this software and associated documentation files (the "Software"), to deal
> @@ -43,6 +44,7 @@
> #include "hw/isa/pc87312.h"
> #include "sysemu/block-backend.h"
> #include "sysemu/arch_init.h"
> +#include "sysemu/kvm.h"
> #include "sysemu/qtest.h"
> #include "exec/address-spaces.h"
> #include "trace.h"
> @@ -54,6 +56,8 @@
>
> #define MAX_IDE_BUS 2
>
> +#define CFG_ADDR 0xf0000510
> +
> #define BIOS_SIZE (1024 * 1024)
> #define BIOS_FILENAME "ppc_rom.bin"
> #define KERNEL_LOAD_ADDR 0x01000000
> @@ -316,6 +320,12 @@ static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr)
>
> #define NVRAM_SIZE 0x2000
>
> +static void fw_cfg_boot_set(void *opaque, const char *boot_device,
> + Error **errp)
> +{
> + fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
> +}
> +
> static void ppc_prep_reset(void *opaque)
> {
> PowerPCCPU *cpu = opaque;
> @@ -677,4 +687,221 @@ static void prep_machine_init(MachineClass *mc)
> mc->default_boot_order = "cad";
> }
>
> +static int prep_set_cmos_checksum(DeviceState *dev, void *opaque)
> +{
> + uint16_t checksum = *(uint16_t *)opaque;
> + ISADevice *rtc;
> +
> + if (object_dynamic_cast(OBJECT(dev), "mc146818rtc")) {
> + rtc = ISA_DEVICE(dev);
> + rtc_set_memory(rtc, 0x2e, checksum & 0xff);
> + rtc_set_memory(rtc, 0x3e, checksum & 0xff);
> + rtc_set_memory(rtc, 0x2f, checksum >> 8);
> + rtc_set_memory(rtc, 0x3f, checksum >> 8);
> + }
> + return 0;
> +}
> +
> +static void ibm_40p_init(MachineState *machine)
> +{
> + CPUPPCState *env = NULL;
> + uint16_t cmos_checksum;
> + PowerPCCPU *cpu;
> + DeviceState *dev;
> + SysBusDevice *pcihost;
> + Nvram *m48t59 = NULL;
> + PCIBus *pci_bus;
> + ISABus *isa_bus;
> + void *fw_cfg;
> + int i;
> + uint32_t kernel_base = 0, initrd_base = 0;
> + long kernel_size = 0, initrd_size = 0;
> + char boot_device;
> +
> + /* init CPU */
> + if (!machine->cpu_model) {
> + machine->cpu_model = "604";
> + }
> + cpu = cpu_ppc_init(machine->cpu_model);
> + if (cpu == NULL) {
> + fprintf(stderr, "Unable to find PowerPC CPU definition\n");
Please use error_report() rather than direct fprintf().
> + exit(1);
> + }
> + env = &cpu->env;
> +
> + if (env->flags & POWERPC_FLAG_RTC_CLK) {
> + /* POWER / PowerPC 601 RTC clock frequency is 7.8125 MHz */
> + cpu_ppc_tb_init(env, 7812500UL);
> + } else {
> + /* Set time-base frequency to 100 Mhz */
> + cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
> + }
> + qemu_register_reset(ppc_prep_reset, cpu);
> + if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
> + hw_error("Only 6xx bus is supported on PREP machine\n");
This is essentially a configuration error (selecting an unsuitable cpu
for the platform. So it should be an error_report() + exit() rather
than hw_error(). I'd also suggest moving up to immediately after the
cpu initialization.
> + }
> +
> + /* PCI host */
> + dev = qdev_create(NULL, "raven-pcihost");
> + if (!bios_name) {
> + bios_name = BIOS_FILENAME;
> + }
> + qdev_prop_set_string(dev, "bios-name", bios_name);
> + qdev_prop_set_uint32(dev, "elf-machine", PPC_ELF_MACHINE);
> + pcihost = SYS_BUS_DEVICE(dev);
> + object_property_add_child(qdev_get_machine(), "raven", OBJECT(dev), NULL);
> + qdev_init_nofail(dev);
> + pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci.0"));
> + if (pci_bus == NULL) {
> + fprintf(stderr, "Couldn't create PCI host controller.\n");
> + exit(1);
> + }
> +
> + /* PCI -> ISA bridge */
> + dev = DEVICE(pci_create_simple(pci_bus, PCI_DEVFN(11, 0), "i82378"));
> + qdev_connect_gpio_out(dev, 0,
> + cpu->env.irq_inputs[PPC6xx_INPUT_INT]);
> + sysbus_connect_irq(pcihost, 0, qdev_get_gpio_in(dev, 15));
> + sysbus_connect_irq(pcihost, 1, qdev_get_gpio_in(dev, 13));
> + sysbus_connect_irq(pcihost, 2, qdev_get_gpio_in(dev, 15));
> + sysbus_connect_irq(pcihost, 3, qdev_get_gpio_in(dev, 13));
> + isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
> +
> + /* Memory controller */
> + dev = DEVICE(isa_create(isa_bus, "rs6000-mc"));
> + qdev_prop_set_uint32(dev, "ram-size", machine->ram_size);
> + qdev_init_nofail(dev);
> +
> + /* initialize CMOS checksums */
> + cmos_checksum = 0x6aa9;
> + qbus_walk_children(BUS(isa_bus), prep_set_cmos_checksum, NULL, NULL, NULL,
> + &cmos_checksum);
> +
> + /* initialize audio subsystem */
> + audio_init();
> +
> + /* add some more devices */
> + if (defaults_enabled()) {
> + isa_create_simple(isa_bus, "i8042");
> + m48t59 = NVRAM(isa_create_simple(isa_bus, "isa-m48t59"));
> +
> + dev = DEVICE(isa_create(isa_bus, "cs4231a"));
> + qdev_prop_set_uint32(dev, "iobase", 0x830);
> + qdev_prop_set_uint32(dev, "irq", 10);
> + qdev_init_nofail(dev);
> +
> + dev = DEVICE(isa_create(isa_bus, "pc87312"));
> + qdev_prop_set_uint32(dev, "config", 12);
> + qdev_init_nofail(dev);
> +
> + dev = DEVICE(isa_create(isa_bus, "prep-systemio"));
> + qdev_prop_set_uint32(dev, "ibm-planar-id", 0xfc);
> + qdev_prop_set_uint32(dev, "equipment", 0xc0);
> + qdev_init_nofail(dev);
> +
> + pci_create_simple(pci_bus, PCI_DEVFN(1, 0), "lsi53c810");
> +
> + /* XXX: s3-trio at PCI_DEVFN(2, 0) */
> + pci_vga_init(pci_bus);
> +
> + for (i = 0; i < nb_nics; i++) {
> + pci_nic_init_nofail(&nd_table[i], pci_bus, "pcnet",
> + i == 0 ? "3" : NULL);
> + }
> + }
> +
> + /* Prepare firmware configuration for OpenBIOS */
> + fw_cfg = fw_cfg_init_mem(CFG_ADDR, CFG_ADDR + 2);
> +
> + if (machine->kernel_filename) {
> + /* load kernel */
> + kernel_base = KERNEL_LOAD_ADDR;
> + kernel_size = load_image_targphys(machine->kernel_filename,
> + kernel_base,
> + machine->ram_size - kernel_base);
> + if (kernel_size < 0) {
> + error_report("could not load kernel '%s'",
> + machine->kernel_filename);
> + exit(1);
> + }
> + fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base);
> + fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
> + /* load initrd */
> + if (machine->initrd_filename) {
> + initrd_base = INITRD_LOAD_ADDR;
> + initrd_size = load_image_targphys(machine->initrd_filename,
> + initrd_base,
> + machine->ram_size - initrd_base);
> + if (initrd_size < 0) {
> + error_report("could not load initial ram disk '%s'",
> + machine->initrd_filename);
> + exit(1);
> + }
> + fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base);
> + fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
> + }
> + if (machine->kernel_cmdline && *machine->kernel_cmdline) {
> + fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
> + pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE,
> + machine->kernel_cmdline);
> + fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA,
> + machine->kernel_cmdline);
> + fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
> + strlen(machine->kernel_cmdline) + 1);
> + }
> + boot_device = 'm';
> + } else {
> + boot_device = machine->boot_order[0];
> + }
> +
> + fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
> + fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size);
> + fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_PREP);
> +
> + fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width);
> + fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height);
> + fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth);
> +
> + fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled());
> + if (kvm_enabled()) {
> +#ifdef CONFIG_KVM
> + uint8_t *hypercall;
> +
> + fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, kvmppc_get_tbfreq());
> + hypercall = g_malloc(16);
> + kvmppc_get_hypercall(env, hypercall, 16);
> + fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16);
> + fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid());
> +#endif
> + } else {
> + fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, NANOSECONDS_PER_SECOND);
> + }
> + fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device);
> + qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
> +
> + /* Prepare firmware configuration for Open Hack'Ware */
> + if (m48t59) {
> + PPC_NVRAM_set_params(m48t59, NVRAM_SIZE, "PREP", ram_size,
> + boot_device,
> + kernel_base, kernel_size,
> + machine->kernel_cmdline,
> + initrd_base, initrd_size,
> + /* XXX: need an option to load a NVRAM image */
> + 0,
> + graphic_width, graphic_height, graphic_depth);
Doesn't this mean the system can't possibly boot without the m48t59?
In which case shouldn't it be created even with -nodefaults?
> + }
> +}
> +
> +static void ibm_40p_machine_init(MachineClass *mc)
> +{
> + mc->desc = "IBM RS/6000 7020 (40p)",
> + mc->init = ibm_40p_init;
> + mc->max_cpus = 1;
> + mc->pci_allow_0_address = true;
> + mc->default_ram_size = 128 * M_BYTE;
> + mc->block_default_type = IF_SCSI;
> + mc->default_boot_order = "c";
> +}
> +
> +DEFINE_MACHINE("40p", ibm_40p_machine_init)
> DEFINE_MACHINE("prep", prep_machine_init)
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [Qemu-devel] [PATCH v2 4/4] prep: add IBM RS/6000 7020 (40p) machine emulation
2017-01-05 23:21 ` David Gibson
@ 2017-01-06 21:51 ` Hervé Poussineau
0 siblings, 0 replies; 9+ messages in thread
From: Hervé Poussineau @ 2017-01-06 21:51 UTC (permalink / raw)
To: David Gibson
Cc: qemu-devel, Alexander Graf, qemu-ppc, Thomas Huth,
Giancarlo Teodori
Le 06/01/2017 à 00:21, David Gibson a écrit :
> On Thu, Jan 05, 2017 at 10:56:57PM +0100, Hervé Poussineau wrote:
>> Machine supports both Open Hack'Ware and OpenBIOS.
>> Open Hack'Ware is the default because OpenBIOS is currently unable to boot
>> PReP boot partitions or PReP kernels.
>>
>> Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
>> ---
>> default-configs/ppc-softmmu.mak | 1 +
>> hw/ppc/prep.c | 227 ++++++++++++++++++++++++++++++++++++++++
>> 2 files changed, 228 insertions(+)
>>
>> diff --git a/default-configs/ppc-softmmu.mak b/default-configs/ppc-softmmu.mak
>> index e567658..7dd004e 100644
>> --- a/default-configs/ppc-softmmu.mak
>> +++ b/default-configs/ppc-softmmu.mak
>> @@ -18,6 +18,7 @@ CONFIG_I82378=y
>> CONFIG_PC87312=y
>> CONFIG_MACIO=y
>> CONFIG_PCSPK=y
>> +CONFIG_CS4231A=y
>> CONFIG_CUDA=y
>> CONFIG_ADB=y
>> CONFIG_MAC_NVRAM=y
>> diff --git a/hw/ppc/prep.c b/hw/ppc/prep.c
>> index 9fb89d3..ec252de 100644
>> --- a/hw/ppc/prep.c
>> +++ b/hw/ppc/prep.c
>> @@ -2,6 +2,7 @@
>> * QEMU PPC PREP hardware System Emulator
>> *
>> * Copyright (c) 2003-2007 Jocelyn Mayer
>> + * Copyright (c) 2017 Hervé Poussineau
>> *
>> * Permission is hereby granted, free of charge, to any person obtaining a copy
>> * of this software and associated documentation files (the "Software"), to deal
>> @@ -43,6 +44,7 @@
>> #include "hw/isa/pc87312.h"
>> #include "sysemu/block-backend.h"
>> #include "sysemu/arch_init.h"
>> +#include "sysemu/kvm.h"
>> #include "sysemu/qtest.h"
>> #include "exec/address-spaces.h"
>> #include "trace.h"
>> @@ -54,6 +56,8 @@
>>
>> #define MAX_IDE_BUS 2
>>
>> +#define CFG_ADDR 0xf0000510
>> +
>> #define BIOS_SIZE (1024 * 1024)
>> #define BIOS_FILENAME "ppc_rom.bin"
>> #define KERNEL_LOAD_ADDR 0x01000000
>> @@ -316,6 +320,12 @@ static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr)
>>
>> #define NVRAM_SIZE 0x2000
>>
>> +static void fw_cfg_boot_set(void *opaque, const char *boot_device,
>> + Error **errp)
>> +{
>> + fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
>> +}
>> +
>> static void ppc_prep_reset(void *opaque)
>> {
>> PowerPCCPU *cpu = opaque;
>> @@ -677,4 +687,221 @@ static void prep_machine_init(MachineClass *mc)
>> mc->default_boot_order = "cad";
>> }
>>
>> +static int prep_set_cmos_checksum(DeviceState *dev, void *opaque)
>> +{
>> + uint16_t checksum = *(uint16_t *)opaque;
>> + ISADevice *rtc;
>> +
>> + if (object_dynamic_cast(OBJECT(dev), "mc146818rtc")) {
>> + rtc = ISA_DEVICE(dev);
>> + rtc_set_memory(rtc, 0x2e, checksum & 0xff);
>> + rtc_set_memory(rtc, 0x3e, checksum & 0xff);
>> + rtc_set_memory(rtc, 0x2f, checksum >> 8);
>> + rtc_set_memory(rtc, 0x3f, checksum >> 8);
>> + }
>> + return 0;
>> +}
>> +
>> +static void ibm_40p_init(MachineState *machine)
>> +{
>> + CPUPPCState *env = NULL;
>> + uint16_t cmos_checksum;
>> + PowerPCCPU *cpu;
>> + DeviceState *dev;
>> + SysBusDevice *pcihost;
>> + Nvram *m48t59 = NULL;
>> + PCIBus *pci_bus;
>> + ISABus *isa_bus;
>> + void *fw_cfg;
>> + int i;
>> + uint32_t kernel_base = 0, initrd_base = 0;
>> + long kernel_size = 0, initrd_size = 0;
>> + char boot_device;
>> +
>> + /* init CPU */
>> + if (!machine->cpu_model) {
>> + machine->cpu_model = "604";
>> + }
>> + cpu = cpu_ppc_init(machine->cpu_model);
>> + if (cpu == NULL) {
>> + fprintf(stderr, "Unable to find PowerPC CPU definition\n");
>
> Please use error_report() rather than direct fprintf().
OK
>
>> + exit(1);
>> + }
>> + env = &cpu->env;
>> +
>> + if (env->flags & POWERPC_FLAG_RTC_CLK) {
>> + /* POWER / PowerPC 601 RTC clock frequency is 7.8125 MHz */
>> + cpu_ppc_tb_init(env, 7812500UL);
>> + } else {
>> + /* Set time-base frequency to 100 Mhz */
>> + cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
>> + }
>> + qemu_register_reset(ppc_prep_reset, cpu);
>> + if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
>> + hw_error("Only 6xx bus is supported on PREP machine\n");
>
> This is essentially a configuration error (selecting an unsuitable cpu
> for the platform. So it should be an error_report() + exit() rather
> than hw_error(). I'd also suggest moving up to immediately after the
> cpu initialization.
OK, will move it up, just after env variable assignation.
>
>> + }
>> +
>> + /* PCI host */
>> + dev = qdev_create(NULL, "raven-pcihost");
>> + if (!bios_name) {
>> + bios_name = BIOS_FILENAME;
>> + }
>> + qdev_prop_set_string(dev, "bios-name", bios_name);
>> + qdev_prop_set_uint32(dev, "elf-machine", PPC_ELF_MACHINE);
>> + pcihost = SYS_BUS_DEVICE(dev);
>> + object_property_add_child(qdev_get_machine(), "raven", OBJECT(dev), NULL);
>> + qdev_init_nofail(dev);
>> + pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci.0"));
>> + if (pci_bus == NULL) {
>> + fprintf(stderr, "Couldn't create PCI host controller.\n");
>> + exit(1);
>> + }
>> +
>> + /* PCI -> ISA bridge */
>> + dev = DEVICE(pci_create_simple(pci_bus, PCI_DEVFN(11, 0), "i82378"));
>> + qdev_connect_gpio_out(dev, 0,
>> + cpu->env.irq_inputs[PPC6xx_INPUT_INT]);
>> + sysbus_connect_irq(pcihost, 0, qdev_get_gpio_in(dev, 15));
>> + sysbus_connect_irq(pcihost, 1, qdev_get_gpio_in(dev, 13));
>> + sysbus_connect_irq(pcihost, 2, qdev_get_gpio_in(dev, 15));
>> + sysbus_connect_irq(pcihost, 3, qdev_get_gpio_in(dev, 13));
>> + isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
>> +
>> + /* Memory controller */
>> + dev = DEVICE(isa_create(isa_bus, "rs6000-mc"));
>> + qdev_prop_set_uint32(dev, "ram-size", machine->ram_size);
>> + qdev_init_nofail(dev);
>> +
>> + /* initialize CMOS checksums */
>> + cmos_checksum = 0x6aa9;
>> + qbus_walk_children(BUS(isa_bus), prep_set_cmos_checksum, NULL, NULL, NULL,
>> + &cmos_checksum);
>> +
>> + /* initialize audio subsystem */
>> + audio_init();
>> +
>> + /* add some more devices */
>> + if (defaults_enabled()) {
>> + isa_create_simple(isa_bus, "i8042");
>> + m48t59 = NVRAM(isa_create_simple(isa_bus, "isa-m48t59"));
>> +
>> + dev = DEVICE(isa_create(isa_bus, "cs4231a"));
>> + qdev_prop_set_uint32(dev, "iobase", 0x830);
>> + qdev_prop_set_uint32(dev, "irq", 10);
>> + qdev_init_nofail(dev);
>> +
>> + dev = DEVICE(isa_create(isa_bus, "pc87312"));
>> + qdev_prop_set_uint32(dev, "config", 12);
>> + qdev_init_nofail(dev);
>> +
>> + dev = DEVICE(isa_create(isa_bus, "prep-systemio"));
>> + qdev_prop_set_uint32(dev, "ibm-planar-id", 0xfc);
>> + qdev_prop_set_uint32(dev, "equipment", 0xc0);
>> + qdev_init_nofail(dev);
>> +
>> + pci_create_simple(pci_bus, PCI_DEVFN(1, 0), "lsi53c810");
>> +
>> + /* XXX: s3-trio at PCI_DEVFN(2, 0) */
>> + pci_vga_init(pci_bus);
>> +
>> + for (i = 0; i < nb_nics; i++) {
>> + pci_nic_init_nofail(&nd_table[i], pci_bus, "pcnet",
>> + i == 0 ? "3" : NULL);
>> + }
>> + }
>> +
>> + /* Prepare firmware configuration for OpenBIOS */
>> + fw_cfg = fw_cfg_init_mem(CFG_ADDR, CFG_ADDR + 2);
>> +
>> + if (machine->kernel_filename) {
>> + /* load kernel */
>> + kernel_base = KERNEL_LOAD_ADDR;
>> + kernel_size = load_image_targphys(machine->kernel_filename,
>> + kernel_base,
>> + machine->ram_size - kernel_base);
>> + if (kernel_size < 0) {
>> + error_report("could not load kernel '%s'",
>> + machine->kernel_filename);
>> + exit(1);
>> + }
>> + fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base);
>> + fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
>> + /* load initrd */
>> + if (machine->initrd_filename) {
>> + initrd_base = INITRD_LOAD_ADDR;
>> + initrd_size = load_image_targphys(machine->initrd_filename,
>> + initrd_base,
>> + machine->ram_size - initrd_base);
>> + if (initrd_size < 0) {
>> + error_report("could not load initial ram disk '%s'",
>> + machine->initrd_filename);
>> + exit(1);
>> + }
>> + fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base);
>> + fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
>> + }
>> + if (machine->kernel_cmdline && *machine->kernel_cmdline) {
>> + fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
>> + pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE,
>> + machine->kernel_cmdline);
>> + fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA,
>> + machine->kernel_cmdline);
>> + fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
>> + strlen(machine->kernel_cmdline) + 1);
>> + }
>> + boot_device = 'm';
>> + } else {
>> + boot_device = machine->boot_order[0];
>> + }
>> +
>> + fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
>> + fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size);
>> + fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_PREP);
>> +
>> + fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width);
>> + fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height);
>> + fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth);
>> +
>> + fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled());
>> + if (kvm_enabled()) {
>> +#ifdef CONFIG_KVM
>> + uint8_t *hypercall;
>> +
>> + fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, kvmppc_get_tbfreq());
>> + hypercall = g_malloc(16);
>> + kvmppc_get_hypercall(env, hypercall, 16);
>> + fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16);
>> + fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid());
>> +#endif
>> + } else {
>> + fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, NANOSECONDS_PER_SECOND);
>> + }
>> + fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device);
>> + qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
>> +
>> + /* Prepare firmware configuration for Open Hack'Ware */
>> + if (m48t59) {
>> + PPC_NVRAM_set_params(m48t59, NVRAM_SIZE, "PREP", ram_size,
>> + boot_device,
>> + kernel_base, kernel_size,
>> + machine->kernel_cmdline,
>> + initrd_base, initrd_size,
>> + /* XXX: need an option to load a NVRAM image */
>> + 0,
>> + graphic_width, graphic_height, graphic_depth);
>
> Doesn't this mean the system can't possibly boot without the m48t59?
> In which case shouldn't it be created even with -nodefaults?
m48t59 nvram is required for Open Hack'Ware.
However, 40p can also use OpenBIOS as an alternative. OpenBIOS uses the mc146818rtc nvram, which is always created and initializated.
I hope that we can remove the m48t59 if we change the default 40p firmware from Open Hack'Ware to OpenBIOS.
>
>> + }
>> +}
>> +
>> +static void ibm_40p_machine_init(MachineClass *mc)
>> +{
>> + mc->desc = "IBM RS/6000 7020 (40p)",
>> + mc->init = ibm_40p_init;
>> + mc->max_cpus = 1;
>> + mc->pci_allow_0_address = true;
>> + mc->default_ram_size = 128 * M_BYTE;
>> + mc->block_default_type = IF_SCSI;
>> + mc->default_boot_order = "c";
>> +}
>> +
>> +DEFINE_MACHINE("40p", ibm_40p_machine_init)
>> DEFINE_MACHINE("prep", prep_machine_init)
>
^ permalink raw reply [flat|nested] 9+ messages in thread