From: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
To: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, rth@twiddle.net
Cc: qemu-devel@nongnu.org, bharata@linux.vnet.ibm.com,
nikunj@linux.vnet.ibm.com
Subject: [Qemu-devel] [PATCH v1 02/14] target-ppc: Add xxinsertw instruction
Date: Fri, 6 Jan 2017 11:44:44 +0530 [thread overview]
Message-ID: <1483683296-32568-3-git-send-email-nikunj@linux.vnet.ibm.com> (raw)
In-Reply-To: <1483683296-32568-1-git-send-email-nikunj@linux.vnet.ibm.com>
xxinsertw: VSX Vector Insert Word
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
target/ppc/helper.h | 1 +
target/ppc/int_helper.c | 25 +++++++++++++++++++++++++
target/ppc/translate/vsx-impl.inc.c | 5 +++--
target/ppc/translate/vsx-ops.inc.c | 1 +
4 files changed, 30 insertions(+), 2 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 8b30420..6c5b194 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -541,6 +541,7 @@ DEF_HELPER_2(xvrspiz, void, env, i32)
DEF_HELPER_2(xxperm, void, env, i32)
DEF_HELPER_2(xxpermr, void, env, i32)
DEF_HELPER_4(xxextractuw, void, env, tl, tl, i32)
+DEF_HELPER_4(xxinsertw, void, env, tl, tl, i32)
DEF_HELPER_2(efscfsi, i32, env, i32)
DEF_HELPER_2(efscfui, i32, env, i32)
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index 63ba0e3..24e5964 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -2059,6 +2059,31 @@ void helper_xxextractuw(CPUPPCState *env, target_ulong xtn,
putVSR(xtn, &xt, env);
}
+void helper_xxinsertw(CPUPPCState *env, target_ulong xtn,
+ target_ulong xbn, uint32_t index)
+{
+ ppc_vsr_t xt, xb;
+ size_t es = sizeof(uint32_t);
+ int ins_index, i = 0;
+
+ getVSR(xbn, &xb, env);
+ getVSR(xtn, &xt, env);
+
+#if defined(HOST_WORDS_BIGENDIAN)
+ ins_index = index;
+ for (i = 0; i < es && ins_index < 16; i++, ins_index++) {
+ xt.u8[ins_index] = xb.u8[8 - es + i];
+ }
+#else
+ ins_index = 15 - index;
+ for (i = es - 1; i >= 0 && ins_index >= 0; i--, ins_index--) {
+ xt.u8[ins_index] = xb.u8[8 + i];
+ }
+#endif
+
+ putVSR(xtn, &xt, env);
+}
+
#define VEXT_SIGNED(name, element, mask, cast, recast) \
void helper_##name(ppc_avr_t *r, ppc_avr_t *b) \
{ \
diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c
index 7977f24..c9ba0f5 100644
--- a/target/ppc/translate/vsx-impl.inc.c
+++ b/target/ppc/translate/vsx-impl.inc.c
@@ -1180,7 +1180,7 @@ static void gen_xxsldwi(DisasContext *ctx)
tcg_temp_free_i64(xtl);
}
-#define VSX_EXTRACT(name) \
+#define VSX_EXTRACT_INSERT(name) \
static void gen_##name(DisasContext *ctx) \
{ \
TCGv xt, xb; \
@@ -1208,7 +1208,8 @@ static void gen_##name(DisasContext *ctx) \
tcg_temp_free_i32(t0); \
}
-VSX_EXTRACT(xxextractuw)
+VSX_EXTRACT_INSERT(xxextractuw)
+VSX_EXTRACT_INSERT(xxinsertw)
#undef GEN_XX2FORM
#undef GEN_XX3FORM
diff --git a/target/ppc/translate/vsx-ops.inc.c b/target/ppc/translate/vsx-ops.inc.c
index 473d925..096d358 100644
--- a/target/ppc/translate/vsx-ops.inc.c
+++ b/target/ppc/translate/vsx-ops.inc.c
@@ -285,6 +285,7 @@ GEN_XX2FORM(xxspltw, 0x08, 0x0A, PPC2_VSX),
GEN_XX1FORM(xxspltib, 0x08, 0x0B, PPC2_ISA300),
GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00),
GEN_XX2FORM_EXT(xxextractuw, 0x0A, 0x0A, PPC2_ISA300),
+GEN_XX2FORM_EXT(xxinsertw, 0x0A, 0x0B, PPC2_ISA300),
#define GEN_XXSEL_ROW(opc3) \
GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x18, opc3, 0, PPC_NONE, PPC2_VSX), \
--
2.7.4
next prev parent reply other threads:[~2017-01-06 6:15 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-01-06 6:14 [Qemu-devel] [PATCH v1 00/14] POWER9 TCG enablements - part10 Nikunj A Dadhania
2017-01-06 6:14 ` [Qemu-devel] [PATCH v1 01/14] target-ppc: Add xxextractuw instruction Nikunj A Dadhania
2017-01-06 6:14 ` Nikunj A Dadhania [this message]
2017-01-06 7:54 ` [Qemu-devel] [PATCH v1 02/14] target-ppc: Add xxinsertw instruction David Gibson
2017-01-06 8:28 ` Nikunj A Dadhania
2017-01-07 1:02 ` David Gibson
2017-01-07 1:03 ` David Gibson
2017-01-06 6:14 ` [Qemu-devel] [PATCH v1 03/14] target-ppc: Use float64 arg in helper_compute_fprf() Nikunj A Dadhania
2017-01-06 6:14 ` [Qemu-devel] [PATCH v1 04/14] target-ppc: Replace isden by float64_is_zero_or_denormal Nikunj A Dadhania
2017-01-06 6:14 ` [Qemu-devel] [PATCH v1 05/14] target-ppc: Rename helper_compute_fprf to helper_compute_fprf_float64 Nikunj A Dadhania
2017-01-06 6:14 ` [Qemu-devel] [PATCH v1 06/14] target-ppc: Add xsaddqp instructions Nikunj A Dadhania
2017-01-06 6:14 ` [Qemu-devel] [PATCH v1 07/14] target-ppc: Add xscvdphp, xscvhpdp Nikunj A Dadhania
2017-01-06 6:14 ` [Qemu-devel] [PATCH v1 08/14] target-ppc: Use correct precision for FPRF setting Nikunj A Dadhania
2017-01-06 6:14 ` [Qemu-devel] [PATCH v1 09/14] target-ppc: Add xscvdpqp instruction Nikunj A Dadhania
2017-01-06 6:14 ` [Qemu-devel] [PATCH v1 10/14] target-ppc: Add xscvqpdp instruction Nikunj A Dadhania
2017-01-06 6:14 ` [Qemu-devel] [PATCH v1 11/14] target-ppc: Add xsxexpdp instruction Nikunj A Dadhania
2017-01-06 6:14 ` [Qemu-devel] [PATCH v1 12/14] target-ppc: Add xsxexpqp instruction Nikunj A Dadhania
2017-01-06 6:14 ` [Qemu-devel] [PATCH v1 13/14] target-ppc: Add xsxsigdp instruction Nikunj A Dadhania
2017-01-06 6:14 ` [Qemu-devel] [PATCH v1 14/14] target-ppc: Add xsxsigqp instructions Nikunj A Dadhania
2017-01-09 2:49 ` [Qemu-devel] [PATCH v1 00/14] POWER9 TCG enablements - part10 David Gibson
2017-01-09 6:51 ` Nikunj A Dadhania
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