* [Qemu-devel] [PATCH v1 01/14] target-ppc: Add xxextractuw instruction
2017-01-06 6:14 [Qemu-devel] [PATCH v1 00/14] POWER9 TCG enablements - part10 Nikunj A Dadhania
@ 2017-01-06 6:14 ` Nikunj A Dadhania
2017-01-06 6:14 ` [Qemu-devel] [PATCH v1 02/14] target-ppc: Add xxinsertw instruction Nikunj A Dadhania
` (13 subsequent siblings)
14 siblings, 0 replies; 21+ messages in thread
From: Nikunj A Dadhania @ 2017-01-06 6:14 UTC (permalink / raw)
To: qemu-ppc, david, rth; +Cc: qemu-devel, bharata, nikunj
xxextractuw: VSX Vector Extract Unsigned Word
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
target/ppc/helper.h | 1 +
target/ppc/int_helper.c | 26 ++++++++++++++++++++++++++
target/ppc/translate/vsx-impl.inc.c | 30 ++++++++++++++++++++++++++++++
target/ppc/translate/vsx-ops.inc.c | 5 +++++
4 files changed, 62 insertions(+)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 4707db4..8b30420 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -540,6 +540,7 @@ DEF_HELPER_2(xvrspip, void, env, i32)
DEF_HELPER_2(xvrspiz, void, env, i32)
DEF_HELPER_2(xxperm, void, env, i32)
DEF_HELPER_2(xxpermr, void, env, i32)
+DEF_HELPER_4(xxextractuw, void, env, tl, tl, i32)
DEF_HELPER_2(efscfsi, i32, env, i32)
DEF_HELPER_2(efscfui, i32, env, i32)
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index 2bb628f..63ba0e3 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -2033,6 +2033,32 @@ VEXTRACT(uw, u32)
VEXTRACT(d, u64)
#undef VEXTRACT
+void helper_xxextractuw(CPUPPCState *env, target_ulong xtn,
+ target_ulong xbn, uint32_t index)
+{
+ ppc_vsr_t xt, xb;
+ size_t es = sizeof(uint32_t);
+ uint32_t ext_index;
+ int i;
+
+ getVSR(xbn, &xb, env);
+ memset(&xt, 0, sizeof(xt));
+
+#if defined(HOST_WORDS_BIGENDIAN)
+ ext_index = index;
+ for (i = 0; i < es; i++, ext_index++) {
+ xt.u8[8 - es + i] = xb.u8[ext_index % 16];
+ }
+#else
+ ext_index = 15 - index;
+ for (i = es - 1; i >= 0; i--, ext_index--) {
+ xt.u8[8 + i] = xb.u8[ext_index % 16];
+ }
+#endif
+
+ putVSR(xtn, &xt, env);
+}
+
#define VEXT_SIGNED(name, element, mask, cast, recast) \
void helper_##name(ppc_avr_t *r, ppc_avr_t *b) \
{ \
diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c
index 2a17c35..7977f24 100644
--- a/target/ppc/translate/vsx-impl.inc.c
+++ b/target/ppc/translate/vsx-impl.inc.c
@@ -1180,6 +1180,36 @@ static void gen_xxsldwi(DisasContext *ctx)
tcg_temp_free_i64(xtl);
}
+#define VSX_EXTRACT(name) \
+static void gen_##name(DisasContext *ctx) \
+{ \
+ TCGv xt, xb; \
+ TCGv_i32 t0 = tcg_temp_new_i32(); \
+ uint8_t uimm = UIMM4(ctx->opcode); \
+ \
+ if (unlikely(!ctx->vsx_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VSXU); \
+ return; \
+ } \
+ xt = tcg_const_tl(xT(ctx->opcode)); \
+ xb = tcg_const_tl(xB(ctx->opcode)); \
+ /* uimm > 15 out of bound and for \
+ * uimm > 12 handle as per hardware in helper \
+ */ \
+ if (uimm > 15) { \
+ tcg_gen_movi_i64(cpu_vsrh(xT(ctx->opcode)), 0); \
+ tcg_gen_movi_i64(cpu_vsrl(xT(ctx->opcode)), 0); \
+ return; \
+ } \
+ tcg_gen_movi_i32(t0, uimm); \
+ gen_helper_##name(cpu_env, xt, xb, t0); \
+ tcg_temp_free(xb); \
+ tcg_temp_free(xt); \
+ tcg_temp_free_i32(t0); \
+}
+
+VSX_EXTRACT(xxextractuw)
+
#undef GEN_XX2FORM
#undef GEN_XX3FORM
#undef GEN_XX2IFORM
diff --git a/target/ppc/translate/vsx-ops.inc.c b/target/ppc/translate/vsx-ops.inc.c
index 46b95e3..473d925 100644
--- a/target/ppc/translate/vsx-ops.inc.c
+++ b/target/ppc/translate/vsx-ops.inc.c
@@ -49,6 +49,10 @@ GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2)
GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2)
+#define GEN_XX2FORM_EXT(name, opc2, opc3, fl2) \
+GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0x00100000, PPC_NONE, fl2), \
+GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0x00100000, PPC_NONE, fl2)
+
#define GEN_XX2FORM_EO(name, opc2, opc3, opc4, fl2) \
GEN_HANDLER2_E_2(name, #name, 0x3C, opc2 | 0, opc3, opc4, 0, PPC_NONE, fl2), \
GEN_HANDLER2_E_2(name, #name, 0x3C, opc2 | 1, opc3, opc4, 0, PPC_NONE, fl2)
@@ -280,6 +284,7 @@ GEN_XX3FORM(xxpermr, 0x08, 0x07, PPC2_ISA300),
GEN_XX2FORM(xxspltw, 0x08, 0x0A, PPC2_VSX),
GEN_XX1FORM(xxspltib, 0x08, 0x0B, PPC2_ISA300),
GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00),
+GEN_XX2FORM_EXT(xxextractuw, 0x0A, 0x0A, PPC2_ISA300),
#define GEN_XXSEL_ROW(opc3) \
GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x18, opc3, 0, PPC_NONE, PPC2_VSX), \
--
2.7.4
^ permalink raw reply related [flat|nested] 21+ messages in thread* [Qemu-devel] [PATCH v1 02/14] target-ppc: Add xxinsertw instruction
2017-01-06 6:14 [Qemu-devel] [PATCH v1 00/14] POWER9 TCG enablements - part10 Nikunj A Dadhania
2017-01-06 6:14 ` [Qemu-devel] [PATCH v1 01/14] target-ppc: Add xxextractuw instruction Nikunj A Dadhania
@ 2017-01-06 6:14 ` Nikunj A Dadhania
2017-01-06 7:54 ` David Gibson
2017-01-07 1:03 ` David Gibson
2017-01-06 6:14 ` [Qemu-devel] [PATCH v1 03/14] target-ppc: Use float64 arg in helper_compute_fprf() Nikunj A Dadhania
` (12 subsequent siblings)
14 siblings, 2 replies; 21+ messages in thread
From: Nikunj A Dadhania @ 2017-01-06 6:14 UTC (permalink / raw)
To: qemu-ppc, david, rth; +Cc: qemu-devel, bharata, nikunj
xxinsertw: VSX Vector Insert Word
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
target/ppc/helper.h | 1 +
target/ppc/int_helper.c | 25 +++++++++++++++++++++++++
target/ppc/translate/vsx-impl.inc.c | 5 +++--
target/ppc/translate/vsx-ops.inc.c | 1 +
4 files changed, 30 insertions(+), 2 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 8b30420..6c5b194 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -541,6 +541,7 @@ DEF_HELPER_2(xvrspiz, void, env, i32)
DEF_HELPER_2(xxperm, void, env, i32)
DEF_HELPER_2(xxpermr, void, env, i32)
DEF_HELPER_4(xxextractuw, void, env, tl, tl, i32)
+DEF_HELPER_4(xxinsertw, void, env, tl, tl, i32)
DEF_HELPER_2(efscfsi, i32, env, i32)
DEF_HELPER_2(efscfui, i32, env, i32)
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index 63ba0e3..24e5964 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -2059,6 +2059,31 @@ void helper_xxextractuw(CPUPPCState *env, target_ulong xtn,
putVSR(xtn, &xt, env);
}
+void helper_xxinsertw(CPUPPCState *env, target_ulong xtn,
+ target_ulong xbn, uint32_t index)
+{
+ ppc_vsr_t xt, xb;
+ size_t es = sizeof(uint32_t);
+ int ins_index, i = 0;
+
+ getVSR(xbn, &xb, env);
+ getVSR(xtn, &xt, env);
+
+#if defined(HOST_WORDS_BIGENDIAN)
+ ins_index = index;
+ for (i = 0; i < es && ins_index < 16; i++, ins_index++) {
+ xt.u8[ins_index] = xb.u8[8 - es + i];
+ }
+#else
+ ins_index = 15 - index;
+ for (i = es - 1; i >= 0 && ins_index >= 0; i--, ins_index--) {
+ xt.u8[ins_index] = xb.u8[8 + i];
+ }
+#endif
+
+ putVSR(xtn, &xt, env);
+}
+
#define VEXT_SIGNED(name, element, mask, cast, recast) \
void helper_##name(ppc_avr_t *r, ppc_avr_t *b) \
{ \
diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c
index 7977f24..c9ba0f5 100644
--- a/target/ppc/translate/vsx-impl.inc.c
+++ b/target/ppc/translate/vsx-impl.inc.c
@@ -1180,7 +1180,7 @@ static void gen_xxsldwi(DisasContext *ctx)
tcg_temp_free_i64(xtl);
}
-#define VSX_EXTRACT(name) \
+#define VSX_EXTRACT_INSERT(name) \
static void gen_##name(DisasContext *ctx) \
{ \
TCGv xt, xb; \
@@ -1208,7 +1208,8 @@ static void gen_##name(DisasContext *ctx) \
tcg_temp_free_i32(t0); \
}
-VSX_EXTRACT(xxextractuw)
+VSX_EXTRACT_INSERT(xxextractuw)
+VSX_EXTRACT_INSERT(xxinsertw)
#undef GEN_XX2FORM
#undef GEN_XX3FORM
diff --git a/target/ppc/translate/vsx-ops.inc.c b/target/ppc/translate/vsx-ops.inc.c
index 473d925..096d358 100644
--- a/target/ppc/translate/vsx-ops.inc.c
+++ b/target/ppc/translate/vsx-ops.inc.c
@@ -285,6 +285,7 @@ GEN_XX2FORM(xxspltw, 0x08, 0x0A, PPC2_VSX),
GEN_XX1FORM(xxspltib, 0x08, 0x0B, PPC2_ISA300),
GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00),
GEN_XX2FORM_EXT(xxextractuw, 0x0A, 0x0A, PPC2_ISA300),
+GEN_XX2FORM_EXT(xxinsertw, 0x0A, 0x0B, PPC2_ISA300),
#define GEN_XXSEL_ROW(opc3) \
GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x18, opc3, 0, PPC_NONE, PPC2_VSX), \
--
2.7.4
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [Qemu-devel] [PATCH v1 02/14] target-ppc: Add xxinsertw instruction
2017-01-06 6:14 ` [Qemu-devel] [PATCH v1 02/14] target-ppc: Add xxinsertw instruction Nikunj A Dadhania
@ 2017-01-06 7:54 ` David Gibson
2017-01-06 8:28 ` Nikunj A Dadhania
2017-01-07 1:03 ` David Gibson
1 sibling, 1 reply; 21+ messages in thread
From: David Gibson @ 2017-01-06 7:54 UTC (permalink / raw)
To: Nikunj A Dadhania; +Cc: qemu-ppc, rth, qemu-devel, bharata
[-- Attachment #1: Type: text/plain, Size: 4053 bytes --]
On Fri, Jan 06, 2017 at 11:44:44AM +0530, Nikunj A Dadhania wrote:
> xxinsertw: VSX Vector Insert Word
>
> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
The comments I had about out of bounds shifts don't seem to have been
addressed here.
> ---
> target/ppc/helper.h | 1 +
> target/ppc/int_helper.c | 25 +++++++++++++++++++++++++
> target/ppc/translate/vsx-impl.inc.c | 5 +++--
> target/ppc/translate/vsx-ops.inc.c | 1 +
> 4 files changed, 30 insertions(+), 2 deletions(-)
>
> diff --git a/target/ppc/helper.h b/target/ppc/helper.h
> index 8b30420..6c5b194 100644
> --- a/target/ppc/helper.h
> +++ b/target/ppc/helper.h
> @@ -541,6 +541,7 @@ DEF_HELPER_2(xvrspiz, void, env, i32)
> DEF_HELPER_2(xxperm, void, env, i32)
> DEF_HELPER_2(xxpermr, void, env, i32)
> DEF_HELPER_4(xxextractuw, void, env, tl, tl, i32)
> +DEF_HELPER_4(xxinsertw, void, env, tl, tl, i32)
>
> DEF_HELPER_2(efscfsi, i32, env, i32)
> DEF_HELPER_2(efscfui, i32, env, i32)
> diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
> index 63ba0e3..24e5964 100644
> --- a/target/ppc/int_helper.c
> +++ b/target/ppc/int_helper.c
> @@ -2059,6 +2059,31 @@ void helper_xxextractuw(CPUPPCState *env, target_ulong xtn,
> putVSR(xtn, &xt, env);
> }
>
> +void helper_xxinsertw(CPUPPCState *env, target_ulong xtn,
> + target_ulong xbn, uint32_t index)
> +{
> + ppc_vsr_t xt, xb;
> + size_t es = sizeof(uint32_t);
> + int ins_index, i = 0;
> +
> + getVSR(xbn, &xb, env);
> + getVSR(xtn, &xt, env);
> +
> +#if defined(HOST_WORDS_BIGENDIAN)
> + ins_index = index;
> + for (i = 0; i < es && ins_index < 16; i++, ins_index++) {
> + xt.u8[ins_index] = xb.u8[8 - es + i];
> + }
> +#else
> + ins_index = 15 - index;
> + for (i = es - 1; i >= 0 && ins_index >= 0; i--, ins_index--) {
> + xt.u8[ins_index] = xb.u8[8 + i];
> + }
> +#endif
> +
> + putVSR(xtn, &xt, env);
> +}
> +
> #define VEXT_SIGNED(name, element, mask, cast, recast) \
> void helper_##name(ppc_avr_t *r, ppc_avr_t *b) \
> { \
> diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c
> index 7977f24..c9ba0f5 100644
> --- a/target/ppc/translate/vsx-impl.inc.c
> +++ b/target/ppc/translate/vsx-impl.inc.c
> @@ -1180,7 +1180,7 @@ static void gen_xxsldwi(DisasContext *ctx)
> tcg_temp_free_i64(xtl);
> }
>
> -#define VSX_EXTRACT(name) \
> +#define VSX_EXTRACT_INSERT(name) \
> static void gen_##name(DisasContext *ctx) \
> { \
> TCGv xt, xb; \
> @@ -1208,7 +1208,8 @@ static void gen_##name(DisasContext *ctx) \
> tcg_temp_free_i32(t0); \
> }
>
> -VSX_EXTRACT(xxextractuw)
> +VSX_EXTRACT_INSERT(xxextractuw)
> +VSX_EXTRACT_INSERT(xxinsertw)
>
> #undef GEN_XX2FORM
> #undef GEN_XX3FORM
> diff --git a/target/ppc/translate/vsx-ops.inc.c b/target/ppc/translate/vsx-ops.inc.c
> index 473d925..096d358 100644
> --- a/target/ppc/translate/vsx-ops.inc.c
> +++ b/target/ppc/translate/vsx-ops.inc.c
> @@ -285,6 +285,7 @@ GEN_XX2FORM(xxspltw, 0x08, 0x0A, PPC2_VSX),
> GEN_XX1FORM(xxspltib, 0x08, 0x0B, PPC2_ISA300),
> GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00),
> GEN_XX2FORM_EXT(xxextractuw, 0x0A, 0x0A, PPC2_ISA300),
> +GEN_XX2FORM_EXT(xxinsertw, 0x0A, 0x0B, PPC2_ISA300),
>
> #define GEN_XXSEL_ROW(opc3) \
> GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x18, opc3, 0, PPC_NONE, PPC2_VSX), \
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
^ permalink raw reply [flat|nested] 21+ messages in thread* Re: [Qemu-devel] [PATCH v1 02/14] target-ppc: Add xxinsertw instruction
2017-01-06 7:54 ` David Gibson
@ 2017-01-06 8:28 ` Nikunj A Dadhania
2017-01-07 1:02 ` David Gibson
0 siblings, 1 reply; 21+ messages in thread
From: Nikunj A Dadhania @ 2017-01-06 8:28 UTC (permalink / raw)
To: David Gibson; +Cc: qemu-ppc, rth, qemu-devel, bharata
David Gibson <david@gibson.dropbear.id.au> writes:
> [ Unknown signature status ]
> On Fri, Jan 06, 2017 at 11:44:44AM +0530, Nikunj A Dadhania wrote:
>> xxinsertw: VSX Vector Insert Word
>>
>> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
>
> The comments I had about out of bounds shifts don't seem to have been
> addressed here.
Bounds are addressed inside the for condition:
#if defined(HOST_WORDS_BIGENDIAN)
ins_index = index;
for (i = 0; i < es && ins_index < 16; i++, ins_index++) {
^^^^^^^^^^^^^^
xt.u8[ins_index] = xb.u8[8 - es + i];
}
#else
ins_index = 15 - index;
for (i = es - 1; i >= 0 && ins_index >= 0; i--, ins_index--) {
^^^^^^^^^^^^^^
xt.u8[ins_index] = xb.u8[8 + i];
}
#endif
That way ins_index will be within 0 - 15. Let me know if I have missed
something.
Regards
Nikunj
^ permalink raw reply [flat|nested] 21+ messages in thread* Re: [Qemu-devel] [PATCH v1 02/14] target-ppc: Add xxinsertw instruction
2017-01-06 8:28 ` Nikunj A Dadhania
@ 2017-01-07 1:02 ` David Gibson
0 siblings, 0 replies; 21+ messages in thread
From: David Gibson @ 2017-01-07 1:02 UTC (permalink / raw)
To: Nikunj A Dadhania; +Cc: qemu-ppc, rth, qemu-devel, bharata
[-- Attachment #1: Type: text/plain, Size: 1278 bytes --]
On Fri, Jan 06, 2017 at 01:58:19PM +0530, Nikunj A Dadhania wrote:
> David Gibson <david@gibson.dropbear.id.au> writes:
>
> > [ Unknown signature status ]
> > On Fri, Jan 06, 2017 at 11:44:44AM +0530, Nikunj A Dadhania wrote:
> >> xxinsertw: VSX Vector Insert Word
> >>
> >> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
> >
> > The comments I had about out of bounds shifts don't seem to have been
> > addressed here.
>
> Bounds are addressed inside the for condition:
>
> #if defined(HOST_WORDS_BIGENDIAN)
> ins_index = index;
> for (i = 0; i < es && ins_index < 16; i++, ins_index++) {
> ^^^^^^^^^^^^^^
> xt.u8[ins_index] = xb.u8[8 - es + i];
> }
> #else
> ins_index = 15 - index;
> for (i = es - 1; i >= 0 && ins_index >= 0; i--, ins_index--) {
> ^^^^^^^^^^^^^^
> xt.u8[ins_index] = xb.u8[8 + i];
> }
> #endif
>
> That way ins_index will be within 0 - 15. Let me know if I have missed
> something.
Oh, yes, I missed that. Sorry.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [Qemu-devel] [PATCH v1 02/14] target-ppc: Add xxinsertw instruction
2017-01-06 6:14 ` [Qemu-devel] [PATCH v1 02/14] target-ppc: Add xxinsertw instruction Nikunj A Dadhania
2017-01-06 7:54 ` David Gibson
@ 2017-01-07 1:03 ` David Gibson
1 sibling, 0 replies; 21+ messages in thread
From: David Gibson @ 2017-01-07 1:03 UTC (permalink / raw)
To: Nikunj A Dadhania; +Cc: qemu-ppc, rth, qemu-devel, bharata
[-- Attachment #1: Type: text/plain, Size: 3990 bytes --]
On Fri, Jan 06, 2017 at 11:44:44AM +0530, Nikunj A Dadhania wrote:
> xxinsertw: VSX Vector Insert Word
>
> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Applied to ppc-for-2.9.
> ---
> target/ppc/helper.h | 1 +
> target/ppc/int_helper.c | 25 +++++++++++++++++++++++++
> target/ppc/translate/vsx-impl.inc.c | 5 +++--
> target/ppc/translate/vsx-ops.inc.c | 1 +
> 4 files changed, 30 insertions(+), 2 deletions(-)
>
> diff --git a/target/ppc/helper.h b/target/ppc/helper.h
> index 8b30420..6c5b194 100644
> --- a/target/ppc/helper.h
> +++ b/target/ppc/helper.h
> @@ -541,6 +541,7 @@ DEF_HELPER_2(xvrspiz, void, env, i32)
> DEF_HELPER_2(xxperm, void, env, i32)
> DEF_HELPER_2(xxpermr, void, env, i32)
> DEF_HELPER_4(xxextractuw, void, env, tl, tl, i32)
> +DEF_HELPER_4(xxinsertw, void, env, tl, tl, i32)
>
> DEF_HELPER_2(efscfsi, i32, env, i32)
> DEF_HELPER_2(efscfui, i32, env, i32)
> diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
> index 63ba0e3..24e5964 100644
> --- a/target/ppc/int_helper.c
> +++ b/target/ppc/int_helper.c
> @@ -2059,6 +2059,31 @@ void helper_xxextractuw(CPUPPCState *env, target_ulong xtn,
> putVSR(xtn, &xt, env);
> }
>
> +void helper_xxinsertw(CPUPPCState *env, target_ulong xtn,
> + target_ulong xbn, uint32_t index)
> +{
> + ppc_vsr_t xt, xb;
> + size_t es = sizeof(uint32_t);
> + int ins_index, i = 0;
> +
> + getVSR(xbn, &xb, env);
> + getVSR(xtn, &xt, env);
> +
> +#if defined(HOST_WORDS_BIGENDIAN)
> + ins_index = index;
> + for (i = 0; i < es && ins_index < 16; i++, ins_index++) {
> + xt.u8[ins_index] = xb.u8[8 - es + i];
> + }
> +#else
> + ins_index = 15 - index;
> + for (i = es - 1; i >= 0 && ins_index >= 0; i--, ins_index--) {
> + xt.u8[ins_index] = xb.u8[8 + i];
> + }
> +#endif
> +
> + putVSR(xtn, &xt, env);
> +}
> +
> #define VEXT_SIGNED(name, element, mask, cast, recast) \
> void helper_##name(ppc_avr_t *r, ppc_avr_t *b) \
> { \
> diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c
> index 7977f24..c9ba0f5 100644
> --- a/target/ppc/translate/vsx-impl.inc.c
> +++ b/target/ppc/translate/vsx-impl.inc.c
> @@ -1180,7 +1180,7 @@ static void gen_xxsldwi(DisasContext *ctx)
> tcg_temp_free_i64(xtl);
> }
>
> -#define VSX_EXTRACT(name) \
> +#define VSX_EXTRACT_INSERT(name) \
> static void gen_##name(DisasContext *ctx) \
> { \
> TCGv xt, xb; \
> @@ -1208,7 +1208,8 @@ static void gen_##name(DisasContext *ctx) \
> tcg_temp_free_i32(t0); \
> }
>
> -VSX_EXTRACT(xxextractuw)
> +VSX_EXTRACT_INSERT(xxextractuw)
> +VSX_EXTRACT_INSERT(xxinsertw)
>
> #undef GEN_XX2FORM
> #undef GEN_XX3FORM
> diff --git a/target/ppc/translate/vsx-ops.inc.c b/target/ppc/translate/vsx-ops.inc.c
> index 473d925..096d358 100644
> --- a/target/ppc/translate/vsx-ops.inc.c
> +++ b/target/ppc/translate/vsx-ops.inc.c
> @@ -285,6 +285,7 @@ GEN_XX2FORM(xxspltw, 0x08, 0x0A, PPC2_VSX),
> GEN_XX1FORM(xxspltib, 0x08, 0x0B, PPC2_ISA300),
> GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00),
> GEN_XX2FORM_EXT(xxextractuw, 0x0A, 0x0A, PPC2_ISA300),
> +GEN_XX2FORM_EXT(xxinsertw, 0x0A, 0x0B, PPC2_ISA300),
>
> #define GEN_XXSEL_ROW(opc3) \
> GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x18, opc3, 0, PPC_NONE, PPC2_VSX), \
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
^ permalink raw reply [flat|nested] 21+ messages in thread
* [Qemu-devel] [PATCH v1 03/14] target-ppc: Use float64 arg in helper_compute_fprf()
2017-01-06 6:14 [Qemu-devel] [PATCH v1 00/14] POWER9 TCG enablements - part10 Nikunj A Dadhania
2017-01-06 6:14 ` [Qemu-devel] [PATCH v1 01/14] target-ppc: Add xxextractuw instruction Nikunj A Dadhania
2017-01-06 6:14 ` [Qemu-devel] [PATCH v1 02/14] target-ppc: Add xxinsertw instruction Nikunj A Dadhania
@ 2017-01-06 6:14 ` Nikunj A Dadhania
2017-01-06 6:14 ` [Qemu-devel] [PATCH v1 04/14] target-ppc: Replace isden by float64_is_zero_or_denormal Nikunj A Dadhania
` (11 subsequent siblings)
14 siblings, 0 replies; 21+ messages in thread
From: Nikunj A Dadhania @ 2017-01-06 6:14 UTC (permalink / raw)
To: qemu-ppc, david, rth; +Cc: qemu-devel, bharata, nikunj
From: Bharata B Rao <bharata@linux.vnet.ibm.com>
Use float64 argument instead of unit64_t in helper_compute_fprf()
This allows code in helper_compute_fprf() to be reused later to
work with float128 argument too.
Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com>
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
target/ppc/fpu_helper.c | 16 +++++++---------
1 file changed, 7 insertions(+), 9 deletions(-)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index 1ccd5e6..4da991a 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -66,23 +66,21 @@ static inline int ppc_float64_get_unbiased_exp(float64 f)
return ((f >> 52) & 0x7FF) - 1023;
}
-void helper_compute_fprf(CPUPPCState *env, uint64_t arg)
+void helper_compute_fprf(CPUPPCState *env, float64 arg)
{
- CPU_DoubleU farg;
int isneg;
int fprf;
- farg.ll = arg;
- isneg = float64_is_neg(farg.d);
- if (unlikely(float64_is_any_nan(farg.d))) {
- if (float64_is_signaling_nan(farg.d, &env->fp_status)) {
+ isneg = float64_is_neg(arg);
+ if (unlikely(float64_is_any_nan(arg))) {
+ if (float64_is_signaling_nan(arg, &env->fp_status)) {
/* Signaling NaN: flags are undefined */
fprf = 0x00;
} else {
/* Quiet NaN */
fprf = 0x11;
}
- } else if (unlikely(float64_is_infinity(farg.d))) {
+ } else if (unlikely(float64_is_infinity(arg))) {
/* +/- infinity */
if (isneg) {
fprf = 0x09;
@@ -90,7 +88,7 @@ void helper_compute_fprf(CPUPPCState *env, uint64_t arg)
fprf = 0x05;
}
} else {
- if (float64_is_zero(farg.d)) {
+ if (float64_is_zero(arg)) {
/* +/- zero */
if (isneg) {
fprf = 0x12;
@@ -98,7 +96,7 @@ void helper_compute_fprf(CPUPPCState *env, uint64_t arg)
fprf = 0x02;
}
} else {
- if (isden(farg.d)) {
+ if (isden(arg)) {
/* Denormalized numbers */
fprf = 0x10;
} else {
--
2.7.4
^ permalink raw reply related [flat|nested] 21+ messages in thread* [Qemu-devel] [PATCH v1 04/14] target-ppc: Replace isden by float64_is_zero_or_denormal
2017-01-06 6:14 [Qemu-devel] [PATCH v1 00/14] POWER9 TCG enablements - part10 Nikunj A Dadhania
` (2 preceding siblings ...)
2017-01-06 6:14 ` [Qemu-devel] [PATCH v1 03/14] target-ppc: Use float64 arg in helper_compute_fprf() Nikunj A Dadhania
@ 2017-01-06 6:14 ` Nikunj A Dadhania
2017-01-06 6:14 ` [Qemu-devel] [PATCH v1 05/14] target-ppc: Rename helper_compute_fprf to helper_compute_fprf_float64 Nikunj A Dadhania
` (10 subsequent siblings)
14 siblings, 0 replies; 21+ messages in thread
From: Nikunj A Dadhania @ 2017-01-06 6:14 UTC (permalink / raw)
To: qemu-ppc, david, rth; +Cc: qemu-devel, bharata, nikunj
From: Bharata B Rao <bharata@linux.vnet.ibm.com>
Replace isden() by float64_is_zero_or_denormal() so that code in
helper_compute_fprf() can be reused to work with float128 argument.
Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com>
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/fpu_helper.c | 11 +----------
1 file changed, 1 insertion(+), 10 deletions(-)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index 4da991a..5a7aa75 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -47,15 +47,6 @@ uint32_t helper_float64_to_float32(CPUPPCState *env, uint64_t arg)
return f.l;
}
-static inline int isden(float64 d)
-{
- CPU_DoubleU u;
-
- u.d = d;
-
- return ((u.ll >> 52) & 0x7FF) == 0;
-}
-
static inline int ppc_float32_get_unbiased_exp(float32 f)
{
return ((f >> 23) & 0xFF) - 127;
@@ -96,7 +87,7 @@ void helper_compute_fprf(CPUPPCState *env, float64 arg)
fprf = 0x02;
}
} else {
- if (isden(arg)) {
+ if (float64_is_zero_or_denormal(arg)) {
/* Denormalized numbers */
fprf = 0x10;
} else {
--
2.7.4
^ permalink raw reply related [flat|nested] 21+ messages in thread* [Qemu-devel] [PATCH v1 05/14] target-ppc: Rename helper_compute_fprf to helper_compute_fprf_float64
2017-01-06 6:14 [Qemu-devel] [PATCH v1 00/14] POWER9 TCG enablements - part10 Nikunj A Dadhania
` (3 preceding siblings ...)
2017-01-06 6:14 ` [Qemu-devel] [PATCH v1 04/14] target-ppc: Replace isden by float64_is_zero_or_denormal Nikunj A Dadhania
@ 2017-01-06 6:14 ` Nikunj A Dadhania
2017-01-06 6:14 ` [Qemu-devel] [PATCH v1 06/14] target-ppc: Add xsaddqp instructions Nikunj A Dadhania
` (9 subsequent siblings)
14 siblings, 0 replies; 21+ messages in thread
From: Nikunj A Dadhania @ 2017-01-06 6:14 UTC (permalink / raw)
To: qemu-ppc, david, rth; +Cc: qemu-devel, bharata, nikunj
From: Bharata B Rao <bharata@linux.vnet.ibm.com>
Since helper_compute_fprf() works on float64 argument, rename it
to helper_compute_fprf_float64(). Also use a macro to generate
helper_compute_fprf_float64() so that float128 version of the same
helper can be introduced easily later.
Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com>
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
target/ppc/fpu_helper.c | 121 +++++++++++++++++++------------------
target/ppc/helper.h | 2 +-
target/ppc/translate/fp-impl.inc.c | 20 +++---
3 files changed, 73 insertions(+), 70 deletions(-)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index 5a7aa75..913d54e 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -57,54 +57,57 @@ static inline int ppc_float64_get_unbiased_exp(float64 f)
return ((f >> 52) & 0x7FF) - 1023;
}
-void helper_compute_fprf(CPUPPCState *env, float64 arg)
-{
- int isneg;
- int fprf;
-
- isneg = float64_is_neg(arg);
- if (unlikely(float64_is_any_nan(arg))) {
- if (float64_is_signaling_nan(arg, &env->fp_status)) {
- /* Signaling NaN: flags are undefined */
- fprf = 0x00;
- } else {
- /* Quiet NaN */
- fprf = 0x11;
- }
- } else if (unlikely(float64_is_infinity(arg))) {
- /* +/- infinity */
- if (isneg) {
- fprf = 0x09;
- } else {
- fprf = 0x05;
- }
- } else {
- if (float64_is_zero(arg)) {
- /* +/- zero */
- if (isneg) {
- fprf = 0x12;
- } else {
- fprf = 0x02;
- }
- } else {
- if (float64_is_zero_or_denormal(arg)) {
- /* Denormalized numbers */
- fprf = 0x10;
- } else {
- /* Normalized numbers */
- fprf = 0x00;
- }
- if (isneg) {
- fprf |= 0x08;
- } else {
- fprf |= 0x04;
- }
- }
- }
- /* We update FPSCR_FPRF */
- env->fpscr &= ~(0x1F << FPSCR_FPRF);
- env->fpscr |= fprf << FPSCR_FPRF;
-}
+#define COMPUTE_FPRF(tp) \
+void helper_compute_fprf_##tp(CPUPPCState *env, tp arg) \
+{ \
+ int isneg; \
+ int fprf; \
+ \
+ isneg = tp##_is_neg(arg); \
+ if (unlikely(tp##_is_any_nan(arg))) { \
+ if (tp##_is_signaling_nan(arg, &env->fp_status)) { \
+ /* Signaling NaN: flags are undefined */ \
+ fprf = 0x00; \
+ } else { \
+ /* Quiet NaN */ \
+ fprf = 0x11; \
+ } \
+ } else if (unlikely(tp##_is_infinity(arg))) { \
+ /* +/- infinity */ \
+ if (isneg) { \
+ fprf = 0x09; \
+ } else { \
+ fprf = 0x05; \
+ } \
+ } else { \
+ if (tp##_is_zero(arg)) { \
+ /* +/- zero */ \
+ if (isneg) { \
+ fprf = 0x12; \
+ } else { \
+ fprf = 0x02; \
+ } \
+ } else { \
+ if (tp##_is_zero_or_denormal(arg)) { \
+ /* Denormalized numbers */ \
+ fprf = 0x10; \
+ } else { \
+ /* Normalized numbers */ \
+ fprf = 0x00; \
+ } \
+ if (isneg) { \
+ fprf |= 0x08; \
+ } else { \
+ fprf |= 0x04; \
+ } \
+ } \
+ } \
+ /* We update FPSCR_FPRF */ \
+ env->fpscr &= ~(0x1F << FPSCR_FPRF); \
+ env->fpscr |= fprf << FPSCR_FPRF; \
+}
+
+COMPUTE_FPRF(float64)
/* Floating-point invalid operations exception */
static inline __attribute__((__always_inline__))
@@ -1808,7 +1811,7 @@ void helper_##name(CPUPPCState *env, uint32_t opcode) \
} \
\
if (sfprf) { \
- helper_compute_fprf(env, xt.fld); \
+ helper_compute_fprf_float64(env, xt.fld); \
} \
} \
putVSR(xT(opcode), &xt, env); \
@@ -1863,7 +1866,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \
} \
\
if (sfprf) { \
- helper_compute_fprf(env, xt.fld); \
+ helper_compute_fprf_float64(env, xt.fld); \
} \
} \
\
@@ -1917,7 +1920,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \
} \
\
if (sfprf) { \
- helper_compute_fprf(env, xt.fld); \
+ helper_compute_fprf_float64(env, xt.fld); \
} \
} \
\
@@ -1958,7 +1961,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \
} \
\
if (sfprf) { \
- helper_compute_fprf(env, xt.fld); \
+ helper_compute_fprf_float64(env, xt.fld); \
} \
} \
\
@@ -2007,7 +2010,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \
} \
\
if (sfprf) { \
- helper_compute_fprf(env, xt.fld); \
+ helper_compute_fprf_float64(env, xt.fld); \
} \
} \
\
@@ -2057,7 +2060,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \
} \
\
if (sfprf) { \
- helper_compute_fprf(env, xt.fld); \
+ helper_compute_fprf_float64(env, xt.fld); \
} \
} \
\
@@ -2257,7 +2260,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \
} \
\
if (sfprf) { \
- helper_compute_fprf(env, xt_out.fld); \
+ helper_compute_fprf_float64(env, xt_out.fld); \
} \
} \
putVSR(xT(opcode), &xt_out, env); \
@@ -2647,7 +2650,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \
xt.tfld = ttp##_snan_to_qnan(xt.tfld); \
} \
if (sfprf) { \
- helper_compute_fprf(env, ttp##_to_float64(xt.tfld, \
+ helper_compute_fprf_float64(env, ttp##_to_float64(xt.tfld, \
&env->fp_status)); \
} \
} \
@@ -2758,7 +2761,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \
xt.tfld = helper_frsp(env, xt.tfld); \
} \
if (sfprf) { \
- helper_compute_fprf(env, xt.tfld); \
+ helper_compute_fprf_float64(env, xt.tfld); \
} \
} \
\
@@ -2814,7 +2817,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \
xt.fld = tp##_round_to_int(xb.fld, &env->fp_status); \
} \
if (sfprf) { \
- helper_compute_fprf(env, xt.fld); \
+ helper_compute_fprf_float64(env, xt.fld); \
} \
} \
\
@@ -2854,7 +2857,7 @@ uint64_t helper_xsrsp(CPUPPCState *env, uint64_t xb)
uint64_t xt = helper_frsp(env, xb);
- helper_compute_fprf(env, xt);
+ helper_compute_fprf_float64(env, xt);
float_check_status(env);
return xt;
}
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 6c5b194..04e688d 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -61,7 +61,7 @@ DEF_HELPER_FLAGS_2(brinc, TCG_CALL_NO_RWG_SE, tl, tl, tl)
DEF_HELPER_1(float_check_status, void, env)
DEF_HELPER_1(reset_fpstatus, void, env)
-DEF_HELPER_2(compute_fprf, void, env, i64)
+DEF_HELPER_2(compute_fprf_float64, void, env, i64)
DEF_HELPER_3(store_fpscr, void, env, i64, i32)
DEF_HELPER_2(fpscr_clrbit, void, env, i32)
DEF_HELPER_2(fpscr_setbit, void, env, i32)
diff --git a/target/ppc/translate/fp-impl.inc.c b/target/ppc/translate/fp-impl.inc.c
index 872af7b..2fbd4d4 100644
--- a/target/ppc/translate/fp-impl.inc.c
+++ b/target/ppc/translate/fp-impl.inc.c
@@ -9,9 +9,9 @@ static inline void gen_reset_fpstatus(void)
gen_helper_reset_fpstatus(cpu_env);
}
-static inline void gen_compute_fprf(TCGv_i64 arg)
+static inline void gen_compute_fprf_float64(TCGv_i64 arg)
{
- gen_helper_compute_fprf(cpu_env, arg);
+ gen_helper_compute_fprf_float64(cpu_env, arg);
gen_helper_float_check_status(cpu_env);
}
@@ -47,7 +47,7 @@ static void gen_f##name(DisasContext *ctx) \
cpu_fpr[rD(ctx->opcode)]); \
} \
if (set_fprf) { \
- gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
+ gen_compute_fprf_float64(cpu_fpr[rD(ctx->opcode)]); \
} \
if (unlikely(Rc(ctx->opcode) != 0)) { \
gen_set_cr1_from_fpscr(ctx); \
@@ -74,7 +74,7 @@ static void gen_f##name(DisasContext *ctx) \
cpu_fpr[rD(ctx->opcode)]); \
} \
if (set_fprf) { \
- gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
+ gen_compute_fprf_float64(cpu_fpr[rD(ctx->opcode)]); \
} \
if (unlikely(Rc(ctx->opcode) != 0)) { \
gen_set_cr1_from_fpscr(ctx); \
@@ -100,7 +100,7 @@ static void gen_f##name(DisasContext *ctx) \
cpu_fpr[rD(ctx->opcode)]); \
} \
if (set_fprf) { \
- gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
+ gen_compute_fprf_float64(cpu_fpr[rD(ctx->opcode)]); \
} \
if (unlikely(Rc(ctx->opcode) != 0)) { \
gen_set_cr1_from_fpscr(ctx); \
@@ -121,7 +121,7 @@ static void gen_f##name(DisasContext *ctx) \
gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
cpu_fpr[rB(ctx->opcode)]); \
if (set_fprf) { \
- gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
+ gen_compute_fprf_float64(cpu_fpr[rD(ctx->opcode)]); \
} \
if (unlikely(Rc(ctx->opcode) != 0)) { \
gen_set_cr1_from_fpscr(ctx); \
@@ -139,7 +139,7 @@ static void gen_f##name(DisasContext *ctx) \
gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
cpu_fpr[rB(ctx->opcode)]); \
if (set_fprf) { \
- gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
+ gen_compute_fprf_float64(cpu_fpr[rD(ctx->opcode)]); \
} \
if (unlikely(Rc(ctx->opcode) != 0)) { \
gen_set_cr1_from_fpscr(ctx); \
@@ -174,7 +174,7 @@ static void gen_frsqrtes(DisasContext *ctx)
cpu_fpr[rB(ctx->opcode)]);
gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
cpu_fpr[rD(ctx->opcode)]);
- gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]);
+ gen_compute_fprf_float64(cpu_fpr[rD(ctx->opcode)]);
if (unlikely(Rc(ctx->opcode) != 0)) {
gen_set_cr1_from_fpscr(ctx);
}
@@ -196,7 +196,7 @@ static void gen_fsqrt(DisasContext *ctx)
gen_reset_fpstatus();
gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
cpu_fpr[rB(ctx->opcode)]);
- gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]);
+ gen_compute_fprf_float64(cpu_fpr[rD(ctx->opcode)]);
if (unlikely(Rc(ctx->opcode) != 0)) {
gen_set_cr1_from_fpscr(ctx);
}
@@ -213,7 +213,7 @@ static void gen_fsqrts(DisasContext *ctx)
cpu_fpr[rB(ctx->opcode)]);
gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
cpu_fpr[rD(ctx->opcode)]);
- gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]);
+ gen_compute_fprf_float64(cpu_fpr[rD(ctx->opcode)]);
if (unlikely(Rc(ctx->opcode) != 0)) {
gen_set_cr1_from_fpscr(ctx);
}
--
2.7.4
^ permalink raw reply related [flat|nested] 21+ messages in thread* [Qemu-devel] [PATCH v1 06/14] target-ppc: Add xsaddqp instructions
2017-01-06 6:14 [Qemu-devel] [PATCH v1 00/14] POWER9 TCG enablements - part10 Nikunj A Dadhania
` (4 preceding siblings ...)
2017-01-06 6:14 ` [Qemu-devel] [PATCH v1 05/14] target-ppc: Rename helper_compute_fprf to helper_compute_fprf_float64 Nikunj A Dadhania
@ 2017-01-06 6:14 ` Nikunj A Dadhania
2017-01-06 6:14 ` [Qemu-devel] [PATCH v1 07/14] target-ppc: Add xscvdphp, xscvhpdp Nikunj A Dadhania
` (8 subsequent siblings)
14 siblings, 0 replies; 21+ messages in thread
From: Nikunj A Dadhania @ 2017-01-06 6:14 UTC (permalink / raw)
To: qemu-ppc, david, rth; +Cc: qemu-devel, bharata, nikunj
From: Bharata B Rao <bharata@linux.vnet.ibm.com>
xsaddqp: VSX Scalar Add Quad-Precision
Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com>
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
target/ppc/fpu_helper.c | 36 ++++++++++++++++++++++++++++++++++++
target/ppc/helper.h | 1 +
target/ppc/internal.h | 2 ++
target/ppc/translate/vsx-impl.inc.c | 1 +
target/ppc/translate/vsx-ops.inc.c | 1 +
5 files changed, 41 insertions(+)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index 913d54e..d48cf51 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -108,6 +108,7 @@ void helper_compute_fprf_##tp(CPUPPCState *env, tp arg) \
}
COMPUTE_FPRF(float64)
+COMPUTE_FPRF(float128)
/* Floating-point invalid operations exception */
static inline __attribute__((__always_inline__))
@@ -1827,6 +1828,41 @@ VSX_ADD_SUB(xssubsp, sub, 1, float64, VsrD(0), 1, 1)
VSX_ADD_SUB(xvsubdp, sub, 2, float64, VsrD(i), 0, 0)
VSX_ADD_SUB(xvsubsp, sub, 4, float32, VsrW(i), 0, 0)
+void helper_xsaddqp(CPUPPCState *env, uint32_t opcode)
+{
+ ppc_vsr_t xt, xa, xb;
+ float_status tstat;
+
+ getVSR(xA(opcode), &xa, env);
+ getVSR(xB(opcode), &xb, env);
+ getVSR(xT(opcode), &xt, env);
+ helper_reset_fpstatus(env);
+
+ if (unlikely(Rc(opcode) != 0)) {
+ /* TODO: Support xsadddpo after round-to-odd is implemented */
+ abort();
+ }
+
+ tstat = env->fp_status;
+ set_float_exception_flags(0, &tstat);
+ xt.f128 = float128_add(xa.f128, xb.f128, &tstat);
+ env->fp_status.float_exception_flags |= tstat.float_exception_flags;
+
+ if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {
+ if (float128_is_infinity(xa.f128) && float128_is_infinity(xb.f128)) {
+ float_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, 1);
+ } else if (float128_is_signaling_nan(xa.f128, &tstat) ||
+ float128_is_signaling_nan(xb.f128, &tstat)) {
+ float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
+ }
+ }
+
+ helper_compute_fprf_float128(env, xt.f128);
+
+ putVSR(xT(opcode), &xt, env);
+ float_check_status(env);
+}
+
/* VSX_MUL - VSX floating point multiply
* op - instruction mnemonic
* nels - number of elements (1, 2 or 4)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 04e688d..cd7b608 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -400,6 +400,7 @@ DEF_HELPER_4(bcdcpsgn, i32, avr, avr, avr, i32)
DEF_HELPER_3(bcdsetsgn, i32, avr, avr, i32)
DEF_HELPER_2(xsadddp, void, env, i32)
+DEF_HELPER_2(xsaddqp, void, env, i32)
DEF_HELPER_2(xssubdp, void, env, i32)
DEF_HELPER_2(xsmuldp, void, env, i32)
DEF_HELPER_2(xsdivdp, void, env, i32)
diff --git a/target/ppc/internal.h b/target/ppc/internal.h
index 66cde46..f4f02e5 100644
--- a/target/ppc/internal.h
+++ b/target/ppc/internal.h
@@ -206,6 +206,7 @@ typedef union _ppc_vsr_t {
uint64_t u64[2];
float32 f32[4];
float64 f64[2];
+ float128 f128;
Int128 s128;
} ppc_vsr_t;
@@ -241,4 +242,5 @@ static inline void putVSR(int n, ppc_vsr_t *vsr, CPUPPCState *env)
}
}
+void helper_compute_fprf_float128(CPUPPCState *env, float128 arg);
#endif /* PPC_INTERNAL_H */
diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c
index c9ba0f5..51ac183 100644
--- a/target/ppc/translate/vsx-impl.inc.c
+++ b/target/ppc/translate/vsx-impl.inc.c
@@ -777,6 +777,7 @@ static void gen_##name(DisasContext * ctx) \
}
GEN_VSX_HELPER_2(xsadddp, 0x00, 0x04, 0, PPC2_VSX)
+GEN_VSX_HELPER_2(xsaddqp, 0x04, 0x00, 0, PPC2_ISA300)
GEN_VSX_HELPER_2(xssubdp, 0x00, 0x05, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xsmuldp, 0x00, 0x06, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xsdivdp, 0x00, 0x07, 0, PPC2_VSX)
diff --git a/target/ppc/translate/vsx-ops.inc.c b/target/ppc/translate/vsx-ops.inc.c
index 096d358..1155765 100644
--- a/target/ppc/translate/vsx-ops.inc.c
+++ b/target/ppc/translate/vsx-ops.inc.c
@@ -123,6 +123,7 @@ GEN_XX2FORM(xvnegsp, 0x12, 0x1B, PPC2_VSX),
GEN_XX3FORM(xvcpsgnsp, 0x00, 0x1A, PPC2_VSX),
GEN_XX3FORM(xsadddp, 0x00, 0x04, PPC2_VSX),
+GEN_VSX_XFORM_300(xsaddqp, 0x04, 0x00, 0x0),
GEN_XX3FORM(xssubdp, 0x00, 0x05, PPC2_VSX),
GEN_XX3FORM(xsmuldp, 0x00, 0x06, PPC2_VSX),
GEN_XX3FORM(xsdivdp, 0x00, 0x07, PPC2_VSX),
--
2.7.4
^ permalink raw reply related [flat|nested] 21+ messages in thread* [Qemu-devel] [PATCH v1 07/14] target-ppc: Add xscvdphp, xscvhpdp
2017-01-06 6:14 [Qemu-devel] [PATCH v1 00/14] POWER9 TCG enablements - part10 Nikunj A Dadhania
` (5 preceding siblings ...)
2017-01-06 6:14 ` [Qemu-devel] [PATCH v1 06/14] target-ppc: Add xsaddqp instructions Nikunj A Dadhania
@ 2017-01-06 6:14 ` Nikunj A Dadhania
2017-01-06 6:14 ` [Qemu-devel] [PATCH v1 08/14] target-ppc: Use correct precision for FPRF setting Nikunj A Dadhania
` (7 subsequent siblings)
14 siblings, 0 replies; 21+ messages in thread
From: Nikunj A Dadhania @ 2017-01-06 6:14 UTC (permalink / raw)
To: qemu-ppc, david, rth; +Cc: qemu-devel, bharata, nikunj
From: Bharata B Rao <bharata@linux.vnet.ibm.com>
xscvdphp: VSX Scalar round & Convert Double-Precision format to
Half-Precision format
xscvhpdp: VSX Scalar Convert Half-Precision format to
Double-Precision format
Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com>
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
include/fpu/softfloat.h | 20 ++++++++++++++++++++
target/ppc/fpu_helper.c | 33 +++++++++++++++++++++++++++++++++
target/ppc/helper.h | 2 ++
target/ppc/internal.h | 3 +++
target/ppc/translate/vsx-impl.inc.c | 2 ++
target/ppc/translate/vsx-ops.inc.c | 2 ++
6 files changed, 62 insertions(+)
diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h
index 14f8383..842ec6b 100644
--- a/include/fpu/softfloat.h
+++ b/include/fpu/softfloat.h
@@ -356,6 +356,26 @@ static inline int float16_is_any_nan(float16 a)
return ((float16_val(a) & ~0x8000) > 0x7c00);
}
+static inline int float16_is_neg(float16 a)
+{
+ return float16_val(a) >> 15;
+}
+
+static inline int float16_is_infinity(float16 a)
+{
+ return (float16_val(a) & 0x7fff) == 0x7c00;
+}
+
+static inline int float16_is_zero(float16 a)
+{
+ return (float16_val(a) & 0x7fff) == 0;
+}
+
+static inline int float16_is_zero_or_denormal(float16 a)
+{
+ return (float16_val(a) & 0x7c00) == 0;
+}
+
/*----------------------------------------------------------------------------
| The pattern for a default generated half-precision NaN.
*----------------------------------------------------------------------------*/
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index d48cf51..aacfd12 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -24,6 +24,7 @@
#define float64_snan_to_qnan(x) ((x) | 0x0008000000000000ULL)
#define float32_snan_to_qnan(x) ((x) | 0x00400000)
+#define float16_snan_to_qnan(x) ((x) | 0x0200)
/*****************************************************************************/
/* Floating point operations helpers */
@@ -107,6 +108,7 @@ void helper_compute_fprf_##tp(CPUPPCState *env, tp arg) \
env->fpscr |= fprf << FPSCR_FPRF; \
}
+COMPUTE_FPRF(float16)
COMPUTE_FPRF(float64)
COMPUTE_FPRF(float128)
@@ -2700,6 +2702,37 @@ VSX_CVT_FP_TO_FP(xscvspdp, 1, float32, float64, VsrW(0), VsrD(0), 1)
VSX_CVT_FP_TO_FP(xvcvdpsp, 2, float64, float32, VsrD(i), VsrW(2*i), 0)
VSX_CVT_FP_TO_FP(xvcvspdp, 2, float32, float64, VsrW(2*i), VsrD(i), 0)
+/* VSX_CVT_FP_TO_FP_HP - VSX floating point/floating point conversion
+ * involving one half precision value
+ * op - instruction mnemonic
+ * stp - source type
+ * ttp - target type
+ * sfld - source vsr_t field
+ * tfld - target vsr_t field
+ */
+#define VSX_CVT_FP_TO_FP_HP(op, stp, ttp, sfld, tfld) \
+void helper_##op(CPUPPCState *env, uint32_t opcode) \
+{ \
+ ppc_vsr_t xt, xb; \
+ \
+ getVSR(xB(opcode), &xb, env); \
+ memset(&xt, 0, sizeof(xt)); \
+ \
+ xt.tfld = stp##_to_##ttp(xb.sfld, 1, &env->fp_status); \
+ if (unlikely(stp##_is_signaling_nan(xb.sfld, \
+ &env->fp_status))) { \
+ float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \
+ xt.tfld = ttp##_snan_to_qnan(xt.tfld); \
+ } \
+ helper_compute_fprf_##ttp(env, xt.tfld); \
+ \
+ putVSR(xT(opcode), &xt, env); \
+ float_check_status(env); \
+}
+
+VSX_CVT_FP_TO_FP_HP(xscvdphp, float64, float16, VsrD(0), VsrH(3))
+VSX_CVT_FP_TO_FP_HP(xscvhpdp, float16, float64, VsrH(3), VsrD(0))
+
uint64_t helper_xscvdpspn(CPUPPCState *env, uint64_t xb)
{
float_status tstat = env->fp_status;
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index cd7b608..889fe55 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -429,8 +429,10 @@ DEF_HELPER_2(xscmpoqp, void, env, i32)
DEF_HELPER_2(xscmpuqp, void, env, i32)
DEF_HELPER_2(xsmaxdp, void, env, i32)
DEF_HELPER_2(xsmindp, void, env, i32)
+DEF_HELPER_2(xscvdphp, void, env, i32)
DEF_HELPER_2(xscvdpsp, void, env, i32)
DEF_HELPER_2(xscvdpspn, i64, env, i64)
+DEF_HELPER_2(xscvhpdp, void, env, i32)
DEF_HELPER_2(xscvspdp, void, env, i32)
DEF_HELPER_2(xscvspdpn, i64, env, i64)
DEF_HELPER_2(xscvdpsxds, void, env, i32)
diff --git a/target/ppc/internal.h b/target/ppc/internal.h
index f4f02e5..16fc117 100644
--- a/target/ppc/internal.h
+++ b/target/ppc/internal.h
@@ -212,10 +212,12 @@ typedef union _ppc_vsr_t {
#if defined(HOST_WORDS_BIGENDIAN)
#define VsrB(i) u8[i]
+#define VsrH(i) u16[i]
#define VsrW(i) u32[i]
#define VsrD(i) u64[i]
#else
#define VsrB(i) u8[15 - (i)]
+#define VsrH(i) u16[7 - (i)]
#define VsrW(i) u32[3 - (i)]
#define VsrD(i) u64[1 - (i)]
#endif
@@ -243,4 +245,5 @@ static inline void putVSR(int n, ppc_vsr_t *vsr, CPUPPCState *env)
}
void helper_compute_fprf_float128(CPUPPCState *env, float128 arg);
+void helper_compute_fprf_float16(CPUPPCState *env, float16 arg);
#endif /* PPC_INTERNAL_H */
diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c
index 51ac183..16242f2 100644
--- a/target/ppc/translate/vsx-impl.inc.c
+++ b/target/ppc/translate/vsx-impl.inc.c
@@ -806,8 +806,10 @@ GEN_VSX_HELPER_2(xscmpoqp, 0x04, 0x04, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xscmpuqp, 0x04, 0x14, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xsmindp, 0x00, 0x15, 0, PPC2_VSX)
+GEN_VSX_HELPER_2(xscvdphp, 0x16, 0x15, 0x11, PPC2_ISA300)
GEN_VSX_HELPER_2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX)
GEN_VSX_HELPER_XT_XB_ENV(xscvdpspn, 0x16, 0x10, 0, PPC2_VSX207)
+GEN_VSX_HELPER_2(xscvhpdp, 0x16, 0x15, 0x10, PPC2_ISA300)
GEN_VSX_HELPER_2(xscvspdp, 0x12, 0x14, 0, PPC2_VSX)
GEN_VSX_HELPER_XT_XB_ENV(xscvspdpn, 0x16, 0x14, 0, PPC2_VSX207)
GEN_VSX_HELPER_2(xscvdpsxds, 0x10, 0x15, 0, PPC2_VSX)
diff --git a/target/ppc/translate/vsx-ops.inc.c b/target/ppc/translate/vsx-ops.inc.c
index 1155765..0704d7a 100644
--- a/target/ppc/translate/vsx-ops.inc.c
+++ b/target/ppc/translate/vsx-ops.inc.c
@@ -152,8 +152,10 @@ GEN_VSX_XFORM_300(xscmpoqp, 0x04, 0x04, 0x00600001),
GEN_VSX_XFORM_300(xscmpuqp, 0x04, 0x14, 0x00600001),
GEN_XX3FORM(xsmaxdp, 0x00, 0x14, PPC2_VSX),
GEN_XX3FORM(xsmindp, 0x00, 0x15, PPC2_VSX),
+GEN_XX2FORM_EO(xscvdphp, 0x16, 0x15, 0x11, PPC2_ISA300),
GEN_XX2FORM(xscvdpsp, 0x12, 0x10, PPC2_VSX),
GEN_XX2FORM(xscvdpspn, 0x16, 0x10, PPC2_VSX207),
+GEN_XX2FORM_EO(xscvhpdp, 0x16, 0x15, 0x10, PPC2_ISA300),
GEN_XX2FORM(xscvspdp, 0x12, 0x14, PPC2_VSX),
GEN_XX2FORM(xscvspdpn, 0x16, 0x14, PPC2_VSX207),
GEN_XX2FORM(xscvdpsxds, 0x10, 0x15, PPC2_VSX),
--
2.7.4
^ permalink raw reply related [flat|nested] 21+ messages in thread* [Qemu-devel] [PATCH v1 08/14] target-ppc: Use correct precision for FPRF setting
2017-01-06 6:14 [Qemu-devel] [PATCH v1 00/14] POWER9 TCG enablements - part10 Nikunj A Dadhania
` (6 preceding siblings ...)
2017-01-06 6:14 ` [Qemu-devel] [PATCH v1 07/14] target-ppc: Add xscvdphp, xscvhpdp Nikunj A Dadhania
@ 2017-01-06 6:14 ` Nikunj A Dadhania
2017-01-06 6:14 ` [Qemu-devel] [PATCH v1 09/14] target-ppc: Add xscvdpqp instruction Nikunj A Dadhania
` (6 subsequent siblings)
14 siblings, 0 replies; 21+ messages in thread
From: Nikunj A Dadhania @ 2017-01-06 6:14 UTC (permalink / raw)
To: qemu-ppc, david, rth; +Cc: qemu-devel, bharata, nikunj
From: Bharata B Rao <bharata@linux.vnet.ibm.com>
Use correct FP precision when setting FPRF in FP conversion helpers
instead of always assuming float64 precision.
Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com>
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
target/ppc/fpu_helper.c | 4 ++--
target/ppc/internal.h | 1 +
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index aacfd12..05b2926 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -109,6 +109,7 @@ void helper_compute_fprf_##tp(CPUPPCState *env, tp arg) \
}
COMPUTE_FPRF(float16)
+COMPUTE_FPRF(float32)
COMPUTE_FPRF(float64)
COMPUTE_FPRF(float128)
@@ -2688,8 +2689,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \
xt.tfld = ttp##_snan_to_qnan(xt.tfld); \
} \
if (sfprf) { \
- helper_compute_fprf_float64(env, ttp##_to_float64(xt.tfld, \
- &env->fp_status)); \
+ helper_compute_fprf_##ttp(env, xt.tfld); \
} \
} \
\
diff --git a/target/ppc/internal.h b/target/ppc/internal.h
index 16fc117..8dcc679 100644
--- a/target/ppc/internal.h
+++ b/target/ppc/internal.h
@@ -246,4 +246,5 @@ static inline void putVSR(int n, ppc_vsr_t *vsr, CPUPPCState *env)
void helper_compute_fprf_float128(CPUPPCState *env, float128 arg);
void helper_compute_fprf_float16(CPUPPCState *env, float16 arg);
+void helper_compute_fprf_float32(CPUPPCState *env, float32 arg);
#endif /* PPC_INTERNAL_H */
--
2.7.4
^ permalink raw reply related [flat|nested] 21+ messages in thread* [Qemu-devel] [PATCH v1 09/14] target-ppc: Add xscvdpqp instruction
2017-01-06 6:14 [Qemu-devel] [PATCH v1 00/14] POWER9 TCG enablements - part10 Nikunj A Dadhania
` (7 preceding siblings ...)
2017-01-06 6:14 ` [Qemu-devel] [PATCH v1 08/14] target-ppc: Use correct precision for FPRF setting Nikunj A Dadhania
@ 2017-01-06 6:14 ` Nikunj A Dadhania
2017-01-06 6:14 ` [Qemu-devel] [PATCH v1 10/14] target-ppc: Add xscvqpdp instruction Nikunj A Dadhania
` (5 subsequent siblings)
14 siblings, 0 replies; 21+ messages in thread
From: Nikunj A Dadhania @ 2017-01-06 6:14 UTC (permalink / raw)
To: qemu-ppc, david, rth; +Cc: qemu-devel, bharata, nikunj
From: Bharata B Rao <bharata@linux.vnet.ibm.com>
xscvdpqp: VSX Scalar Convert Double-Precision format to
Quad-Precision format
Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com>
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
target/ppc/fpu_helper.c | 10 ++++++++++
target/ppc/helper.h | 1 +
target/ppc/translate/vsx-impl.inc.c | 1 +
target/ppc/translate/vsx-ops.inc.c | 1 +
4 files changed, 13 insertions(+)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index 05b2926..224876b 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -22,6 +22,15 @@
#include "exec/exec-all.h"
#include "internal.h"
+static inline float128 float128_snan_to_qnan(float128 x)
+{
+ float128 r;
+
+ r.high = x.high | 0x0000800000000000;
+ r.low = x.low;
+ return r;
+}
+
#define float64_snan_to_qnan(x) ((x) | 0x0008000000000000ULL)
#define float32_snan_to_qnan(x) ((x) | 0x00400000)
#define float16_snan_to_qnan(x) ((x) | 0x0200)
@@ -2701,6 +2710,7 @@ VSX_CVT_FP_TO_FP(xscvdpsp, 1, float64, float32, VsrD(0), VsrW(0), 1)
VSX_CVT_FP_TO_FP(xscvspdp, 1, float32, float64, VsrW(0), VsrD(0), 1)
VSX_CVT_FP_TO_FP(xvcvdpsp, 2, float64, float32, VsrD(i), VsrW(2*i), 0)
VSX_CVT_FP_TO_FP(xvcvspdp, 2, float32, float64, VsrW(2*i), VsrD(i), 0)
+VSX_CVT_FP_TO_FP(xscvdpqp, 1, float64, float128, VsrD(0), f128, 1)
/* VSX_CVT_FP_TO_FP_HP - VSX floating point/floating point conversion
* involving one half precision value
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 889fe55..3b5d0ad 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -430,6 +430,7 @@ DEF_HELPER_2(xscmpuqp, void, env, i32)
DEF_HELPER_2(xsmaxdp, void, env, i32)
DEF_HELPER_2(xsmindp, void, env, i32)
DEF_HELPER_2(xscvdphp, void, env, i32)
+DEF_HELPER_2(xscvdpqp, void, env, i32)
DEF_HELPER_2(xscvdpsp, void, env, i32)
DEF_HELPER_2(xscvdpspn, i64, env, i64)
DEF_HELPER_2(xscvhpdp, void, env, i32)
diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c
index 16242f2..358ff4c 100644
--- a/target/ppc/translate/vsx-impl.inc.c
+++ b/target/ppc/translate/vsx-impl.inc.c
@@ -808,6 +808,7 @@ GEN_VSX_HELPER_2(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xsmindp, 0x00, 0x15, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xscvdphp, 0x16, 0x15, 0x11, PPC2_ISA300)
GEN_VSX_HELPER_2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX)
+GEN_VSX_HELPER_2(xscvdpqp, 0x04, 0x1A, 0x16, PPC2_ISA300)
GEN_VSX_HELPER_XT_XB_ENV(xscvdpspn, 0x16, 0x10, 0, PPC2_VSX207)
GEN_VSX_HELPER_2(xscvhpdp, 0x16, 0x15, 0x10, PPC2_ISA300)
GEN_VSX_HELPER_2(xscvspdp, 0x12, 0x14, 0, PPC2_VSX)
diff --git a/target/ppc/translate/vsx-ops.inc.c b/target/ppc/translate/vsx-ops.inc.c
index 0704d7a..fcf9597 100644
--- a/target/ppc/translate/vsx-ops.inc.c
+++ b/target/ppc/translate/vsx-ops.inc.c
@@ -112,6 +112,7 @@ GEN_VSX_XFORM_300_EO(xsabsqp, 0x04, 0x19, 0x00, 0x00000001),
GEN_VSX_XFORM_300_EO(xsnabsqp, 0x04, 0x19, 0x08, 0x00000001),
GEN_VSX_XFORM_300_EO(xsnegqp, 0x04, 0x19, 0x10, 0x00000001),
GEN_VSX_XFORM_300(xscpsgnqp, 0x04, 0x03, 0x00000001),
+GEN_VSX_XFORM_300_EO(xscvdpqp, 0x04, 0x1A, 0x16, 0x00000001),
GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),
GEN_XX2FORM(xvnabsdp, 0x12, 0x1E, PPC2_VSX),
--
2.7.4
^ permalink raw reply related [flat|nested] 21+ messages in thread* [Qemu-devel] [PATCH v1 10/14] target-ppc: Add xscvqpdp instruction
2017-01-06 6:14 [Qemu-devel] [PATCH v1 00/14] POWER9 TCG enablements - part10 Nikunj A Dadhania
` (8 preceding siblings ...)
2017-01-06 6:14 ` [Qemu-devel] [PATCH v1 09/14] target-ppc: Add xscvdpqp instruction Nikunj A Dadhania
@ 2017-01-06 6:14 ` Nikunj A Dadhania
2017-01-06 6:14 ` [Qemu-devel] [PATCH v1 11/14] target-ppc: Add xsxexpdp instruction Nikunj A Dadhania
` (4 subsequent siblings)
14 siblings, 0 replies; 21+ messages in thread
From: Nikunj A Dadhania @ 2017-01-06 6:14 UTC (permalink / raw)
To: qemu-ppc, david, rth; +Cc: qemu-devel, bharata, nikunj
From: Bharata B Rao <bharata@linux.vnet.ibm.com>
xscvqpdp: VSX Scalar round & Convert Quad-Precision format to
Double-Precision format
Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com>
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
target/ppc/fpu_helper.c | 28 ++++++++++++++++++++++++++++
target/ppc/helper.h | 1 +
target/ppc/translate/vsx-impl.inc.c | 1 +
target/ppc/translate/vsx-ops.inc.c | 1 +
4 files changed, 31 insertions(+)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index 224876b..dfd3515 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -2743,6 +2743,34 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \
VSX_CVT_FP_TO_FP_HP(xscvdphp, float64, float16, VsrD(0), VsrH(3))
VSX_CVT_FP_TO_FP_HP(xscvhpdp, float16, float64, VsrH(3), VsrD(0))
+/*
+ * xscvqpdp isn't using VSX_CVT_FP_TO_FP() because xscvqpdpo will be
+ * added to this later.
+ */
+void helper_xscvqpdp(CPUPPCState *env, uint32_t opcode)
+{
+ ppc_vsr_t xt, xb;
+
+ getVSR(xB(opcode), &xb, env);
+ getVSR(xT(opcode), &xt, env);
+
+ if (unlikely(Rc(opcode) != 0)) {
+ /* TODO: Support xscvqpdpo after round-to-odd is implemented */
+ abort();
+ }
+
+ xt.VsrD(0) = float128_to_float64(xb.f128, &env->fp_status);
+ if (unlikely(float128_is_signaling_nan(xb.f128,
+ &env->fp_status))) {
+ float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0);
+ xt.VsrD(0) = float64_snan_to_qnan(xt.VsrD(0));
+ }
+ helper_compute_fprf_float64(env, xt.VsrD(0));
+
+ putVSR(xT(opcode), &xt, env);
+ float_check_status(env);
+}
+
uint64_t helper_xscvdpspn(CPUPPCState *env, uint64_t xb)
{
float_status tstat = env->fp_status;
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 3b5d0ad..f28bf62 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -433,6 +433,7 @@ DEF_HELPER_2(xscvdphp, void, env, i32)
DEF_HELPER_2(xscvdpqp, void, env, i32)
DEF_HELPER_2(xscvdpsp, void, env, i32)
DEF_HELPER_2(xscvdpspn, i64, env, i64)
+DEF_HELPER_2(xscvqpdp, void, env, i32)
DEF_HELPER_2(xscvhpdp, void, env, i32)
DEF_HELPER_2(xscvspdp, void, env, i32)
DEF_HELPER_2(xscvspdpn, i64, env, i64)
diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c
index 358ff4c..d9cdaf1 100644
--- a/target/ppc/translate/vsx-impl.inc.c
+++ b/target/ppc/translate/vsx-impl.inc.c
@@ -810,6 +810,7 @@ GEN_VSX_HELPER_2(xscvdphp, 0x16, 0x15, 0x11, PPC2_ISA300)
GEN_VSX_HELPER_2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xscvdpqp, 0x04, 0x1A, 0x16, PPC2_ISA300)
GEN_VSX_HELPER_XT_XB_ENV(xscvdpspn, 0x16, 0x10, 0, PPC2_VSX207)
+GEN_VSX_HELPER_2(xscvqpdp, 0x04, 0x1A, 0x14, PPC2_ISA300)
GEN_VSX_HELPER_2(xscvhpdp, 0x16, 0x15, 0x10, PPC2_ISA300)
GEN_VSX_HELPER_2(xscvspdp, 0x12, 0x14, 0, PPC2_VSX)
GEN_VSX_HELPER_XT_XB_ENV(xscvspdpn, 0x16, 0x14, 0, PPC2_VSX207)
diff --git a/target/ppc/translate/vsx-ops.inc.c b/target/ppc/translate/vsx-ops.inc.c
index fcf9597..cc5b268 100644
--- a/target/ppc/translate/vsx-ops.inc.c
+++ b/target/ppc/translate/vsx-ops.inc.c
@@ -113,6 +113,7 @@ GEN_VSX_XFORM_300_EO(xsnabsqp, 0x04, 0x19, 0x08, 0x00000001),
GEN_VSX_XFORM_300_EO(xsnegqp, 0x04, 0x19, 0x10, 0x00000001),
GEN_VSX_XFORM_300(xscpsgnqp, 0x04, 0x03, 0x00000001),
GEN_VSX_XFORM_300_EO(xscvdpqp, 0x04, 0x1A, 0x16, 0x00000001),
+GEN_VSX_XFORM_300_EO(xscvqpdp, 0x04, 0x1A, 0x14, 0x0),
GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),
GEN_XX2FORM(xvnabsdp, 0x12, 0x1E, PPC2_VSX),
--
2.7.4
^ permalink raw reply related [flat|nested] 21+ messages in thread* [Qemu-devel] [PATCH v1 11/14] target-ppc: Add xsxexpdp instruction
2017-01-06 6:14 [Qemu-devel] [PATCH v1 00/14] POWER9 TCG enablements - part10 Nikunj A Dadhania
` (9 preceding siblings ...)
2017-01-06 6:14 ` [Qemu-devel] [PATCH v1 10/14] target-ppc: Add xscvqpdp instruction Nikunj A Dadhania
@ 2017-01-06 6:14 ` Nikunj A Dadhania
2017-01-06 6:14 ` [Qemu-devel] [PATCH v1 12/14] target-ppc: Add xsxexpqp instruction Nikunj A Dadhania
` (3 subsequent siblings)
14 siblings, 0 replies; 21+ messages in thread
From: Nikunj A Dadhania @ 2017-01-06 6:14 UTC (permalink / raw)
To: qemu-ppc, david, rth; +Cc: qemu-devel, bharata, nikunj
xsxexpdp: VSX Scalar Extract Exponent Dual Precision
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
target/ppc/translate/vsx-impl.inc.c | 13 +++++++++++++
target/ppc/translate/vsx-ops.inc.c | 4 ++++
2 files changed, 17 insertions(+)
diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c
index d9cdaf1..b8ff31e 100644
--- a/target/ppc/translate/vsx-impl.inc.c
+++ b/target/ppc/translate/vsx-impl.inc.c
@@ -1216,6 +1216,19 @@ static void gen_##name(DisasContext *ctx) \
VSX_EXTRACT_INSERT(xxextractuw)
VSX_EXTRACT_INSERT(xxinsertw)
+#ifdef TARGET_PPC64
+static void gen_xsxexpdp(DisasContext *ctx)
+{
+ TCGv rt = cpu_gpr[rD(ctx->opcode)];
+ if (unlikely(!ctx->vsx_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VSXU);
+ return;
+ }
+ tcg_gen_shri_i64(rt, cpu_vsrh(xB(ctx->opcode)), 52);
+ tcg_gen_andi_i64(rt, rt, 0x7FF);
+}
+#endif
+
#undef GEN_XX2FORM
#undef GEN_XX3FORM
#undef GEN_XX2IFORM
diff --git a/target/ppc/translate/vsx-ops.inc.c b/target/ppc/translate/vsx-ops.inc.c
index cc5b268..2243a1f 100644
--- a/target/ppc/translate/vsx-ops.inc.c
+++ b/target/ppc/translate/vsx-ops.inc.c
@@ -115,6 +115,10 @@ GEN_VSX_XFORM_300(xscpsgnqp, 0x04, 0x03, 0x00000001),
GEN_VSX_XFORM_300_EO(xscvdpqp, 0x04, 0x1A, 0x16, 0x00000001),
GEN_VSX_XFORM_300_EO(xscvqpdp, 0x04, 0x1A, 0x14, 0x0),
+#ifdef TARGET_PPC64
+GEN_XX2FORM_EO(xsxexpdp, 0x16, 0x15, 0x00, PPC2_ISA300),
+#endif
+
GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),
GEN_XX2FORM(xvnabsdp, 0x12, 0x1E, PPC2_VSX),
GEN_XX2FORM(xvnegdp, 0x12, 0x1F, PPC2_VSX),
--
2.7.4
^ permalink raw reply related [flat|nested] 21+ messages in thread* [Qemu-devel] [PATCH v1 12/14] target-ppc: Add xsxexpqp instruction
2017-01-06 6:14 [Qemu-devel] [PATCH v1 00/14] POWER9 TCG enablements - part10 Nikunj A Dadhania
` (10 preceding siblings ...)
2017-01-06 6:14 ` [Qemu-devel] [PATCH v1 11/14] target-ppc: Add xsxexpdp instruction Nikunj A Dadhania
@ 2017-01-06 6:14 ` Nikunj A Dadhania
2017-01-06 6:14 ` [Qemu-devel] [PATCH v1 13/14] target-ppc: Add xsxsigdp instruction Nikunj A Dadhania
` (2 subsequent siblings)
14 siblings, 0 replies; 21+ messages in thread
From: Nikunj A Dadhania @ 2017-01-06 6:14 UTC (permalink / raw)
To: qemu-ppc, david, rth; +Cc: qemu-devel, bharata, nikunj
xsxexpqp: VSX Scalar Extract Exponent Quad Precision
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
target/ppc/translate/vsx-impl.inc.c | 15 +++++++++++++++
target/ppc/translate/vsx-ops.inc.c | 1 +
2 files changed, 16 insertions(+)
diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c
index b8ff31e..514a273 100644
--- a/target/ppc/translate/vsx-impl.inc.c
+++ b/target/ppc/translate/vsx-impl.inc.c
@@ -1227,6 +1227,21 @@ static void gen_xsxexpdp(DisasContext *ctx)
tcg_gen_shri_i64(rt, cpu_vsrh(xB(ctx->opcode)), 52);
tcg_gen_andi_i64(rt, rt, 0x7FF);
}
+
+static void gen_xsxexpqp(DisasContext *ctx)
+{
+ TCGv_i64 xth = cpu_vsrh(rD(ctx->opcode) + 32);
+ TCGv_i64 xtl = cpu_vsrl(rD(ctx->opcode) + 32);
+ TCGv_i64 xbh = cpu_vsrh(rB(ctx->opcode) + 32);
+
+ if (unlikely(!ctx->vsx_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VSXU);
+ return;
+ }
+ tcg_gen_shri_i64(xth, xbh, 48);
+ tcg_gen_andi_i64(xth, xth, 0x7FFF);
+ tcg_gen_movi_i64(xtl, 0);
+}
#endif
#undef GEN_XX2FORM
diff --git a/target/ppc/translate/vsx-ops.inc.c b/target/ppc/translate/vsx-ops.inc.c
index 2243a1f..2ea8ce4 100644
--- a/target/ppc/translate/vsx-ops.inc.c
+++ b/target/ppc/translate/vsx-ops.inc.c
@@ -117,6 +117,7 @@ GEN_VSX_XFORM_300_EO(xscvqpdp, 0x04, 0x1A, 0x14, 0x0),
#ifdef TARGET_PPC64
GEN_XX2FORM_EO(xsxexpdp, 0x16, 0x15, 0x00, PPC2_ISA300),
+GEN_VSX_XFORM_300_EO(xsxexpqp, 0x04, 0x19, 0x02, 0x00000001),
#endif
GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),
--
2.7.4
^ permalink raw reply related [flat|nested] 21+ messages in thread* [Qemu-devel] [PATCH v1 13/14] target-ppc: Add xsxsigdp instruction
2017-01-06 6:14 [Qemu-devel] [PATCH v1 00/14] POWER9 TCG enablements - part10 Nikunj A Dadhania
` (11 preceding siblings ...)
2017-01-06 6:14 ` [Qemu-devel] [PATCH v1 12/14] target-ppc: Add xsxexpqp instruction Nikunj A Dadhania
@ 2017-01-06 6:14 ` Nikunj A Dadhania
2017-01-06 6:14 ` [Qemu-devel] [PATCH v1 14/14] target-ppc: Add xsxsigqp instructions Nikunj A Dadhania
2017-01-09 2:49 ` [Qemu-devel] [PATCH v1 00/14] POWER9 TCG enablements - part10 David Gibson
14 siblings, 0 replies; 21+ messages in thread
From: Nikunj A Dadhania @ 2017-01-06 6:14 UTC (permalink / raw)
To: qemu-ppc, david, rth; +Cc: qemu-devel, bharata, nikunj
xsxsigdp: VSX Scalar Extract Significand Dual Precision
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
target/ppc/translate/vsx-impl.inc.c | 29 +++++++++++++++++++++++++++++
target/ppc/translate/vsx-ops.inc.c | 1 +
2 files changed, 30 insertions(+)
diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c
index 514a273..1fea8dc 100644
--- a/target/ppc/translate/vsx-impl.inc.c
+++ b/target/ppc/translate/vsx-impl.inc.c
@@ -1242,6 +1242,35 @@ static void gen_xsxexpqp(DisasContext *ctx)
tcg_gen_andi_i64(xth, xth, 0x7FFF);
tcg_gen_movi_i64(xtl, 0);
}
+
+static void gen_xsxsigdp(DisasContext *ctx)
+{
+ TCGv rt = cpu_gpr[rD(ctx->opcode)];
+ TCGv_i64 t0, zr, nan, exp;
+
+ if (unlikely(!ctx->vsx_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VSXU);
+ return;
+ }
+ exp = tcg_temp_new_i64();
+ t0 = tcg_temp_new_i64();
+ zr = tcg_const_i64(0);
+ nan = tcg_const_i64(2047);
+
+ tcg_gen_shri_i64(exp, cpu_vsrh(xB(ctx->opcode)), 52);
+ tcg_gen_andi_i64(exp, exp, 0x7FF);
+ tcg_gen_movi_i64(t0, 0x0010000000000000);
+ tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, zr, zr, t0);
+ tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, nan, zr, t0);
+ tcg_gen_andi_i64(rt, cpu_vsrh(xB(ctx->opcode)), 0x000FFFFFFFFFFFFF);
+ tcg_gen_or_i64(rt, rt, t0);
+
+ tcg_temp_free_i64(t0);
+ tcg_temp_free_i64(exp);
+ tcg_temp_free_i64(zr);
+ tcg_temp_free_i64(nan);
+}
+
#endif
#undef GEN_XX2FORM
diff --git a/target/ppc/translate/vsx-ops.inc.c b/target/ppc/translate/vsx-ops.inc.c
index 2ea8ce4..c7791f8 100644
--- a/target/ppc/translate/vsx-ops.inc.c
+++ b/target/ppc/translate/vsx-ops.inc.c
@@ -118,6 +118,7 @@ GEN_VSX_XFORM_300_EO(xscvqpdp, 0x04, 0x1A, 0x14, 0x0),
#ifdef TARGET_PPC64
GEN_XX2FORM_EO(xsxexpdp, 0x16, 0x15, 0x00, PPC2_ISA300),
GEN_VSX_XFORM_300_EO(xsxexpqp, 0x04, 0x19, 0x02, 0x00000001),
+GEN_XX2FORM_EO(xsxsigdp, 0x16, 0x15, 0x01, PPC2_ISA300),
#endif
GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),
--
2.7.4
^ permalink raw reply related [flat|nested] 21+ messages in thread* [Qemu-devel] [PATCH v1 14/14] target-ppc: Add xsxsigqp instructions
2017-01-06 6:14 [Qemu-devel] [PATCH v1 00/14] POWER9 TCG enablements - part10 Nikunj A Dadhania
` (12 preceding siblings ...)
2017-01-06 6:14 ` [Qemu-devel] [PATCH v1 13/14] target-ppc: Add xsxsigdp instruction Nikunj A Dadhania
@ 2017-01-06 6:14 ` Nikunj A Dadhania
2017-01-09 2:49 ` [Qemu-devel] [PATCH v1 00/14] POWER9 TCG enablements - part10 David Gibson
14 siblings, 0 replies; 21+ messages in thread
From: Nikunj A Dadhania @ 2017-01-06 6:14 UTC (permalink / raw)
To: qemu-ppc, david, rth; +Cc: qemu-devel, bharata, nikunj
xsxsigqp: VSX Scalar Extract Significand Quad Precision
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
target/ppc/translate/vsx-impl.inc.c | 29 +++++++++++++++++++++++++++++
target/ppc/translate/vsx-ops.inc.c | 1 +
2 files changed, 30 insertions(+)
diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c
index 1fea8dc..2d9fe50 100644
--- a/target/ppc/translate/vsx-impl.inc.c
+++ b/target/ppc/translate/vsx-impl.inc.c
@@ -1271,6 +1271,35 @@ static void gen_xsxsigdp(DisasContext *ctx)
tcg_temp_free_i64(nan);
}
+static void gen_xsxsigqp(DisasContext *ctx)
+{
+ TCGv_i64 t0, zr, nan, exp;
+ TCGv_i64 xth = cpu_vsrh(rD(ctx->opcode) + 32);
+ TCGv_i64 xtl = cpu_vsrl(rD(ctx->opcode) + 32);
+
+ if (unlikely(!ctx->vsx_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VSXU);
+ return;
+ }
+ exp = tcg_temp_new_i64();
+ t0 = tcg_temp_new_i64();
+ zr = tcg_const_i64(0);
+ nan = tcg_const_i64(32767);
+
+ tcg_gen_shri_i64(exp, cpu_vsrh(rB(ctx->opcode) + 32), 48);
+ tcg_gen_andi_i64(exp, exp, 0x7FFF);
+ tcg_gen_movi_i64(t0, 0x0001000000000000);
+ tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, zr, zr, t0);
+ tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, nan, zr, t0);
+ tcg_gen_andi_i64(xth, cpu_vsrh(rB(ctx->opcode) + 32), 0x0000FFFFFFFFFFFF);
+ tcg_gen_or_i64(xth, xth, t0);
+ tcg_gen_mov_i64(xtl, cpu_vsrl(rB(ctx->opcode) + 32));
+
+ tcg_temp_free_i64(t0);
+ tcg_temp_free_i64(exp);
+ tcg_temp_free_i64(zr);
+ tcg_temp_free_i64(nan);
+}
#endif
#undef GEN_XX2FORM
diff --git a/target/ppc/translate/vsx-ops.inc.c b/target/ppc/translate/vsx-ops.inc.c
index c7791f8..aeeaff2 100644
--- a/target/ppc/translate/vsx-ops.inc.c
+++ b/target/ppc/translate/vsx-ops.inc.c
@@ -119,6 +119,7 @@ GEN_VSX_XFORM_300_EO(xscvqpdp, 0x04, 0x1A, 0x14, 0x0),
GEN_XX2FORM_EO(xsxexpdp, 0x16, 0x15, 0x00, PPC2_ISA300),
GEN_VSX_XFORM_300_EO(xsxexpqp, 0x04, 0x19, 0x02, 0x00000001),
GEN_XX2FORM_EO(xsxsigdp, 0x16, 0x15, 0x01, PPC2_ISA300),
+GEN_VSX_XFORM_300_EO(xsxsigqp, 0x04, 0x19, 0x12, 0x00000001),
#endif
GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),
--
2.7.4
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [Qemu-devel] [PATCH v1 00/14] POWER9 TCG enablements - part10
2017-01-06 6:14 [Qemu-devel] [PATCH v1 00/14] POWER9 TCG enablements - part10 Nikunj A Dadhania
` (13 preceding siblings ...)
2017-01-06 6:14 ` [Qemu-devel] [PATCH v1 14/14] target-ppc: Add xsxsigqp instructions Nikunj A Dadhania
@ 2017-01-09 2:49 ` David Gibson
2017-01-09 6:51 ` Nikunj A Dadhania
14 siblings, 1 reply; 21+ messages in thread
From: David Gibson @ 2017-01-09 2:49 UTC (permalink / raw)
To: Nikunj A Dadhania; +Cc: qemu-ppc, rth, qemu-devel, bharata
[-- Attachment #1: Type: text/plain, Size: 1851 bytes --]
On Fri, Jan 06, 2017 at 11:44:42AM +0530, Nikunj A Dadhania wrote:
> This series contains 11 new instructions for POWER9 ISA3.0
> VSX Vector Insert/Extract Word
> VSX Scalar Extract Exponent/Significand
> VSX Scalar Convert
> VSX Scalar Add QP
> Various float related improvements
Applied to ppc-for-2.9, thanks.
>
> Changelog:
> v0:
> Rebase and update reviewed-by
>
> Bharata B Rao (8):
> target-ppc: Use float64 arg in helper_compute_fprf()
> target-ppc: Replace isden by float64_is_zero_or_denormal
> target-ppc: Rename helper_compute_fprf to helper_compute_fprf_float64
> target-ppc: Add xsaddqp instructions
> target-ppc: Add xscvdphp, xscvhpdp
> target-ppc: Use correct precision for FPRF setting
> target-ppc: Add xscvdpqp instruction
> target-ppc: Add xscvqpdp instruction
>
> Nikunj A Dadhania (6):
> target-ppc: Add xxextractuw instruction
> target-ppc: Add xxinsertw instruction
> target-ppc: Add xsxexpdp instruction
> target-ppc: Add xsxexpqp instruction
> target-ppc: Add xsxsigdp instruction
> target-ppc: Add xsxsigqp instructions
>
> include/fpu/softfloat.h | 20 +++
> target/ppc/fpu_helper.c | 241 +++++++++++++++++++++++++-----------
> target/ppc/helper.h | 9 +-
> target/ppc/int_helper.c | 51 ++++++++
> target/ppc/internal.h | 6 +
> target/ppc/translate/fp-impl.inc.c | 20 +--
> target/ppc/translate/vsx-impl.inc.c | 122 ++++++++++++++++++
> target/ppc/translate/vsx-ops.inc.c | 18 +++
> 8 files changed, 405 insertions(+), 82 deletions(-)
>
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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^ permalink raw reply [flat|nested] 21+ messages in thread* Re: [Qemu-devel] [PATCH v1 00/14] POWER9 TCG enablements - part10
2017-01-09 2:49 ` [Qemu-devel] [PATCH v1 00/14] POWER9 TCG enablements - part10 David Gibson
@ 2017-01-09 6:51 ` Nikunj A Dadhania
0 siblings, 0 replies; 21+ messages in thread
From: Nikunj A Dadhania @ 2017-01-09 6:51 UTC (permalink / raw)
To: David Gibson; +Cc: qemu-ppc, rth, qemu-devel, bharata
David Gibson <david@gibson.dropbear.id.au> writes:
> [ Unknown signature status ]
> On Fri, Jan 06, 2017 at 11:44:42AM +0530, Nikunj A Dadhania wrote:
>> This series contains 11 new instructions for POWER9 ISA3.0
>> VSX Vector Insert/Extract Word
>> VSX Scalar Extract Exponent/Significand
>> VSX Scalar Convert
>> VSX Scalar Add QP
>> Various float related improvements
>
> Applied to ppc-for-2.9, thanks.
Found issue in register numbering in 3 instructions.
xsaddqp
xscvdpqp
xscvqpdp
Please drop following:
target-ppc: Add xsaddqp instructions
target-ppc: Add xscvdpqp instruction
target-ppc: Add xscvqpdp instruction
I will resend them.
Regards
Nikunj
^ permalink raw reply [flat|nested] 21+ messages in thread