From: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
To: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au
Cc: qemu-devel@nongnu.org, bharata@linux.vnet.ibm.com,
nikunj@linux.vnet.ibm.com
Subject: [Qemu-devel] [PATCH v2 0/3] POWER9 TCG enablements - part10
Date: Mon, 9 Jan 2017 19:56:12 +0530 [thread overview]
Message-ID: <1483971975-5612-1-git-send-email-nikunj@linux.vnet.ibm.com> (raw)
This series contains 11 new instructions for POWER9 ISA3.0
VSX Scalar Convert
VSX Scalar Add QP
Changelog:
v1:
* xsaddqp, xscv[dpqp, qpdp] instructions use register numbering 0-31, this needs
to be handled in the decoding. ISA 3.0 documents to use them as VSR[VRA + 32],
and likewise for other registers.
v0:
Rebase and update reviewed-by
Bharata B Rao (3):
target-ppc: Add xsaddqp instructions
target-ppc: Add xscvdpqp instruction
target-ppc: Add xscvqpdp instruction
target/ppc/fpu_helper.c | 109 ++++++++++++++++++++++++++++++++++++
target/ppc/helper.h | 3 +
target/ppc/internal.h | 1 +
target/ppc/translate/vsx-impl.inc.c | 3 +
target/ppc/translate/vsx-ops.inc.c | 3 +
5 files changed, 119 insertions(+)
--
2.7.4
next reply other threads:[~2017-01-09 14:26 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-01-09 14:26 Nikunj A Dadhania [this message]
2017-01-09 14:26 ` [Qemu-devel] [PATCH v2 1/3] target-ppc: Add xsaddqp instructions Nikunj A Dadhania
2017-01-09 14:26 ` [Qemu-devel] [PATCH v2 2/3] target-ppc: Add xscvdpqp instruction Nikunj A Dadhania
2017-01-09 14:26 ` [Qemu-devel] [PATCH v2 3/3] target-ppc: Add xscvqpdp instruction Nikunj A Dadhania
2017-01-10 0:26 ` [Qemu-devel] [PATCH v2 0/3] POWER9 TCG enablements - part10 David Gibson
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