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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-arm@nongnu.org, qemu-devel@nongnu.org
Cc: patches@linaro.org, Andrew Jones <drjones@redhat.com>,
	Christoffer Dall <christoffer.dall@linaro.org>,
	"Edgar E . Iglesias" <edgar.iglesias@xilinx.com>,
	Alistair Francis <alistair.francis@xilinx.com>
Subject: [Qemu-devel] [PATCH v2 01/18] hw/intc/arm_gicv3: Add external IRQ lines for VIRQ and VFIQ
Date: Mon,  9 Jan 2017 16:05:07 +0000	[thread overview]
Message-ID: <1483977924-14522-2-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1483977924-14522-1-git-send-email-peter.maydell@linaro.org>

Augment the GICv3's QOM device interface by adding two
new sets of sysbus IRQ lines, to signal VIRQ and VFIQ to
each CPU.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/intc/arm_gicv3_common.h | 2 ++
 hw/intc/arm_gicv3_common.c         | 6 ++++++
 2 files changed, 8 insertions(+)

diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3_common.h
index 341a311..beb2c77 100644
--- a/include/hw/intc/arm_gicv3_common.h
+++ b/include/hw/intc/arm_gicv3_common.h
@@ -145,6 +145,8 @@ struct GICv3CPUState {
     CPUState *cpu;
     qemu_irq parent_irq;
     qemu_irq parent_fiq;
+    qemu_irq parent_virq;
+    qemu_irq parent_vfiq;
 
     /* Redistributor */
     uint32_t level;                  /* Current IRQ level */
diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c
index 0aa9b9c..0ee67a4 100644
--- a/hw/intc/arm_gicv3_common.c
+++ b/hw/intc/arm_gicv3_common.c
@@ -126,6 +126,12 @@ void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler,
     for (i = 0; i < s->num_cpu; i++) {
         sysbus_init_irq(sbd, &s->cpu[i].parent_fiq);
     }
+    for (i = 0; i < s->num_cpu; i++) {
+        sysbus_init_irq(sbd, &s->cpu[i].parent_virq);
+    }
+    for (i = 0; i < s->num_cpu; i++) {
+        sysbus_init_irq(sbd, &s->cpu[i].parent_vfiq);
+    }
 
     memory_region_init_io(&s->iomem_dist, OBJECT(s), ops, s,
                           "gicv3_dist", 0x10000);
-- 
2.7.4

  reply	other threads:[~2017-01-09 16:05 UTC|newest]

Thread overview: 37+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-01-09 16:05 [Qemu-devel] [PATCH v2 00/18] arm: Add virtualization to GICv3, and enable EL2 on 64-bit CPUs Peter Maydell
2017-01-09 16:05 ` Peter Maydell [this message]
2017-01-17 21:49   ` [Qemu-devel] [PATCH v2 01/18] hw/intc/arm_gicv3: Add external IRQ lines for VIRQ and VFIQ Alistair Francis
2017-01-09 16:05 ` [Qemu-devel] [PATCH v2 02/18] hw/intc/arm_gic: " Peter Maydell
2017-01-10 16:49   ` Edgar E. Iglesias
2017-01-09 16:05 ` [Qemu-devel] [PATCH v2 03/18] target-arm: Expose output GPIO line for VCPU maintenance interrupt Peter Maydell
2017-01-17 21:50   ` Alistair Francis
2017-01-09 16:05 ` [Qemu-devel] [PATCH v2 04/18] hw/arm/virt: Wire VIRQ, VFIQ, maintenance irq lines from GIC to CPU Peter Maydell
2017-01-10 16:42   ` Edgar E. Iglesias
2017-01-10 17:17     ` Peter Maydell
2017-01-09 16:05 ` [Qemu-devel] [PATCH v2 05/18] target-arm: Add ARMCPU fields for GIC CPU i/f config Peter Maydell
2017-01-17 22:12   ` Alistair Francis
2017-01-09 16:05 ` [Qemu-devel] [PATCH v2 06/18] hw/intc/gicv3: Add defines for ICH system register fields Peter Maydell
2017-01-09 16:05 ` [Qemu-devel] [PATCH v2 07/18] hw/intc/gicv3: Add data fields for virtualization support Peter Maydell
2017-01-17 22:13   ` Alistair Francis
2017-01-09 16:05 ` [Qemu-devel] [PATCH v2 08/18] hw/intc/arm_gicv3: Add accessors for ICH_ system registers Peter Maydell
2017-01-09 16:05 ` [Qemu-devel] [PATCH v2 09/18] hw/intc/arm_gicv3: Implement ICV_ registers which are just accessors Peter Maydell
2017-01-09 16:05 ` [Qemu-devel] [PATCH v2 10/18] hw/intc/arm_gicv3: Implement ICV_ HPPIR, DIR and RPR registers Peter Maydell
2017-01-09 16:05 ` [Qemu-devel] [PATCH v2 11/18] hw/intc/arm_gicv3: Implement ICV_ registers EOIR and IAR Peter Maydell
2017-01-09 16:05 ` [Qemu-devel] [PATCH v2 12/18] hw/intc/arm_gicv3: Implement gicv3_cpuif_virt_update() Peter Maydell
2017-01-09 16:05 ` [Qemu-devel] [PATCH v2 13/18] hw/intc/arm_gicv3: Implement EL2 traps for CPU i/f regs Peter Maydell
2017-01-09 16:05 ` [Qemu-devel] [PATCH v2 14/18] hw/arm/virt: Support using SMC for PSCI Peter Maydell
2017-01-09 16:05 ` [Qemu-devel] [PATCH v2 15/18] hw/arm/virt-acpi-build: use SMC if booting in EL2 Peter Maydell
2017-01-17 22:14   ` Alistair Francis
2017-01-09 16:05 ` [Qemu-devel] [PATCH v2 16/18] target/arm/psci.c: If EL2 implemented, start CPUs " Peter Maydell
2017-01-10 16:36   ` Edgar E. Iglesias
2017-01-17 14:47   ` Andrew Jones
2017-01-09 16:05 ` [Qemu-devel] [PATCH v2 17/18] target-arm: Enable EL2 feature bit on A53 and A57 Peter Maydell
2017-01-09 16:05 ` [Qemu-devel] [PATCH v2 18/18] hw/arm/virt: Add board property to enable EL2 Peter Maydell
2017-01-10 16:45   ` Edgar E. Iglesias
2017-01-17 14:07 ` [Qemu-devel] [Qemu-arm] [PATCH v2 00/18] arm: Add virtualization to GICv3, and enable EL2 on 64-bit CPUs Peter Maydell
2017-01-17 14:49   ` Andrew Jones
2017-01-17 22:16     ` Alistair Francis
2017-01-18  9:17   ` Edgar E. Iglesias
2017-01-19 12:59     ` Peter Maydell
2017-01-19 13:02       ` Edgar E. Iglesias
2017-01-19 13:31         ` Peter Maydell

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