From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-arm@nongnu.org, qemu-devel@nongnu.org
Cc: patches@linaro.org, Andrew Jones <drjones@redhat.com>,
Christoffer Dall <christoffer.dall@linaro.org>,
"Edgar E . Iglesias" <edgar.iglesias@xilinx.com>,
Alistair Francis <alistair.francis@xilinx.com>
Subject: [Qemu-devel] [PATCH v2 04/18] hw/arm/virt: Wire VIRQ, VFIQ, maintenance irq lines from GIC to CPU
Date: Mon, 9 Jan 2017 16:05:10 +0000 [thread overview]
Message-ID: <1483977924-14522-5-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1483977924-14522-1-git-send-email-peter.maydell@linaro.org>
Wire the new VIRQ, VFIQ and maintenance interrupt lines from the
GIC to each CPU.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/arm/virt.h | 2 ++
hw/arm/virt.c | 14 +++++++++++---
2 files changed, 13 insertions(+), 3 deletions(-)
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
index eb1c63d..b8a19ec 100644
--- a/include/hw/arm/virt.h
+++ b/include/hw/arm/virt.h
@@ -39,6 +39,8 @@
#define NUM_GICV2M_SPIS 64
#define NUM_VIRTIO_TRANSPORTS 32
+#define ARCH_GICV3_MAINT_IRQ 9
+
#define ARCH_TIMER_VIRT_IRQ 11
#define ARCH_TIMER_S_EL1_IRQ 13
#define ARCH_TIMER_NS_EL1_IRQ 14
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 7a03f84..b31d302 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -547,9 +547,9 @@ static void create_gic(VirtMachineState *vms, qemu_irq *pic)
sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base);
}
- /* Wire the outputs from each CPU's generic timer to the
- * appropriate GIC PPI inputs, and the GIC's IRQ output to
- * the CPU's IRQ input.
+ /* Wire the outputs from each CPU's generic timer and the GICv3
+ * maintenance interrupt signal to the appropriate GIC PPI inputs,
+ * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs.
*/
for (i = 0; i < smp_cpus; i++) {
DeviceState *cpudev = DEVICE(qemu_get_cpu(i));
@@ -571,9 +571,17 @@ static void create_gic(VirtMachineState *vms, qemu_irq *pic)
ppibase + timer_irq[irq]));
}
+ qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 0,
+ qdev_get_gpio_in(gicdev, ppibase
+ + ARCH_GICV3_MAINT_IRQ));
+
sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
sysbus_connect_irq(gicbusdev, i + smp_cpus,
qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
+ sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus,
+ qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
+ sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus,
+ qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
}
for (i = 0; i < NUM_IRQS; i++) {
--
2.7.4
next prev parent reply other threads:[~2017-01-09 16:05 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-01-09 16:05 [Qemu-devel] [PATCH v2 00/18] arm: Add virtualization to GICv3, and enable EL2 on 64-bit CPUs Peter Maydell
2017-01-09 16:05 ` [Qemu-devel] [PATCH v2 01/18] hw/intc/arm_gicv3: Add external IRQ lines for VIRQ and VFIQ Peter Maydell
2017-01-17 21:49 ` Alistair Francis
2017-01-09 16:05 ` [Qemu-devel] [PATCH v2 02/18] hw/intc/arm_gic: " Peter Maydell
2017-01-10 16:49 ` Edgar E. Iglesias
2017-01-09 16:05 ` [Qemu-devel] [PATCH v2 03/18] target-arm: Expose output GPIO line for VCPU maintenance interrupt Peter Maydell
2017-01-17 21:50 ` Alistair Francis
2017-01-09 16:05 ` Peter Maydell [this message]
2017-01-10 16:42 ` [Qemu-devel] [PATCH v2 04/18] hw/arm/virt: Wire VIRQ, VFIQ, maintenance irq lines from GIC to CPU Edgar E. Iglesias
2017-01-10 17:17 ` Peter Maydell
2017-01-09 16:05 ` [Qemu-devel] [PATCH v2 05/18] target-arm: Add ARMCPU fields for GIC CPU i/f config Peter Maydell
2017-01-17 22:12 ` Alistair Francis
2017-01-09 16:05 ` [Qemu-devel] [PATCH v2 06/18] hw/intc/gicv3: Add defines for ICH system register fields Peter Maydell
2017-01-09 16:05 ` [Qemu-devel] [PATCH v2 07/18] hw/intc/gicv3: Add data fields for virtualization support Peter Maydell
2017-01-17 22:13 ` Alistair Francis
2017-01-09 16:05 ` [Qemu-devel] [PATCH v2 08/18] hw/intc/arm_gicv3: Add accessors for ICH_ system registers Peter Maydell
2017-01-09 16:05 ` [Qemu-devel] [PATCH v2 09/18] hw/intc/arm_gicv3: Implement ICV_ registers which are just accessors Peter Maydell
2017-01-09 16:05 ` [Qemu-devel] [PATCH v2 10/18] hw/intc/arm_gicv3: Implement ICV_ HPPIR, DIR and RPR registers Peter Maydell
2017-01-09 16:05 ` [Qemu-devel] [PATCH v2 11/18] hw/intc/arm_gicv3: Implement ICV_ registers EOIR and IAR Peter Maydell
2017-01-09 16:05 ` [Qemu-devel] [PATCH v2 12/18] hw/intc/arm_gicv3: Implement gicv3_cpuif_virt_update() Peter Maydell
2017-01-09 16:05 ` [Qemu-devel] [PATCH v2 13/18] hw/intc/arm_gicv3: Implement EL2 traps for CPU i/f regs Peter Maydell
2017-01-09 16:05 ` [Qemu-devel] [PATCH v2 14/18] hw/arm/virt: Support using SMC for PSCI Peter Maydell
2017-01-09 16:05 ` [Qemu-devel] [PATCH v2 15/18] hw/arm/virt-acpi-build: use SMC if booting in EL2 Peter Maydell
2017-01-17 22:14 ` Alistair Francis
2017-01-09 16:05 ` [Qemu-devel] [PATCH v2 16/18] target/arm/psci.c: If EL2 implemented, start CPUs " Peter Maydell
2017-01-10 16:36 ` Edgar E. Iglesias
2017-01-17 14:47 ` Andrew Jones
2017-01-09 16:05 ` [Qemu-devel] [PATCH v2 17/18] target-arm: Enable EL2 feature bit on A53 and A57 Peter Maydell
2017-01-09 16:05 ` [Qemu-devel] [PATCH v2 18/18] hw/arm/virt: Add board property to enable EL2 Peter Maydell
2017-01-10 16:45 ` Edgar E. Iglesias
2017-01-17 14:07 ` [Qemu-devel] [Qemu-arm] [PATCH v2 00/18] arm: Add virtualization to GICv3, and enable EL2 on 64-bit CPUs Peter Maydell
2017-01-17 14:49 ` Andrew Jones
2017-01-17 22:16 ` Alistair Francis
2017-01-18 9:17 ` Edgar E. Iglesias
2017-01-19 12:59 ` Peter Maydell
2017-01-19 13:02 ` Edgar E. Iglesias
2017-01-19 13:31 ` Peter Maydell
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1483977924-14522-5-git-send-email-peter.maydell@linaro.org \
--to=peter.maydell@linaro.org \
--cc=alistair.francis@xilinx.com \
--cc=christoffer.dall@linaro.org \
--cc=drjones@redhat.com \
--cc=edgar.iglesias@xilinx.com \
--cc=patches@linaro.org \
--cc=qemu-arm@nongnu.org \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).