From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55793) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cQs9e-0001AD-54 for qemu-devel@nongnu.org; Tue, 10 Jan 2017 03:51:43 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cQs9a-0000yW-W8 for qemu-devel@nongnu.org; Tue, 10 Jan 2017 03:51:42 -0500 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:49585 helo=mx0a-001b2d01.pphosted.com) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1cQs9a-0000yF-RD for qemu-devel@nongnu.org; Tue, 10 Jan 2017 03:51:38 -0500 Received: from pps.filterd (m0098421.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.17/8.16.0.17) with SMTP id v0A8nM9x099996 for ; Tue, 10 Jan 2017 03:51:38 -0500 Received: from e28smtp01.in.ibm.com (e28smtp01.in.ibm.com [125.16.236.1]) by mx0a-001b2d01.pphosted.com with ESMTP id 27vt6q4quk-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Tue, 10 Jan 2017 03:51:38 -0500 Received: from localhost by e28smtp01.in.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Tue, 10 Jan 2017 14:21:34 +0530 From: Nikunj A Dadhania Date: Tue, 10 Jan 2017 14:20:41 +0530 In-Reply-To: <1484038243-30314-1-git-send-email-nikunj@linux.vnet.ibm.com> References: <1484038243-30314-1-git-send-email-nikunj@linux.vnet.ibm.com> Message-Id: <1484038243-30314-10-git-send-email-nikunj@linux.vnet.ibm.com> Subject: [Qemu-devel] [PATCH 09/11] target-ppc: Add xvxsigsp instruction List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, rth@twiddle.net Cc: qemu-devel@nongnu.org, bharata@linux.vnet.ibm.com, nikunj@linux.vnet.ibm.com xvxsigsp: VSX Vector Extract Significand Single Precision Signed-off-by: Nikunj A Dadhania --- target/ppc/fpu_helper.c | 20 ++++++++++++++++++++ target/ppc/helper.h | 1 + target/ppc/translate/vsx-impl.inc.c | 2 ++ target/ppc/translate/vsx-ops.inc.c | 1 + 4 files changed, 24 insertions(+) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index 77f68e9..4da83d9 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -3026,3 +3026,23 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \ VSX_XXPERM(xxperm, 0) VSX_XXPERM(xxpermr, 1) + +void helper_xvxsigsp(CPUPPCState *env, uint32_t opcode) +{ + ppc_vsr_t xt, xb; + uint32_t exp, i, fraction; + + getVSR(xB(opcode), &xb, env); + memset(&xt, 0, sizeof(xt)); + + for (i = 0; i < 4; i++) { + exp = (xb.VsrW(i) >> 23) & 0xFF; + fraction = xb.VsrW(i) & 0x7FFFFF; + if (exp != 0 && exp != 255) { + xt.VsrW(i) = fraction | 0x00800000; + } else { + xt.VsrW(i) = fraction; + } + } + putVSR(xT(opcode), &xt, env); +} diff --git a/target/ppc/helper.h b/target/ppc/helper.h index f28bf62..27607bf 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -547,6 +547,7 @@ DEF_HELPER_2(xxperm, void, env, i32) DEF_HELPER_2(xxpermr, void, env, i32) DEF_HELPER_4(xxextractuw, void, env, tl, tl, i32) DEF_HELPER_4(xxinsertw, void, env, tl, tl, i32) +DEF_HELPER_2(xvxsigsp, void, env, i32) DEF_HELPER_2(efscfsi, i32, env, i32) DEF_HELPER_2(efscfui, i32, env, i32) diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c index 7b26f75..4e57af7 100644 --- a/target/ppc/translate/vsx-impl.inc.c +++ b/target/ppc/translate/vsx-impl.inc.c @@ -1430,6 +1430,8 @@ static void gen_xvxexpdp(DisasContext *ctx) tcg_gen_andi_i64(xtl, xtl, 0x7FF); } +GEN_VSX_HELPER_2(xvxsigsp, 0x00, 0x04, 0, PPC2_ISA300) + #undef GEN_XX2FORM #undef GEN_XX3FORM #undef GEN_XX2IFORM diff --git a/target/ppc/translate/vsx-ops.inc.c b/target/ppc/translate/vsx-ops.inc.c index a3061ce..2c4f641 100644 --- a/target/ppc/translate/vsx-ops.inc.c +++ b/target/ppc/translate/vsx-ops.inc.c @@ -128,6 +128,7 @@ GEN_XX3FORM(xviexpsp, 0x00, 0x1B, PPC2_ISA300), GEN_XX3FORM(xviexpdp, 0x00, 0x1F, PPC2_ISA300), GEN_XX2FORM_EO(xvxexpdp, 0x16, 0x1D, 0x00, PPC2_ISA300), GEN_XX2FORM_EO(xvxexpsp, 0x16, 0x1D, 0x08, PPC2_ISA300), +GEN_XX2FORM_EO(xvxsigsp, 0x16, 0x1D, 0x09, PPC2_ISA300), GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX), GEN_XX2FORM(xvnabsdp, 0x12, 0x1E, PPC2_VSX), -- 2.7.4