From: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
To: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, rth@twiddle.net
Cc: qemu-devel@nongnu.org, bharata@linux.vnet.ibm.com,
nikunj@linux.vnet.ibm.com
Subject: [Qemu-devel] [PATCH 06/11] target-ppc: Add xviexpdp instruction
Date: Tue, 10 Jan 2017 14:20:38 +0530 [thread overview]
Message-ID: <1484038243-30314-7-git-send-email-nikunj@linux.vnet.ibm.com> (raw)
In-Reply-To: <1484038243-30314-1-git-send-email-nikunj@linux.vnet.ibm.com>
xviexpdp: VSX Vector Insert Exponent Dual Precision
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
target/ppc/translate/vsx-impl.inc.c | 26 ++++++++++++++++++++++++++
target/ppc/translate/vsx-ops.inc.c | 1 +
2 files changed, 27 insertions(+)
diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c
index c86f1b5..b66272e 100644
--- a/target/ppc/translate/vsx-impl.inc.c
+++ b/target/ppc/translate/vsx-impl.inc.c
@@ -1370,6 +1370,32 @@ static void gen_xviexpsp(DisasContext *ctx)
tcg_temp_free_i64(t0);
}
+static void gen_xviexpdp(DisasContext *ctx)
+{
+ TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode));
+ TCGv_i64 xtl = cpu_vsrl(xT(ctx->opcode));
+ TCGv_i64 xah = cpu_vsrh(xA(ctx->opcode));
+ TCGv_i64 xal = cpu_vsrl(xA(ctx->opcode));
+ TCGv_i64 xbh = cpu_vsrh(xB(ctx->opcode));
+ TCGv_i64 xbl = cpu_vsrl(xB(ctx->opcode));
+ TCGv_i64 t0;
+
+ if (unlikely(!ctx->vsx_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VSXU);
+ return;
+ }
+ t0 = tcg_temp_new_i64();
+ tcg_gen_andi_i64(xth, xah, 0x800FFFFFFFFFFFFF);
+ tcg_gen_andi_i64(t0, xbh, 0x7FF);
+ tcg_gen_shli_i64(t0, t0, 52);
+ tcg_gen_or_i64(xth, xth, t0);
+ tcg_gen_andi_i64(xtl, xal, 0x800FFFFFFFFFFFFF);
+ tcg_gen_andi_i64(t0, xbl, 0x7FF);
+ tcg_gen_shli_i64(t0, t0, 52);
+ tcg_gen_or_i64(xtl, xtl, t0);
+ tcg_temp_free_i64(t0);
+}
+
#undef GEN_XX2FORM
#undef GEN_XX3FORM
#undef GEN_XX2IFORM
diff --git a/target/ppc/translate/vsx-ops.inc.c b/target/ppc/translate/vsx-ops.inc.c
index 93752f0..253a5c4 100644
--- a/target/ppc/translate/vsx-ops.inc.c
+++ b/target/ppc/translate/vsx-ops.inc.c
@@ -125,6 +125,7 @@ GEN_VSX_XFORM_300(xsiexpqp, 0x4, 0x1B, 0x00000001),
#endif
GEN_XX3FORM(xviexpsp, 0x00, 0x1B, PPC2_ISA300),
+GEN_XX3FORM(xviexpdp, 0x00, 0x1F, PPC2_ISA300),
GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),
GEN_XX2FORM(xvnabsdp, 0x12, 0x1E, PPC2_VSX),
--
2.7.4
next prev parent reply other threads:[~2017-01-10 8:51 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-01-10 8:50 [Qemu-devel] [PATCH 00/11] POWER9 TCG enablements - part11 Nikunj A Dadhania
2017-01-10 8:50 ` [Qemu-devel] [PATCH 01/11] target-ppc: xscvqpdp zero VSR Nikunj A Dadhania
2017-01-10 8:50 ` [Qemu-devel] [PATCH 02/11] softfloat: Fix the default qNAN for target-ppc Nikunj A Dadhania
2017-01-10 8:50 ` [Qemu-devel] [PATCH 03/11] target-ppc: Add xsiexpdp instruction Nikunj A Dadhania
2017-01-12 2:47 ` David Gibson
2017-01-12 4:53 ` Nikunj A Dadhania
2017-01-12 5:11 ` David Gibson
2017-01-10 8:50 ` [Qemu-devel] [PATCH 04/11] target-ppc: Add xsiexpqp instruction Nikunj A Dadhania
2017-01-10 8:50 ` [Qemu-devel] [PATCH 05/11] target-ppc: Add xviexpsp instruction Nikunj A Dadhania
2017-01-10 8:50 ` Nikunj A Dadhania [this message]
2017-01-10 8:50 ` [Qemu-devel] [PATCH 07/11] target-ppc: Add xvxexpsp instruction Nikunj A Dadhania
2017-01-10 8:50 ` [Qemu-devel] [PATCH 08/11] target-ppc: Add xvxexpdp instruction Nikunj A Dadhania
2017-01-10 8:50 ` [Qemu-devel] [PATCH 09/11] target-ppc: Add xvxsigsp instruction Nikunj A Dadhania
2017-01-10 8:50 ` [Qemu-devel] [PATCH 10/11] target-ppc: Add xvxsigdp instruction Nikunj A Dadhania
2017-01-10 8:50 ` [Qemu-devel] [PATCH 11/11] target-ppc: Add xscvqps[d, w]z instructions Nikunj A Dadhania
2017-01-12 2:51 ` [Qemu-devel] [PATCH 00/11] POWER9 TCG enablements - part11 David Gibson
2017-01-12 5:38 ` David Gibson
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