* [Qemu-devel] [PATCH 1/7] target-ppc: Use ppc_vsr_t.f128 in xscmp[o, u, exp]qp
2017-01-12 16:24 [Qemu-devel] [PATCH 0/7] POWER9 TCG enablements - part12 Nikunj A Dadhania
@ 2017-01-12 16:24 ` Nikunj A Dadhania
2017-01-12 16:24 ` [Qemu-devel] [PATCH 2/7] target-ppc: Add xscvsdqp and xscvudqp instructions Nikunj A Dadhania
` (6 subsequent siblings)
7 siblings, 0 replies; 11+ messages in thread
From: Nikunj A Dadhania @ 2017-01-12 16:24 UTC (permalink / raw)
To: qemu-ppc, david, rth; +Cc: qemu-devel, bharata, nikunj
From: Bharata B Rao <bharata@linux.vnet.ibm.com>
xscmpoqp, xscmpuqp & xscmpexpqp were added before f128 field was
introduced in ppc_vsr_t. Now that we have it, use it instead of
generating the 128 bit float using two 64bit fields.
Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com>
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
target/ppc/fpu_helper.c | 20 ++++++++------------
1 file changed, 8 insertions(+), 12 deletions(-)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index ae57272..d648234 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -2452,8 +2452,8 @@ void helper_xscmpexpqp(CPUPPCState *env, uint32_t opcode)
exp_a = extract64(xa.VsrD(0), 48, 15);
exp_b = extract64(xb.VsrD(0), 48, 15);
- if (unlikely(float128_is_any_nan(make_float128(xa.VsrD(0), xa.VsrD(1))) ||
- float128_is_any_nan(make_float128(xb.VsrD(0), xb.VsrD(1))))) {
+ if (unlikely(float128_is_any_nan(xa.f128) ||
+ float128_is_any_nan(xb.f128))) {
cc = CRF_SO;
} else {
if (exp_a < exp_b) {
@@ -2528,24 +2528,20 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \
ppc_vsr_t xa, xb; \
uint32_t cc = 0; \
bool vxsnan_flag = false, vxvc_flag = false; \
- float128 a, b; \
\
helper_reset_fpstatus(env); \
getVSR(rA(opcode) + 32, &xa, env); \
getVSR(rB(opcode) + 32, &xb, env); \
\
- a = make_float128(xa.VsrD(0), xa.VsrD(1)); \
- b = make_float128(xb.VsrD(0), xb.VsrD(1)); \
- \
- if (float128_is_signaling_nan(a, &env->fp_status) || \
- float128_is_signaling_nan(b, &env->fp_status)) { \
+ if (float128_is_signaling_nan(xa.f128, &env->fp_status) || \
+ float128_is_signaling_nan(xb.f128, &env->fp_status)) { \
vxsnan_flag = true; \
cc = CRF_SO; \
if (fpscr_ve == 0 && ordered) { \
vxvc_flag = true; \
} \
- } else if (float128_is_quiet_nan(a, &env->fp_status) || \
- float128_is_quiet_nan(b, &env->fp_status)) { \
+ } else if (float128_is_quiet_nan(xa.f128, &env->fp_status) || \
+ float128_is_quiet_nan(xb.f128, &env->fp_status)) { \
cc = CRF_SO; \
if (ordered) { \
vxvc_flag = true; \
@@ -2558,9 +2554,9 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \
float_invalid_op_excp(env, POWERPC_EXCP_FP_VXVC, 0); \
} \
\
- if (float128_lt(a, b, &env->fp_status)) { \
+ if (float128_lt(xa.f128, xb.f128, &env->fp_status)) { \
cc |= CRF_LT; \
- } else if (!float128_le(a, b, &env->fp_status)) { \
+ } else if (!float128_le(xa.f128, xb.f128, &env->fp_status)) { \
cc |= CRF_GT; \
} else { \
cc |= CRF_EQ; \
--
2.7.4
^ permalink raw reply related [flat|nested] 11+ messages in thread* [Qemu-devel] [PATCH 2/7] target-ppc: Add xscvsdqp and xscvudqp instructions
2017-01-12 16:24 [Qemu-devel] [PATCH 0/7] POWER9 TCG enablements - part12 Nikunj A Dadhania
2017-01-12 16:24 ` [Qemu-devel] [PATCH 1/7] target-ppc: Use ppc_vsr_t.f128 in xscmp[o, u, exp]qp Nikunj A Dadhania
@ 2017-01-12 16:24 ` Nikunj A Dadhania
2017-01-12 16:24 ` [Qemu-devel] [PATCH 3/7] target-ppc: Add xsdivqp instruction Nikunj A Dadhania
` (5 subsequent siblings)
7 siblings, 0 replies; 11+ messages in thread
From: Nikunj A Dadhania @ 2017-01-12 16:24 UTC (permalink / raw)
To: qemu-ppc, david, rth; +Cc: qemu-devel, bharata, nikunj
From: Bharata B Rao <bharata@linux.vnet.ibm.com>
xscvsdqp: VSX Scalar Convert Signed Doubleword format to
Quad-Precision format
xscvudqp: VSX Scalar Convert Unsigned Doubleword format to
Quad-Precision format
Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com>
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
target/ppc/fpu_helper.c | 25 +++++++++++++++++++++++++
target/ppc/helper.h | 2 ++
target/ppc/translate/vsx-impl.inc.c | 2 ++
target/ppc/translate/vsx-ops.inc.c | 2 ++
4 files changed, 31 insertions(+)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index d648234..b9689b7 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -2960,6 +2960,31 @@ VSX_CVT_INT_TO_FP(xvcvuxdsp, 2, uint64, float32, VsrD(i), VsrW(2*i), 0, 0)
VSX_CVT_INT_TO_FP(xvcvsxwsp, 4, int32, float32, VsrW(i), VsrW(i), 0, 0)
VSX_CVT_INT_TO_FP(xvcvuxwsp, 4, uint32, float32, VsrW(i), VsrW(i), 0, 0)
+/* VSX_CVT_INT_TO_FP_VECTOR - VSX integer to floating point conversion
+ * op - instruction mnemonic
+ * stp - source type (int32, uint32, int64 or uint64)
+ * ttp - target type (float32 or float64)
+ * sfld - source vsr_t field
+ * tfld - target vsr_t field
+ */
+#define VSX_CVT_INT_TO_FP_VECTOR(op, stp, ttp, sfld, tfld) \
+void helper_##op(CPUPPCState *env, uint32_t opcode) \
+{ \
+ ppc_vsr_t xt, xb; \
+ \
+ getVSR(rB(opcode) + 32, &xb, env); \
+ getVSR(rD(opcode) + 32, &xt, env); \
+ \
+ xt.tfld = stp##_to_##ttp(xb.sfld, &env->fp_status); \
+ helper_compute_fprf_##ttp(env, xt.tfld); \
+ \
+ putVSR(xT(opcode) + 32, &xt, env); \
+ float_check_status(env); \
+}
+
+VSX_CVT_INT_TO_FP_VECTOR(xscvsdqp, int64, float128, VsrD(0), f128)
+VSX_CVT_INT_TO_FP_VECTOR(xscvudqp, uint64, float128, VsrD(0), f128)
+
/* For "use current rounding mode", define a value that will not be one of
* the existing rounding model enums.
*/
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 54853b8..73c60d7 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -437,6 +437,7 @@ DEF_HELPER_2(xscvqpdp, void, env, i32)
DEF_HELPER_2(xscvqpsdz, void, env, i32)
DEF_HELPER_2(xscvqpswz, void, env, i32)
DEF_HELPER_2(xscvhpdp, void, env, i32)
+DEF_HELPER_2(xscvsdqp, void, env, i32)
DEF_HELPER_2(xscvspdp, void, env, i32)
DEF_HELPER_2(xscvspdpn, i64, env, i64)
DEF_HELPER_2(xscvdpsxds, void, env, i32)
@@ -446,6 +447,7 @@ DEF_HELPER_2(xscvdpuxws, void, env, i32)
DEF_HELPER_2(xscvsxddp, void, env, i32)
DEF_HELPER_2(xscvuxdsp, void, env, i32)
DEF_HELPER_2(xscvsxdsp, void, env, i32)
+DEF_HELPER_2(xscvudqp, void, env, i32)
DEF_HELPER_2(xscvuxddp, void, env, i32)
DEF_HELPER_2(xsrdpi, void, env, i32)
DEF_HELPER_2(xsrdpic, void, env, i32)
diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c
index 3c924ba..37004a4 100644
--- a/target/ppc/translate/vsx-impl.inc.c
+++ b/target/ppc/translate/vsx-impl.inc.c
@@ -814,6 +814,7 @@ GEN_VSX_HELPER_2(xscvqpdp, 0x04, 0x1A, 0x14, PPC2_ISA300)
GEN_VSX_HELPER_2(xscvqpsdz, 0x04, 0x1A, 0x19, PPC2_ISA300)
GEN_VSX_HELPER_2(xscvqpswz, 0x04, 0x1A, 0x09, PPC2_ISA300)
GEN_VSX_HELPER_2(xscvhpdp, 0x16, 0x15, 0x10, PPC2_ISA300)
+GEN_VSX_HELPER_2(xscvsdqp, 0x04, 0x1A, 0x0A, PPC2_ISA300)
GEN_VSX_HELPER_2(xscvspdp, 0x12, 0x14, 0, PPC2_VSX)
GEN_VSX_HELPER_XT_XB_ENV(xscvspdpn, 0x16, 0x14, 0, PPC2_VSX207)
GEN_VSX_HELPER_2(xscvdpsxds, 0x10, 0x15, 0, PPC2_VSX)
@@ -821,6 +822,7 @@ GEN_VSX_HELPER_2(xscvdpsxws, 0x10, 0x05, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xscvdpuxds, 0x10, 0x14, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xscvdpuxws, 0x10, 0x04, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xscvsxddp, 0x10, 0x17, 0, PPC2_VSX)
+GEN_VSX_HELPER_2(xscvudqp, 0x04, 0x1A, 0x02, PPC2_ISA300)
GEN_VSX_HELPER_2(xscvuxddp, 0x10, 0x16, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xsrdpi, 0x12, 0x04, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xsrdpic, 0x16, 0x06, 0, PPC2_VSX)
diff --git a/target/ppc/translate/vsx-ops.inc.c b/target/ppc/translate/vsx-ops.inc.c
index 297c317..6b6b828 100644
--- a/target/ppc/translate/vsx-ops.inc.c
+++ b/target/ppc/translate/vsx-ops.inc.c
@@ -176,6 +176,7 @@ GEN_XX2FORM_EO(xscvdphp, 0x16, 0x15, 0x11, PPC2_ISA300),
GEN_XX2FORM(xscvdpsp, 0x12, 0x10, PPC2_VSX),
GEN_XX2FORM(xscvdpspn, 0x16, 0x10, PPC2_VSX207),
GEN_XX2FORM_EO(xscvhpdp, 0x16, 0x15, 0x10, PPC2_ISA300),
+GEN_VSX_XFORM_300_EO(xscvsdqp, 0x04, 0x1A, 0x0A, 0x00000001),
GEN_XX2FORM(xscvspdp, 0x12, 0x14, PPC2_VSX),
GEN_XX2FORM(xscvspdpn, 0x16, 0x14, PPC2_VSX207),
GEN_XX2FORM(xscvdpsxds, 0x10, 0x15, PPC2_VSX),
@@ -183,6 +184,7 @@ GEN_XX2FORM(xscvdpsxws, 0x10, 0x05, PPC2_VSX),
GEN_XX2FORM(xscvdpuxds, 0x10, 0x14, PPC2_VSX),
GEN_XX2FORM(xscvdpuxws, 0x10, 0x04, PPC2_VSX),
GEN_XX2FORM(xscvsxddp, 0x10, 0x17, PPC2_VSX),
+GEN_VSX_XFORM_300_EO(xscvudqp, 0x04, 0x1A, 0x02, 0x00000001),
GEN_XX2FORM(xscvuxddp, 0x10, 0x16, PPC2_VSX),
GEN_XX2FORM(xsrdpi, 0x12, 0x04, PPC2_VSX),
GEN_XX2FORM(xsrdpic, 0x16, 0x06, PPC2_VSX),
--
2.7.4
^ permalink raw reply related [flat|nested] 11+ messages in thread* [Qemu-devel] [PATCH 3/7] target-ppc: Add xsdivqp instruction
2017-01-12 16:24 [Qemu-devel] [PATCH 0/7] POWER9 TCG enablements - part12 Nikunj A Dadhania
2017-01-12 16:24 ` [Qemu-devel] [PATCH 1/7] target-ppc: Use ppc_vsr_t.f128 in xscmp[o, u, exp]qp Nikunj A Dadhania
2017-01-12 16:24 ` [Qemu-devel] [PATCH 2/7] target-ppc: Add xscvsdqp and xscvudqp instructions Nikunj A Dadhania
@ 2017-01-12 16:24 ` Nikunj A Dadhania
2017-01-12 16:24 ` [Qemu-devel] [PATCH 4/7] target-ppc: Add xsmulqp instruction Nikunj A Dadhania
` (4 subsequent siblings)
7 siblings, 0 replies; 11+ messages in thread
From: Nikunj A Dadhania @ 2017-01-12 16:24 UTC (permalink / raw)
To: qemu-ppc, david, rth; +Cc: qemu-devel, bharata, nikunj
From: Bharata B Rao <bharata@linux.vnet.ibm.com>
xsdivqp: VSX Scalar Divide Quad-Precision
Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com>
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
target/ppc/fpu_helper.c | 36 ++++++++++++++++++++++++++++++++++++
target/ppc/helper.h | 1 +
target/ppc/translate/vsx-impl.inc.c | 1 +
target/ppc/translate/vsx-ops.inc.c | 1 +
4 files changed, 39 insertions(+)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index b9689b7..545bbbc 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -1981,6 +1981,42 @@ VSX_DIV(xsdivsp, 1, float64, VsrD(0), 1, 1)
VSX_DIV(xvdivdp, 2, float64, VsrD(i), 0, 0)
VSX_DIV(xvdivsp, 4, float32, VsrW(i), 0, 0)
+void helper_xsdivqp(CPUPPCState *env, uint32_t opcode)
+{
+ ppc_vsr_t xt, xa, xb;
+
+ getVSR(rA(opcode) + 32, &xa, env);
+ getVSR(rB(opcode) + 32, &xb, env);
+ getVSR(rD(opcode) + 32, &xt, env);
+
+ if (unlikely(Rc(opcode) != 0)) {
+ /* TODO: Support xsdivqpo after round-to-odd is implemented */
+ abort();
+ }
+
+ helper_reset_fpstatus(env);
+ float_status tstat = env->fp_status;
+ set_float_exception_flags(0, &tstat);
+ xt.f128 = float128_div(xa.f128, xb.f128, &tstat);
+ env->fp_status.float_exception_flags |= tstat.float_exception_flags;
+
+ if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {
+ if (float128_is_infinity(xa.f128) && float128_is_infinity(xb.f128)) {
+ float_invalid_op_excp(env, POWERPC_EXCP_FP_VXIDI, 1);
+ } else if (float128_is_zero(xa.f128) &&
+ float128_is_zero(xb.f128)) {
+ float_invalid_op_excp(env, POWERPC_EXCP_FP_VXZDZ, 1);
+ } else if (float128_is_signaling_nan(xa.f128, &tstat) ||
+ float128_is_signaling_nan(xb.f128, &tstat)) {
+ float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
+ }
+ }
+
+ helper_compute_fprf_float128(env, xt.f128);
+ putVSR(rD(opcode) + 32, &xt, env);
+ float_check_status(env);
+}
+
/* VSX_RE - VSX floating point reciprocal estimate
* op - instruction mnemonic
* nels - number of elements (1, 2 or 4)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 73c60d7..636462f 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -404,6 +404,7 @@ DEF_HELPER_2(xsaddqp, void, env, i32)
DEF_HELPER_2(xssubdp, void, env, i32)
DEF_HELPER_2(xsmuldp, void, env, i32)
DEF_HELPER_2(xsdivdp, void, env, i32)
+DEF_HELPER_2(xsdivqp, void, env, i32)
DEF_HELPER_2(xsredp, void, env, i32)
DEF_HELPER_2(xssqrtdp, void, env, i32)
DEF_HELPER_2(xsrsqrtedp, void, env, i32)
diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c
index 37004a4..38fab01 100644
--- a/target/ppc/translate/vsx-impl.inc.c
+++ b/target/ppc/translate/vsx-impl.inc.c
@@ -781,6 +781,7 @@ GEN_VSX_HELPER_2(xsaddqp, 0x04, 0x00, 0, PPC2_ISA300)
GEN_VSX_HELPER_2(xssubdp, 0x00, 0x05, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xsmuldp, 0x00, 0x06, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xsdivdp, 0x00, 0x07, 0, PPC2_VSX)
+GEN_VSX_HELPER_2(xsdivqp, 0x04, 0x11, 0, PPC2_ISA300)
GEN_VSX_HELPER_2(xsredp, 0x14, 0x05, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xssqrtdp, 0x16, 0x04, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xsrsqrtedp, 0x14, 0x04, 0, PPC2_VSX)
diff --git a/target/ppc/translate/vsx-ops.inc.c b/target/ppc/translate/vsx-ops.inc.c
index 6b6b828..c1164c3 100644
--- a/target/ppc/translate/vsx-ops.inc.c
+++ b/target/ppc/translate/vsx-ops.inc.c
@@ -196,6 +196,7 @@ GEN_XX3FORM(xsaddsp, 0x00, 0x00, PPC2_VSX207),
GEN_XX3FORM(xssubsp, 0x00, 0x01, PPC2_VSX207),
GEN_XX3FORM(xsmulsp, 0x00, 0x02, PPC2_VSX207),
GEN_XX3FORM(xsdivsp, 0x00, 0x03, PPC2_VSX207),
+GEN_VSX_XFORM_300(xsdivqp, 0x04, 0x11, 0x0),
GEN_XX2FORM(xsresp, 0x14, 0x01, PPC2_VSX207),
GEN_XX2FORM(xsrsp, 0x12, 0x11, PPC2_VSX207),
GEN_XX2FORM(xssqrtsp, 0x16, 0x00, PPC2_VSX207),
--
2.7.4
^ permalink raw reply related [flat|nested] 11+ messages in thread* [Qemu-devel] [PATCH 4/7] target-ppc: Add xsmulqp instruction
2017-01-12 16:24 [Qemu-devel] [PATCH 0/7] POWER9 TCG enablements - part12 Nikunj A Dadhania
` (2 preceding siblings ...)
2017-01-12 16:24 ` [Qemu-devel] [PATCH 3/7] target-ppc: Add xsdivqp instruction Nikunj A Dadhania
@ 2017-01-12 16:24 ` Nikunj A Dadhania
2017-01-12 16:24 ` [Qemu-devel] [PATCH 5/7] target-ppc: Add xvcv[hpsp, sphp] instructions Nikunj A Dadhania
` (3 subsequent siblings)
7 siblings, 0 replies; 11+ messages in thread
From: Nikunj A Dadhania @ 2017-01-12 16:24 UTC (permalink / raw)
To: qemu-ppc, david, rth; +Cc: qemu-devel, bharata, nikunj
From: Bharata B Rao <bharata@linux.vnet.ibm.com>
xsmulqp: VSX Scalar Multiply Quad-Precision
Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com>
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
target/ppc/fpu_helper.c | 35 +++++++++++++++++++++++++++++++++++
target/ppc/helper.h | 1 +
target/ppc/translate/vsx-impl.inc.c | 1 +
target/ppc/translate/vsx-ops.inc.c | 1 +
4 files changed, 38 insertions(+)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index 545bbbc..e7e1024 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -1927,6 +1927,41 @@ VSX_MUL(xsmulsp, 1, float64, VsrD(0), 1, 1)
VSX_MUL(xvmuldp, 2, float64, VsrD(i), 0, 0)
VSX_MUL(xvmulsp, 4, float32, VsrW(i), 0, 0)
+void helper_xsmulqp(CPUPPCState *env, uint32_t opcode)
+{
+ ppc_vsr_t xt, xa, xb;
+
+ getVSR(rA(opcode) + 32, &xa, env);
+ getVSR(rB(opcode) + 32, &xb, env);
+ getVSR(rD(opcode) + 32, &xt, env);
+
+ if (unlikely(Rc(opcode) != 0)) {
+ /* TODO: Support xsmulpo after round-to-odd is implemented */
+ abort();
+ }
+
+ helper_reset_fpstatus(env);
+
+ float_status tstat = env->fp_status;
+ set_float_exception_flags(0, &tstat);
+ xt.f128 = float128_mul(xa.f128, xb.f128, &tstat);
+ env->fp_status.float_exception_flags |= tstat.float_exception_flags;
+
+ if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {
+ if ((float128_is_infinity(xa.f128) && float128_is_zero(xb.f128)) ||
+ (float128_is_infinity(xb.f128) && float128_is_zero(xa.f128))) {
+ float_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ, 1);
+ } else if (float128_is_signaling_nan(xa.f128, &tstat) ||
+ float128_is_signaling_nan(xb.f128, &tstat)) {
+ float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
+ }
+ }
+ helper_compute_fprf_float128(env, xt.f128);
+
+ putVSR(rD(opcode) + 32, &xt, env);
+ float_check_status(env);
+}
+
/* VSX_DIV - VSX floating point divide
* op - instruction mnemonic
* nels - number of elements (1, 2 or 4)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 636462f..9cd6534 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -403,6 +403,7 @@ DEF_HELPER_2(xsadddp, void, env, i32)
DEF_HELPER_2(xsaddqp, void, env, i32)
DEF_HELPER_2(xssubdp, void, env, i32)
DEF_HELPER_2(xsmuldp, void, env, i32)
+DEF_HELPER_2(xsmulqp, void, env, i32)
DEF_HELPER_2(xsdivdp, void, env, i32)
DEF_HELPER_2(xsdivqp, void, env, i32)
DEF_HELPER_2(xsredp, void, env, i32)
diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c
index 38fab01..d75474e 100644
--- a/target/ppc/translate/vsx-impl.inc.c
+++ b/target/ppc/translate/vsx-impl.inc.c
@@ -780,6 +780,7 @@ GEN_VSX_HELPER_2(xsadddp, 0x00, 0x04, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xsaddqp, 0x04, 0x00, 0, PPC2_ISA300)
GEN_VSX_HELPER_2(xssubdp, 0x00, 0x05, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xsmuldp, 0x00, 0x06, 0, PPC2_VSX)
+GEN_VSX_HELPER_2(xsmulqp, 0x04, 0x01, 0, PPC2_ISA300)
GEN_VSX_HELPER_2(xsdivdp, 0x00, 0x07, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xsdivqp, 0x04, 0x11, 0, PPC2_ISA300)
GEN_VSX_HELPER_2(xsredp, 0x14, 0x05, 0, PPC2_VSX)
diff --git a/target/ppc/translate/vsx-ops.inc.c b/target/ppc/translate/vsx-ops.inc.c
index c1164c3..589b505 100644
--- a/target/ppc/translate/vsx-ops.inc.c
+++ b/target/ppc/translate/vsx-ops.inc.c
@@ -146,6 +146,7 @@ GEN_XX3FORM(xsadddp, 0x00, 0x04, PPC2_VSX),
GEN_VSX_XFORM_300(xsaddqp, 0x04, 0x00, 0x0),
GEN_XX3FORM(xssubdp, 0x00, 0x05, PPC2_VSX),
GEN_XX3FORM(xsmuldp, 0x00, 0x06, PPC2_VSX),
+GEN_VSX_XFORM_300(xsmulqp, 0x04, 0x01, 0x0),
GEN_XX3FORM(xsdivdp, 0x00, 0x07, PPC2_VSX),
GEN_XX2FORM(xsredp, 0x14, 0x05, PPC2_VSX),
GEN_XX2FORM(xssqrtdp, 0x16, 0x04, PPC2_VSX),
--
2.7.4
^ permalink raw reply related [flat|nested] 11+ messages in thread* [Qemu-devel] [PATCH 5/7] target-ppc: Add xvcv[hpsp, sphp] instructions
2017-01-12 16:24 [Qemu-devel] [PATCH 0/7] POWER9 TCG enablements - part12 Nikunj A Dadhania
` (3 preceding siblings ...)
2017-01-12 16:24 ` [Qemu-devel] [PATCH 4/7] target-ppc: Add xsmulqp instruction Nikunj A Dadhania
@ 2017-01-12 16:24 ` Nikunj A Dadhania
2017-01-12 16:24 ` [Qemu-devel] [PATCH 6/7] target-ppc: Add xvtstdc[sp, dp] instructions Nikunj A Dadhania
` (2 subsequent siblings)
7 siblings, 0 replies; 11+ messages in thread
From: Nikunj A Dadhania @ 2017-01-12 16:24 UTC (permalink / raw)
To: qemu-ppc, david, rth; +Cc: qemu-devel, bharata, nikunj
xvcvhpsp: VSX Vector Convert Half Precision to Single Precision
xvcvsphp: VSX Vector Convert Single Precision to Half Precision
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
target/ppc/fpu_helper.c | 27 ++++++++++++++++++---------
target/ppc/helper.h | 2 ++
target/ppc/translate/vsx-impl.inc.c | 2 ++
target/ppc/translate/vsx-ops.inc.c | 2 ++
4 files changed, 24 insertions(+), 9 deletions(-)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index e7e1024..ffcf9ca 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -2817,33 +2817,42 @@ VSX_CVT_FP_TO_FP_VECTOR(xscvdpqp, 1, float64, float128, VsrD(0), f128, 1)
/* VSX_CVT_FP_TO_FP_HP - VSX floating point/floating point conversion
* involving one half precision value
* op - instruction mnemonic
+ * nels - number of elements (1, 2 or 4)
* stp - source type
* ttp - target type
* sfld - source vsr_t field
* tfld - target vsr_t field
+ * sfprf - set FPRF
*/
-#define VSX_CVT_FP_TO_FP_HP(op, stp, ttp, sfld, tfld) \
+#define VSX_CVT_FP_TO_FP_HP(op, nels, stp, ttp, sfld, tfld, sfprf) \
void helper_##op(CPUPPCState *env, uint32_t opcode) \
{ \
ppc_vsr_t xt, xb; \
+ int i; \
\
getVSR(xB(opcode), &xb, env); \
memset(&xt, 0, sizeof(xt)); \
\
- xt.tfld = stp##_to_##ttp(xb.sfld, 1, &env->fp_status); \
- if (unlikely(stp##_is_signaling_nan(xb.sfld, \
- &env->fp_status))) { \
- float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \
- xt.tfld = ttp##_snan_to_qnan(xt.tfld); \
+ for (i = 0; i < nels; i++) { \
+ xt.tfld = stp##_to_##ttp(xb.sfld, 1, &env->fp_status); \
+ if (unlikely(stp##_is_signaling_nan(xb.sfld, \
+ &env->fp_status))) { \
+ float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \
+ xt.tfld = ttp##_snan_to_qnan(xt.tfld); \
+ } \
+ if (sfprf) { \
+ helper_compute_fprf_##ttp(env, xt.tfld); \
+ } \
} \
- helper_compute_fprf_##ttp(env, xt.tfld); \
\
putVSR(xT(opcode), &xt, env); \
float_check_status(env); \
}
-VSX_CVT_FP_TO_FP_HP(xscvdphp, float64, float16, VsrD(0), VsrH(3))
-VSX_CVT_FP_TO_FP_HP(xscvhpdp, float16, float64, VsrH(3), VsrD(0))
+VSX_CVT_FP_TO_FP_HP(xscvdphp, 1, float64, float16, VsrD(0), VsrH(3), 1)
+VSX_CVT_FP_TO_FP_HP(xscvhpdp, 1, float16, float64, VsrH(3), VsrD(0), 1)
+VSX_CVT_FP_TO_FP_HP(xvcvsphp, 4, float32, float16, VsrW(i), VsrH(2 * i + 1), 0)
+VSX_CVT_FP_TO_FP_HP(xvcvhpsp, 4, float16, float32, VsrH(2 * i + 1), VsrW(i), 0)
/*
* xscvqpdp isn't using VSX_CVT_FP_TO_FP() because xscvqpdpo will be
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 9cd6534..14a12e0 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -536,6 +536,8 @@ DEF_HELPER_2(xvcmpgesp, void, env, i32)
DEF_HELPER_2(xvcmpgtsp, void, env, i32)
DEF_HELPER_2(xvcmpnesp, void, env, i32)
DEF_HELPER_2(xvcvspdp, void, env, i32)
+DEF_HELPER_2(xvcvsphp, void, env, i32)
+DEF_HELPER_2(xvcvhpsp, void, env, i32)
DEF_HELPER_2(xvcvspsxds, void, env, i32)
DEF_HELPER_2(xvcvspsxws, void, env, i32)
DEF_HELPER_2(xvcvspuxds, void, env, i32)
diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c
index d75474e..9bcc5af 100644
--- a/target/ppc/translate/vsx-impl.inc.c
+++ b/target/ppc/translate/vsx-impl.inc.c
@@ -913,6 +913,8 @@ GEN_VSX_HELPER_2(xvcmpgtsp, 0x0C, 0x09, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvcmpgesp, 0x0C, 0x0A, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvcmpnesp, 0x0C, 0x0B, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvcvspdp, 0x12, 0x1C, 0, PPC2_VSX)
+GEN_VSX_HELPER_2(xvcvhpsp, 0x16, 0x1D, 0x18, PPC2_ISA300)
+GEN_VSX_HELPER_2(xvcvsphp, 0x16, 0x1D, 0x19, PPC2_ISA300)
GEN_VSX_HELPER_2(xvcvspsxds, 0x10, 0x19, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvcvspsxws, 0x10, 0x09, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvcvspuxds, 0x10, 0x18, 0, PPC2_VSX)
diff --git a/target/ppc/translate/vsx-ops.inc.c b/target/ppc/translate/vsx-ops.inc.c
index 589b505..ee74312 100644
--- a/target/ppc/translate/vsx-ops.inc.c
+++ b/target/ppc/translate/vsx-ops.inc.c
@@ -291,6 +291,8 @@ GEN_XX2FORM(xvrspiz, 0x12, 0x09, PPC2_VSX),
GEN_XX2FORM_EO(xxbrh, 0x16, 0x1D, 0x07, PPC2_ISA300),
GEN_XX2FORM_EO(xxbrw, 0x16, 0x1D, 0x0F, PPC2_ISA300),
GEN_XX2FORM_EO(xxbrd, 0x16, 0x1D, 0x17, PPC2_ISA300),
+GEN_XX2FORM_EO(xvcvhpsp, 0x16, 0x1D, 0x18, PPC2_ISA300),
+GEN_XX2FORM_EO(xvcvsphp, 0x16, 0x1D, 0x19, PPC2_ISA300),
GEN_XX2FORM_EO(xxbrq, 0x16, 0x1D, 0x1F, PPC2_ISA300),
#define VSX_LOGICAL(name, opc2, opc3, fl2) \
--
2.7.4
^ permalink raw reply related [flat|nested] 11+ messages in thread* [Qemu-devel] [PATCH 6/7] target-ppc: Add xvtstdc[sp, dp] instructions
2017-01-12 16:24 [Qemu-devel] [PATCH 0/7] POWER9 TCG enablements - part12 Nikunj A Dadhania
` (4 preceding siblings ...)
2017-01-12 16:24 ` [Qemu-devel] [PATCH 5/7] target-ppc: Add xvcv[hpsp, sphp] instructions Nikunj A Dadhania
@ 2017-01-12 16:24 ` Nikunj A Dadhania
2017-01-12 17:23 ` Richard Henderson
2017-01-12 16:24 ` [Qemu-devel] [PATCH 7/7] target-ppc: Add xststdc[sp, dp, qp] instructions Nikunj A Dadhania
2017-01-13 3:01 ` [Qemu-devel] [PATCH 0/7] POWER9 TCG enablements - part12 David Gibson
7 siblings, 1 reply; 11+ messages in thread
From: Nikunj A Dadhania @ 2017-01-12 16:24 UTC (permalink / raw)
To: qemu-ppc, david, rth; +Cc: qemu-devel, bharata, nikunj
xvtstdcsp: VSX Vector Test Data Class Single-Precision
xvtstdcdp: VSX Vector Test Data Class Double-Precision
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
target/ppc/fpu_helper.c | 50 +++++++++++++++++++++++++++++++++++++
target/ppc/helper.h | 2 ++
target/ppc/internal.h | 5 ++--
target/ppc/translate/vsx-impl.inc.c | 2 ++
target/ppc/translate/vsx-ops.inc.c | 8 ++++++
5 files changed, 65 insertions(+), 2 deletions(-)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index ffcf9ca..15af7e2 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -3187,3 +3187,53 @@ void helper_xvxsigsp(CPUPPCState *env, uint32_t opcode)
}
putVSR(xT(opcode), &xt, env);
}
+
+/* VSX_TEST_DC - VSX floating point test data class
+ * op - instruction mnemonic
+ * nels - number of elements (1, 2 or 4)
+ * xbn - VSR register number
+ * tp - type (float32 or float64)
+ * fld - vsr_t field (VsrD(*) or VsrW(*))
+ * tfld - target vsr_t field (VsrD(*) or VsrW(*))
+ * fld_max - target field max
+ */
+#define VSX_TEST_DC(op, nels, xbn, tp, fld, tfld, fld_max) \
+void helper_##op(CPUPPCState *env, uint32_t opcode) \
+{ \
+ ppc_vsr_t xt, xb; \
+ uint32_t i, nan, infinity, dcmx, zero, denormal, sign; \
+ uint32_t match = 0; \
+ \
+ getVSR(xbn, &xb, env); \
+ memset(&xt, 0, sizeof(xt)); \
+ dcmx = DCMX_XV(opcode); \
+ \
+ for (i = 0; i < nels; i++) { \
+ nan = tp##_is_any_nan(xb.fld); \
+ infinity = tp##_is_infinity(xb.fld); \
+ sign = tp##_is_neg(xb.fld); \
+ zero = denormal = 0; \
+ if (tp##_is_zero_or_denormal(xb.fld)) { \
+ if (tp##_is_zero(xb.fld)) { \
+ zero = 1; \
+ } else { \
+ denormal = 1; \
+ } \
+ } \
+ \
+ if ((extract32(dcmx, 6, 1) && nan) || \
+ (extract32(dcmx, 5, 1) && infinity && !sign) || \
+ (extract32(dcmx, 4, 1) && infinity && sign) || \
+ (extract32(dcmx, 3, 1) && zero && !sign) || \
+ (extract32(dcmx, 3, 1) && zero && sign) || \
+ (extract32(dcmx, 1, 1) && denormal && !sign) || \
+ (extract32(dcmx, 0, 1) && denormal && sign)) { \
+ match = 1; \
+ } \
+ xt.tfld = match ? fld_max : 0; \
+ } \
+ putVSR(xT(opcode), &xt, env); \
+}
+
+VSX_TEST_DC(xvtstdcdp, 2, xB(opcode), float64, VsrD(i), VsrD(i), UINT64_MAX)
+VSX_TEST_DC(xvtstdcsp, 4, xB(opcode), float32, VsrW(i), VsrW(i), UINT32_MAX)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 14a12e0..2057560 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -546,6 +546,8 @@ DEF_HELPER_2(xvcvsxdsp, void, env, i32)
DEF_HELPER_2(xvcvuxdsp, void, env, i32)
DEF_HELPER_2(xvcvsxwsp, void, env, i32)
DEF_HELPER_2(xvcvuxwsp, void, env, i32)
+DEF_HELPER_2(xvtstdcsp, void, env, i32)
+DEF_HELPER_2(xvtstdcdp, void, env, i32)
DEF_HELPER_2(xvrspi, void, env, i32)
DEF_HELPER_2(xvrspic, void, env, i32)
DEF_HELPER_2(xvrspim, void, env, i32)
diff --git a/target/ppc/internal.h b/target/ppc/internal.h
index c22d74e..4c3811a 100644
--- a/target/ppc/internal.h
+++ b/target/ppc/internal.h
@@ -68,7 +68,7 @@ static inline uint32_t name(uint32_t opcode) \
((opcode >> (shift2)) & ((1 << (nb2)) - 1)); \
}
-#define EXTRACT_HELPER_DXFORM(name, \
+#define EXTRACT_HELPER_SPLIT_3(name, \
d0_bits, shift_op_d0, shift_d0, \
d1_bits, shift_op_d1, shift_d1, \
d2_bits, shift_op_d2, shift_d2) \
@@ -156,7 +156,7 @@ EXTRACT_HELPER(FPFLM, 17, 8);
EXTRACT_HELPER(FPW, 16, 1);
/* addpcis */
-EXTRACT_HELPER_DXFORM(DX, 10, 6, 6, 5, 16, 1, 1, 0, 0)
+EXTRACT_HELPER_SPLIT_3(DX, 10, 6, 6, 5, 16, 1, 1, 0, 0)
#if defined(TARGET_PPC64)
/* darn */
EXTRACT_HELPER(L, 16, 2);
@@ -198,6 +198,7 @@ EXTRACT_HELPER(UIM, 16, 2);
EXTRACT_HELPER(SHW, 8, 2);
EXTRACT_HELPER(SP, 19, 2);
EXTRACT_HELPER(IMM8, 11, 8);
+EXTRACT_HELPER_SPLIT_3(DCMX_XV, 5, 16, 0, 1, 2, 5, 1, 6, 6);
typedef union _ppc_vsr_t {
uint8_t u8[16];
diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c
index 9bcc5af..adb6fc7 100644
--- a/target/ppc/translate/vsx-impl.inc.c
+++ b/target/ppc/translate/vsx-impl.inc.c
@@ -928,6 +928,8 @@ GEN_VSX_HELPER_2(xvrspic, 0x16, 0x0A, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvrspim, 0x12, 0x0B, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvrspip, 0x12, 0x0A, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvrspiz, 0x12, 0x09, 0, PPC2_VSX)
+GEN_VSX_HELPER_2(xvtstdcsp, 0x14, 0x1A, 0, PPC2_VSX)
+GEN_VSX_HELPER_2(xvtstdcdp, 0x14, 0x1E, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xxperm, 0x08, 0x03, 0, PPC2_ISA300)
GEN_VSX_HELPER_2(xxpermr, 0x08, 0x07, 0, PPC2_ISA300)
diff --git a/target/ppc/translate/vsx-ops.inc.c b/target/ppc/translate/vsx-ops.inc.c
index ee74312..6dd5d72 100644
--- a/target/ppc/translate/vsx-ops.inc.c
+++ b/target/ppc/translate/vsx-ops.inc.c
@@ -133,6 +133,14 @@ GEN_XX2FORM_EO(xvxsigdp, 0x16, 0x1D, 0x01, PPC2_ISA300),
GEN_XX2FORM_EO(xvxexpsp, 0x16, 0x1D, 0x08, PPC2_ISA300),
GEN_XX2FORM_EO(xvxsigsp, 0x16, 0x1D, 0x09, PPC2_ISA300),
+/* DCMX = bit[25] << 6 | bit[29] << 5 | bit[11:15] */
+#define GEN_XX2FORM_DCMX(name, opc2, opc3, fl2) \
+GEN_XX3FORM(name, opc2, opc3 | 0, fl2), \
+GEN_XX3FORM(name, opc2, opc3 | 1, fl2)
+
+GEN_XX2FORM_DCMX(xvtstdcdp, 0x14, 0x1E, PPC2_ISA300),
+GEN_XX2FORM_DCMX(xvtstdcsp, 0x14, 0x1A, PPC2_ISA300),
+
GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),
GEN_XX2FORM(xvnabsdp, 0x12, 0x1E, PPC2_VSX),
GEN_XX2FORM(xvnegdp, 0x12, 0x1F, PPC2_VSX),
--
2.7.4
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [Qemu-devel] [PATCH 6/7] target-ppc: Add xvtstdc[sp, dp] instructions
2017-01-12 16:24 ` [Qemu-devel] [PATCH 6/7] target-ppc: Add xvtstdc[sp, dp] instructions Nikunj A Dadhania
@ 2017-01-12 17:23 ` Richard Henderson
2017-01-13 3:32 ` Nikunj A Dadhania
0 siblings, 1 reply; 11+ messages in thread
From: Richard Henderson @ 2017-01-12 17:23 UTC (permalink / raw)
To: Nikunj A Dadhania, qemu-ppc, david; +Cc: qemu-devel, bharata
On 01/12/2017 08:24 AM, Nikunj A Dadhania wrote:
> + nan = tp##_is_any_nan(xb.fld); \
> + infinity = tp##_is_infinity(xb.fld); \
> + sign = tp##_is_neg(xb.fld); \
> + zero = denormal = 0; \
> + if (tp##_is_zero_or_denormal(xb.fld)) { \
> + if (tp##_is_zero(xb.fld)) { \
> + zero = 1; \
> + } else { \
> + denormal = 1; \
> + } \
> + } \
> + \
> + if ((extract32(dcmx, 6, 1) && nan) || \
> + (extract32(dcmx, 5, 1) && infinity && !sign) || \
> + (extract32(dcmx, 4, 1) && infinity && sign) || \
> + (extract32(dcmx, 3, 1) && zero && !sign) || \
> + (extract32(dcmx, 3, 1) && zero && sign) || \
> + (extract32(dcmx, 1, 1) && denormal && !sign) || \
> + (extract32(dcmx, 0, 1) && denormal && sign)) { \
> + match = 1; \
> + } \
I'll note that all of these are mutually exclusive, therefore you're doing much
more work than required.
sign = tp##_is_neg(x));
if (tp##is_any_nan(x)) {
match = extract32(dcmx, 6, 1);
} else if (tp##_is_infinity(x)) {
match = extract32(dcmx, 4 + !sign, 1);
} else if (tp##_is_zero(x)) {
match = extract32(dcmx, 2 + !sign, 1);
} else if (tp##_is_zero_or_denormal(x)) {
match = extract32(dcmx, 0 + !sign, 1);
}
(Also, an apparent typo for your zero && sign case.)
r~
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [Qemu-devel] [PATCH 6/7] target-ppc: Add xvtstdc[sp, dp] instructions
2017-01-12 17:23 ` Richard Henderson
@ 2017-01-13 3:32 ` Nikunj A Dadhania
0 siblings, 0 replies; 11+ messages in thread
From: Nikunj A Dadhania @ 2017-01-13 3:32 UTC (permalink / raw)
To: Richard Henderson, qemu-ppc, david; +Cc: qemu-devel, bharata
Richard Henderson <rth@twiddle.net> writes:
> On 01/12/2017 08:24 AM, Nikunj A Dadhania wrote:
>> + nan = tp##_is_any_nan(xb.fld); \
>> + infinity = tp##_is_infinity(xb.fld); \
>> + sign = tp##_is_neg(xb.fld); \
>> + zero = denormal = 0; \
>> + if (tp##_is_zero_or_denormal(xb.fld)) { \
>> + if (tp##_is_zero(xb.fld)) { \
>> + zero = 1; \
>> + } else { \
>> + denormal = 1; \
>> + } \
>> + } \
>> + \
>> + if ((extract32(dcmx, 6, 1) && nan) || \
>> + (extract32(dcmx, 5, 1) && infinity && !sign) || \
>> + (extract32(dcmx, 4, 1) && infinity && sign) || \
>> + (extract32(dcmx, 3, 1) && zero && !sign) || \
>> + (extract32(dcmx, 3, 1) && zero && sign) || \
>> + (extract32(dcmx, 1, 1) && denormal && !sign) || \
>> + (extract32(dcmx, 0, 1) && denormal && sign)) { \
>> + match = 1; \
>> + } \
>
> I'll note that all of these are mutually exclusive, therefore you're doing much
> more work than required.
>
> sign = tp##_is_neg(x));
> if (tp##is_any_nan(x)) {
> match = extract32(dcmx, 6, 1);
> } else if (tp##_is_infinity(x)) {
> match = extract32(dcmx, 4 + !sign, 1);
> } else if (tp##_is_zero(x)) {
> match = extract32(dcmx, 2 + !sign, 1);
> } else if (tp##_is_zero_or_denormal(x)) {
> match = extract32(dcmx, 0 + !sign, 1);
> }
Right, that is pretty concise. Will send updated series changing patch 6
and 7.
> (Also, an apparent typo for your zero && sign case.)
Yes, was by mistake.
Regards
Nikunj
^ permalink raw reply [flat|nested] 11+ messages in thread
* [Qemu-devel] [PATCH 7/7] target-ppc: Add xststdc[sp, dp, qp] instructions
2017-01-12 16:24 [Qemu-devel] [PATCH 0/7] POWER9 TCG enablements - part12 Nikunj A Dadhania
` (5 preceding siblings ...)
2017-01-12 16:24 ` [Qemu-devel] [PATCH 6/7] target-ppc: Add xvtstdc[sp, dp] instructions Nikunj A Dadhania
@ 2017-01-12 16:24 ` Nikunj A Dadhania
2017-01-13 3:01 ` [Qemu-devel] [PATCH 0/7] POWER9 TCG enablements - part12 David Gibson
7 siblings, 0 replies; 11+ messages in thread
From: Nikunj A Dadhania @ 2017-01-12 16:24 UTC (permalink / raw)
To: qemu-ppc, david, rth; +Cc: qemu-devel, bharata, nikunj
xststdcsp: VSX Scalar Test Data Class Single-Precision
xststdcdp: VSX Scalar Test Data Class Double-Precision
xststdcqp: VSX Scalar Test Data Class Quad-Precision
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
target/ppc/fpu_helper.c | 76 +++++++++++++++++++++++++++++++++----
target/ppc/helper.h | 3 ++
target/ppc/internal.h | 1 +
target/ppc/translate/vsx-impl.inc.c | 3 ++
target/ppc/translate/vsx-ops.inc.c | 4 ++
5 files changed, 79 insertions(+), 8 deletions(-)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index 15af7e2..d24a5ba 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -3196,17 +3196,22 @@ void helper_xvxsigsp(CPUPPCState *env, uint32_t opcode)
* fld - vsr_t field (VsrD(*) or VsrW(*))
* tfld - target vsr_t field (VsrD(*) or VsrW(*))
* fld_max - target field max
+ * scrf - set result in CR and FPCC
*/
-#define VSX_TEST_DC(op, nels, xbn, tp, fld, tfld, fld_max) \
+#define VSX_TEST_DC(op, nels, xbn, tp, fld, tfld, fld_max, scrf) \
void helper_##op(CPUPPCState *env, uint32_t opcode) \
{ \
ppc_vsr_t xt, xb; \
uint32_t i, nan, infinity, dcmx, zero, denormal, sign; \
- uint32_t match = 0; \
+ uint32_t cc, match = 0; \
\
getVSR(xbn, &xb, env); \
- memset(&xt, 0, sizeof(xt)); \
- dcmx = DCMX_XV(opcode); \
+ if (!scrf) { \
+ memset(&xt, 0, sizeof(xt)); \
+ dcmx = DCMX_XV(opcode); \
+ } else { \
+ dcmx = DCMX(opcode); \
+ } \
\
for (i = 0; i < nels; i++) { \
nan = tp##_is_any_nan(xb.fld); \
@@ -3230,10 +3235,65 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \
(extract32(dcmx, 0, 1) && denormal && sign)) { \
match = 1; \
} \
- xt.tfld = match ? fld_max : 0; \
+ \
+ if (scrf) { \
+ cc = sign << CRF_LT_BIT | match << CRF_EQ_BIT; \
+ env->fpscr &= ~(0x0F << FPSCR_FPRF); \
+ env->fpscr |= cc << FPSCR_FPRF; \
+ env->crf[BF(opcode)] = cc; \
+ } else { \
+ xt.tfld = match ? fld_max : 0; \
+ } \
+ } \
+ if (!scrf) { \
+ putVSR(xT(opcode), &xt, env); \
} \
- putVSR(xT(opcode), &xt, env); \
}
-VSX_TEST_DC(xvtstdcdp, 2, xB(opcode), float64, VsrD(i), VsrD(i), UINT64_MAX)
-VSX_TEST_DC(xvtstdcsp, 4, xB(opcode), float32, VsrW(i), VsrW(i), UINT32_MAX)
+VSX_TEST_DC(xvtstdcdp, 2, xB(opcode), float64, VsrD(i), VsrD(i), UINT64_MAX, 0)
+VSX_TEST_DC(xvtstdcsp, 4, xB(opcode), float32, VsrW(i), VsrW(i), UINT32_MAX, 0)
+VSX_TEST_DC(xststdcdp, 1, xB(opcode), float64, VsrD(0), VsrD(0), 0, 1)
+VSX_TEST_DC(xststdcqp, 1, (rB(opcode) + 32), float128, f128, VsrD(0), 0, 1)
+
+void helper_xststdcsp(CPUPPCState *env, uint32_t opcode)
+{
+ ppc_vsr_t xb;
+ uint32_t nan, infinity, dcmx, zero, denormal, sign, exp;
+ uint32_t cc, match = 0, not_sp = 0;
+
+ getVSR(xB(opcode), &xb, env);
+ dcmx = DCMX(opcode);
+ exp = (xb.VsrD(0) >> 52) & 0x7FF;
+ nan = float64_is_any_nan(xb.VsrD(0));
+ infinity = float64_is_infinity(xb.VsrD(0));
+ sign = float64_is_neg(xb.VsrD(0));
+ zero = denormal = 0;
+ if (float64_is_zero_or_denormal(xb.VsrD(0)) ||
+ (exp > 0 && exp < 0x381)) {
+ if (float64_is_zero(xb.VsrD(0))) {
+ zero = 1;
+ } else {
+ denormal = 1;
+ }
+ }
+
+ if ((extract32(dcmx, 6, 1) && nan) ||
+ (extract32(dcmx, 5, 1) && infinity && !sign) ||
+ (extract32(dcmx, 4, 1) && infinity && sign) ||
+ (extract32(dcmx, 3, 1) && zero && !sign) ||
+ (extract32(dcmx, 2, 1) && zero && sign) ||
+ (extract32(dcmx, 1, 1) && denormal && !sign) ||
+ (extract32(dcmx, 0, 1) && denormal && sign)) {
+ match = 1;
+ }
+
+ not_sp = !float64_eq(xb.VsrD(0),
+ float32_to_float64(
+ float64_to_float32(xb.VsrD(0), &env->fp_status),
+ &env->fp_status), &env->fp_status);
+
+ cc = sign << CRF_LT_BIT | match << CRF_EQ_BIT | not_sp << CRF_SO_BIT;
+ env->fpscr &= ~(0x0F << FPSCR_FPRF);
+ env->fpscr |= cc << FPSCR_FPRF;
+ env->crf[BF(opcode)] = cc;
+}
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 2057560..8331913 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -451,6 +451,9 @@ DEF_HELPER_2(xscvuxdsp, void, env, i32)
DEF_HELPER_2(xscvsxdsp, void, env, i32)
DEF_HELPER_2(xscvudqp, void, env, i32)
DEF_HELPER_2(xscvuxddp, void, env, i32)
+DEF_HELPER_2(xststdcsp, void, env, i32)
+DEF_HELPER_2(xststdcdp, void, env, i32)
+DEF_HELPER_2(xststdcqp, void, env, i32)
DEF_HELPER_2(xsrdpi, void, env, i32)
DEF_HELPER_2(xsrdpic, void, env, i32)
DEF_HELPER_2(xsrdpim, void, env, i32)
diff --git a/target/ppc/internal.h b/target/ppc/internal.h
index 4c3811a..5a2fd68 100644
--- a/target/ppc/internal.h
+++ b/target/ppc/internal.h
@@ -198,6 +198,7 @@ EXTRACT_HELPER(UIM, 16, 2);
EXTRACT_HELPER(SHW, 8, 2);
EXTRACT_HELPER(SP, 19, 2);
EXTRACT_HELPER(IMM8, 11, 8);
+EXTRACT_HELPER(DCMX, 16, 7);
EXTRACT_HELPER_SPLIT_3(DCMX_XV, 5, 16, 0, 1, 2, 5, 1, 6, 6);
typedef union _ppc_vsr_t {
diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c
index adb6fc7..a44c003 100644
--- a/target/ppc/translate/vsx-impl.inc.c
+++ b/target/ppc/translate/vsx-impl.inc.c
@@ -850,6 +850,9 @@ GEN_VSX_HELPER_2(xsnmsubasp, 0x04, 0x12, 0, PPC2_VSX207)
GEN_VSX_HELPER_2(xsnmsubmsp, 0x04, 0x13, 0, PPC2_VSX207)
GEN_VSX_HELPER_2(xscvsxdsp, 0x10, 0x13, 0, PPC2_VSX207)
GEN_VSX_HELPER_2(xscvuxdsp, 0x10, 0x12, 0, PPC2_VSX207)
+GEN_VSX_HELPER_2(xststdcsp, 0x14, 0x12, 0, PPC2_ISA300)
+GEN_VSX_HELPER_2(xststdcdp, 0x14, 0x16, 0, PPC2_ISA300)
+GEN_VSX_HELPER_2(xststdcqp, 0x04, 0x16, 0, PPC2_ISA300)
GEN_VSX_HELPER_2(xvadddp, 0x00, 0x0C, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvsubdp, 0x00, 0x0D, 0, PPC2_VSX)
diff --git a/target/ppc/translate/vsx-ops.inc.c b/target/ppc/translate/vsx-ops.inc.c
index 6dd5d72..7dc9f6f 100644
--- a/target/ppc/translate/vsx-ops.inc.c
+++ b/target/ppc/translate/vsx-ops.inc.c
@@ -126,6 +126,10 @@ GEN_HANDLER_E(xsiexpdp, 0x3C, 0x16, 0x1C, 0, PPC_NONE, PPC2_ISA300),
GEN_VSX_XFORM_300(xsiexpqp, 0x4, 0x1B, 0x00000001),
#endif
+GEN_XX2FORM(xststdcdp, 0x14, 0x16, PPC2_ISA300),
+GEN_XX2FORM(xststdcsp, 0x14, 0x12, PPC2_ISA300),
+GEN_VSX_XFORM_300(xststdcqp, 0x04, 0x16, 0x00000001),
+
GEN_XX3FORM(xviexpsp, 0x00, 0x1B, PPC2_ISA300),
GEN_XX3FORM(xviexpdp, 0x00, 0x1F, PPC2_ISA300),
GEN_XX2FORM_EO(xvxexpdp, 0x16, 0x1D, 0x00, PPC2_ISA300),
--
2.7.4
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [Qemu-devel] [PATCH 0/7] POWER9 TCG enablements - part12
2017-01-12 16:24 [Qemu-devel] [PATCH 0/7] POWER9 TCG enablements - part12 Nikunj A Dadhania
` (6 preceding siblings ...)
2017-01-12 16:24 ` [Qemu-devel] [PATCH 7/7] target-ppc: Add xststdc[sp, dp, qp] instructions Nikunj A Dadhania
@ 2017-01-13 3:01 ` David Gibson
7 siblings, 0 replies; 11+ messages in thread
From: David Gibson @ 2017-01-13 3:01 UTC (permalink / raw)
To: Nikunj A Dadhania; +Cc: qemu-ppc, rth, qemu-devel, bharata
[-- Attachment #1: Type: text/plain, Size: 1330 bytes --]
On Thu, Jan 12, 2017 at 09:54:04PM +0530, Nikunj A Dadhania wrote:
> This series contains 11 new instructions for POWER9 ISA3.0
> VSX Scalar Test Data Class
> VSX Vector Test Data Class
> VSX Vector Convert HP/SP
> VSX Scalar Multiply/Divide
> VSX Scalar Convert Unsigned/Signed Doubleword
>
> Bharata B Rao (4):
> target-ppc: Use ppc_vsr_t.f128 in xscmp[o,u,exp]qp
> target-ppc: Add xscvsdqp and xscvudqp instructions
> target-ppc: Add xsdivqp instruction
> target-ppc: Add xsmulqp instruction
>
> Nikunj A Dadhania (3):
> target-ppc: Add xvcv[hpsp, sphp] instructions
> target-ppc: Add xvtstdc[sp,dp] instructions
> target-ppc: Add xststdc[sp, dp, qp] instructions
>
> target/ppc/fpu_helper.c | 253 +++++++++++++++++++++++++++++++++---
> target/ppc/helper.h | 11 ++
> target/ppc/internal.h | 6 +-
> target/ppc/translate/vsx-impl.inc.c | 11 ++
> target/ppc/translate/vsx-ops.inc.c | 18 +++
> 5 files changed, 276 insertions(+), 23 deletions(-)
I've merged 1..5. 6 & 7 I've left, pending a reply to rth's comment.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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^ permalink raw reply [flat|nested] 11+ messages in thread