From: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
To: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, rth@twiddle.net
Cc: qemu-devel@nongnu.org, bharata@linux.vnet.ibm.com,
nikunj@linux.vnet.ibm.com
Subject: [Qemu-devel] [PATCH 6/7] target-ppc: Add xvtstdc[sp, dp] instructions
Date: Thu, 12 Jan 2017 21:54:10 +0530 [thread overview]
Message-ID: <1484238251-8096-7-git-send-email-nikunj@linux.vnet.ibm.com> (raw)
In-Reply-To: <1484238251-8096-1-git-send-email-nikunj@linux.vnet.ibm.com>
xvtstdcsp: VSX Vector Test Data Class Single-Precision
xvtstdcdp: VSX Vector Test Data Class Double-Precision
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
target/ppc/fpu_helper.c | 50 +++++++++++++++++++++++++++++++++++++
target/ppc/helper.h | 2 ++
target/ppc/internal.h | 5 ++--
target/ppc/translate/vsx-impl.inc.c | 2 ++
target/ppc/translate/vsx-ops.inc.c | 8 ++++++
5 files changed, 65 insertions(+), 2 deletions(-)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index ffcf9ca..15af7e2 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -3187,3 +3187,53 @@ void helper_xvxsigsp(CPUPPCState *env, uint32_t opcode)
}
putVSR(xT(opcode), &xt, env);
}
+
+/* VSX_TEST_DC - VSX floating point test data class
+ * op - instruction mnemonic
+ * nels - number of elements (1, 2 or 4)
+ * xbn - VSR register number
+ * tp - type (float32 or float64)
+ * fld - vsr_t field (VsrD(*) or VsrW(*))
+ * tfld - target vsr_t field (VsrD(*) or VsrW(*))
+ * fld_max - target field max
+ */
+#define VSX_TEST_DC(op, nels, xbn, tp, fld, tfld, fld_max) \
+void helper_##op(CPUPPCState *env, uint32_t opcode) \
+{ \
+ ppc_vsr_t xt, xb; \
+ uint32_t i, nan, infinity, dcmx, zero, denormal, sign; \
+ uint32_t match = 0; \
+ \
+ getVSR(xbn, &xb, env); \
+ memset(&xt, 0, sizeof(xt)); \
+ dcmx = DCMX_XV(opcode); \
+ \
+ for (i = 0; i < nels; i++) { \
+ nan = tp##_is_any_nan(xb.fld); \
+ infinity = tp##_is_infinity(xb.fld); \
+ sign = tp##_is_neg(xb.fld); \
+ zero = denormal = 0; \
+ if (tp##_is_zero_or_denormal(xb.fld)) { \
+ if (tp##_is_zero(xb.fld)) { \
+ zero = 1; \
+ } else { \
+ denormal = 1; \
+ } \
+ } \
+ \
+ if ((extract32(dcmx, 6, 1) && nan) || \
+ (extract32(dcmx, 5, 1) && infinity && !sign) || \
+ (extract32(dcmx, 4, 1) && infinity && sign) || \
+ (extract32(dcmx, 3, 1) && zero && !sign) || \
+ (extract32(dcmx, 3, 1) && zero && sign) || \
+ (extract32(dcmx, 1, 1) && denormal && !sign) || \
+ (extract32(dcmx, 0, 1) && denormal && sign)) { \
+ match = 1; \
+ } \
+ xt.tfld = match ? fld_max : 0; \
+ } \
+ putVSR(xT(opcode), &xt, env); \
+}
+
+VSX_TEST_DC(xvtstdcdp, 2, xB(opcode), float64, VsrD(i), VsrD(i), UINT64_MAX)
+VSX_TEST_DC(xvtstdcsp, 4, xB(opcode), float32, VsrW(i), VsrW(i), UINT32_MAX)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 14a12e0..2057560 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -546,6 +546,8 @@ DEF_HELPER_2(xvcvsxdsp, void, env, i32)
DEF_HELPER_2(xvcvuxdsp, void, env, i32)
DEF_HELPER_2(xvcvsxwsp, void, env, i32)
DEF_HELPER_2(xvcvuxwsp, void, env, i32)
+DEF_HELPER_2(xvtstdcsp, void, env, i32)
+DEF_HELPER_2(xvtstdcdp, void, env, i32)
DEF_HELPER_2(xvrspi, void, env, i32)
DEF_HELPER_2(xvrspic, void, env, i32)
DEF_HELPER_2(xvrspim, void, env, i32)
diff --git a/target/ppc/internal.h b/target/ppc/internal.h
index c22d74e..4c3811a 100644
--- a/target/ppc/internal.h
+++ b/target/ppc/internal.h
@@ -68,7 +68,7 @@ static inline uint32_t name(uint32_t opcode) \
((opcode >> (shift2)) & ((1 << (nb2)) - 1)); \
}
-#define EXTRACT_HELPER_DXFORM(name, \
+#define EXTRACT_HELPER_SPLIT_3(name, \
d0_bits, shift_op_d0, shift_d0, \
d1_bits, shift_op_d1, shift_d1, \
d2_bits, shift_op_d2, shift_d2) \
@@ -156,7 +156,7 @@ EXTRACT_HELPER(FPFLM, 17, 8);
EXTRACT_HELPER(FPW, 16, 1);
/* addpcis */
-EXTRACT_HELPER_DXFORM(DX, 10, 6, 6, 5, 16, 1, 1, 0, 0)
+EXTRACT_HELPER_SPLIT_3(DX, 10, 6, 6, 5, 16, 1, 1, 0, 0)
#if defined(TARGET_PPC64)
/* darn */
EXTRACT_HELPER(L, 16, 2);
@@ -198,6 +198,7 @@ EXTRACT_HELPER(UIM, 16, 2);
EXTRACT_HELPER(SHW, 8, 2);
EXTRACT_HELPER(SP, 19, 2);
EXTRACT_HELPER(IMM8, 11, 8);
+EXTRACT_HELPER_SPLIT_3(DCMX_XV, 5, 16, 0, 1, 2, 5, 1, 6, 6);
typedef union _ppc_vsr_t {
uint8_t u8[16];
diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c
index 9bcc5af..adb6fc7 100644
--- a/target/ppc/translate/vsx-impl.inc.c
+++ b/target/ppc/translate/vsx-impl.inc.c
@@ -928,6 +928,8 @@ GEN_VSX_HELPER_2(xvrspic, 0x16, 0x0A, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvrspim, 0x12, 0x0B, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvrspip, 0x12, 0x0A, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvrspiz, 0x12, 0x09, 0, PPC2_VSX)
+GEN_VSX_HELPER_2(xvtstdcsp, 0x14, 0x1A, 0, PPC2_VSX)
+GEN_VSX_HELPER_2(xvtstdcdp, 0x14, 0x1E, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xxperm, 0x08, 0x03, 0, PPC2_ISA300)
GEN_VSX_HELPER_2(xxpermr, 0x08, 0x07, 0, PPC2_ISA300)
diff --git a/target/ppc/translate/vsx-ops.inc.c b/target/ppc/translate/vsx-ops.inc.c
index ee74312..6dd5d72 100644
--- a/target/ppc/translate/vsx-ops.inc.c
+++ b/target/ppc/translate/vsx-ops.inc.c
@@ -133,6 +133,14 @@ GEN_XX2FORM_EO(xvxsigdp, 0x16, 0x1D, 0x01, PPC2_ISA300),
GEN_XX2FORM_EO(xvxexpsp, 0x16, 0x1D, 0x08, PPC2_ISA300),
GEN_XX2FORM_EO(xvxsigsp, 0x16, 0x1D, 0x09, PPC2_ISA300),
+/* DCMX = bit[25] << 6 | bit[29] << 5 | bit[11:15] */
+#define GEN_XX2FORM_DCMX(name, opc2, opc3, fl2) \
+GEN_XX3FORM(name, opc2, opc3 | 0, fl2), \
+GEN_XX3FORM(name, opc2, opc3 | 1, fl2)
+
+GEN_XX2FORM_DCMX(xvtstdcdp, 0x14, 0x1E, PPC2_ISA300),
+GEN_XX2FORM_DCMX(xvtstdcsp, 0x14, 0x1A, PPC2_ISA300),
+
GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),
GEN_XX2FORM(xvnabsdp, 0x12, 0x1E, PPC2_VSX),
GEN_XX2FORM(xvnegdp, 0x12, 0x1F, PPC2_VSX),
--
2.7.4
next prev parent reply other threads:[~2017-01-12 16:25 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-01-12 16:24 [Qemu-devel] [PATCH 0/7] POWER9 TCG enablements - part12 Nikunj A Dadhania
2017-01-12 16:24 ` [Qemu-devel] [PATCH 1/7] target-ppc: Use ppc_vsr_t.f128 in xscmp[o, u, exp]qp Nikunj A Dadhania
2017-01-12 16:24 ` [Qemu-devel] [PATCH 2/7] target-ppc: Add xscvsdqp and xscvudqp instructions Nikunj A Dadhania
2017-01-12 16:24 ` [Qemu-devel] [PATCH 3/7] target-ppc: Add xsdivqp instruction Nikunj A Dadhania
2017-01-12 16:24 ` [Qemu-devel] [PATCH 4/7] target-ppc: Add xsmulqp instruction Nikunj A Dadhania
2017-01-12 16:24 ` [Qemu-devel] [PATCH 5/7] target-ppc: Add xvcv[hpsp, sphp] instructions Nikunj A Dadhania
2017-01-12 16:24 ` Nikunj A Dadhania [this message]
2017-01-12 17:23 ` [Qemu-devel] [PATCH 6/7] target-ppc: Add xvtstdc[sp, dp] instructions Richard Henderson
2017-01-13 3:32 ` Nikunj A Dadhania
2017-01-12 16:24 ` [Qemu-devel] [PATCH 7/7] target-ppc: Add xststdc[sp, dp, qp] instructions Nikunj A Dadhania
2017-01-13 3:01 ` [Qemu-devel] [PATCH 0/7] POWER9 TCG enablements - part12 David Gibson
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