[Qemu-devel] [PATCH v6 0/2] POWER9 TCG enablements - BCD functions

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* [Qemu-devel] [PATCH v6 0/2] POWER9 TCG enablements - BCD functions - final part
@ 2017-01-12 20:08 Jose Ricardo Ziviani
  2017-01-12 20:08 ` [Qemu-devel] [PATCH v6 1/2] ppc: Implement bcdtrunc. instruction Jose Ricardo Ziviani
                   ` (2 more replies)
  0 siblings, 3 replies; 4+ messages in thread
From: Jose Ricardo Ziviani @ 2017-01-12 20:08 UTC (permalink / raw)
  To: qemu-ppc; +Cc: qemu-devel, david, nikunj

v6:
 - improves bcdtrunc/bcdutrunc overflow comparison
 - removes bcds/bcdus/bcdsr applied patches

v5:
 - removes 'unlikely' gcc branch pred. hints from not unlikely places
 - adds comments in host-utils functions
 - adds more test cases for shift functions
 - handles "shift backwards" with signed shifts
 - rebases branch

v4:
 - improves functions to behave exactly like the target

v3:
 - moves shift functions to host-utils.c and added config_int128 guard
 - changes Makefile to always compile host-utils.c
 - redesigns bcd[u]trunc to use bitwise operations
 - removes "target-ppc: Implement bcd_is_valid function" (merged)

v2:
 - bcd[s,sr,us] uses 1 byte for shifting instead of 4 bytes
 - left/right functions in host-utils are out of CONFIG_INT128
 - fixes overflowing issue in left shift and added a testcase

This serie contains 5 new instructions for POWER9 ISA3.0, left/right shifts for 
unsigned quadwords and a small improvement to check whether a bcd value is 
valid or not.

bcdtrunc.: Decimal signed trucate
bcdutrunc.: Decimal unsigned truncate

Jose Ricardo Ziviani (2):
  ppc: Implement bcdtrunc. instruction
  ppc: Implement bcdutrunc. instruction

 target/ppc/helper.h                 |  2 +
 target/ppc/int_helper.c             | 88 +++++++++++++++++++++++++++++++++++++
 target/ppc/translate/vmx-impl.inc.c |  9 ++++
 target/ppc/translate/vmx-ops.inc.c  |  6 +--
 4 files changed, 102 insertions(+), 3 deletions(-)

-- 
2.7.4

^ permalink raw reply	[flat|nested] 4+ messages in thread

* [Qemu-devel] [PATCH v6 1/2] ppc: Implement bcdtrunc. instruction
  2017-01-12 20:08 [Qemu-devel] [PATCH v6 0/2] POWER9 TCG enablements - BCD functions - final part Jose Ricardo Ziviani
@ 2017-01-12 20:08 ` Jose Ricardo Ziviani
  2017-01-12 20:08 ` [Qemu-devel] [PATCH v6 2/2] ppc: Implement bcdutrunc. instruction Jose Ricardo Ziviani
  2017-01-12 23:32 ` [Qemu-devel] [PATCH v6 0/2] POWER9 TCG enablements - BCD functions - final part David Gibson
  2 siblings, 0 replies; 4+ messages in thread
From: Jose Ricardo Ziviani @ 2017-01-12 20:08 UTC (permalink / raw)
  To: qemu-ppc; +Cc: qemu-devel, david, nikunj

bcdtrunc.: Decimal integer truncate. Given a BCD number in vrb and the
number of bytes to truncate in vra, the return register will have vrb
with such bits truncated.

Signed-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com>
---
 target/ppc/helper.h                 |  1 +
 target/ppc/int_helper.c             | 37 +++++++++++++++++++++++++++++++++++++
 target/ppc/translate/vmx-impl.inc.c |  5 +++++
 target/ppc/translate/vmx-ops.inc.c  |  4 ++--
 4 files changed, 45 insertions(+), 2 deletions(-)

diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index d1db462..db17917 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -401,6 +401,7 @@ DEF_HELPER_3(bcdsetsgn, i32, avr, avr, i32)
 DEF_HELPER_4(bcds, i32, avr, avr, avr, i32)
 DEF_HELPER_4(bcdus, i32, avr, avr, avr, i32)
 DEF_HELPER_4(bcdsr, i32, avr, avr, avr, i32)
+DEF_HELPER_4(bcdtrunc, i32, avr, avr, avr, i32)
 
 DEF_HELPER_2(xsadddp, void, env, i32)
 DEF_HELPER_2(xsaddqp, void, env, i32)
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index 7b6045f..5b75c8a 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -3223,6 +3223,43 @@ uint32_t helper_bcdsr(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t ps)
     return cr;
 }
 
+uint32_t helper_bcdtrunc(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t ps)
+{
+    uint64_t mask;
+    uint32_t ox_flag = 0;
+#if defined(HOST_WORDS_BIGENDIAN)
+    int i = a->s16[3] + 1;
+#else
+    int i = a->s16[4] + 1;
+#endif
+    ppc_avr_t ret = *b;
+
+    if (bcd_is_valid(b) == false) {
+        return CRF_SO;
+    }
+
+    if (i > 16 && i < 32) {
+        mask = (uint64_t)-1 >> (128 - i * 4);
+        if (ret.u64[HI_IDX] & ~mask) {
+            ox_flag = CRF_SO;
+        }
+
+        ret.u64[HI_IDX] &= mask;
+    } else if (i >= 0 && i <= 16) {
+        mask = (uint64_t)-1 >> (64 - i * 4);
+        if (ret.u64[HI_IDX] || (ret.u64[LO_IDX] & ~mask)) {
+            ox_flag = CRF_SO;
+        }
+
+        ret.u64[LO_IDX] &= mask;
+        ret.u64[HI_IDX] = 0;
+    }
+    bcd_put_digit(&ret, bcd_preferred_sgn(bcd_get_sgn(b), ps), 0);
+    *r = ret;
+
+    return bcd_cmp_zero(&ret) | ox_flag;
+}
+
 void helper_vsbox(ppc_avr_t *r, ppc_avr_t *a)
 {
     int i;
diff --git a/target/ppc/translate/vmx-impl.inc.c b/target/ppc/translate/vmx-impl.inc.c
index 451abb5..1683f42 100644
--- a/target/ppc/translate/vmx-impl.inc.c
+++ b/target/ppc/translate/vmx-impl.inc.c
@@ -1019,6 +1019,7 @@ GEN_BCD(bcdcpsgn);
 GEN_BCD(bcds);
 GEN_BCD(bcdus);
 GEN_BCD(bcdsr);
+GEN_BCD(bcdtrunc);
 
 static void gen_xpnd04_1(DisasContext *ctx)
 {
@@ -1097,6 +1098,10 @@ GEN_VXFORM_DUAL(vsubudm, PPC2_ALTIVEC_207, PPC_NONE, \
                 bcds, PPC_NONE, PPC2_ISA300)
 GEN_VXFORM_DUAL(vsubuwm, PPC_ALTIVEC, PPC_NONE, \
                 bcdus, PPC_NONE, PPC2_ISA300)
+GEN_VXFORM_DUAL(vsubsbs, PPC_ALTIVEC, PPC_NONE, \
+                bcdtrunc, PPC_NONE, PPC2_ISA300)
+GEN_VXFORM_DUAL(vsubuqm, PPC2_ALTIVEC_207, PPC_NONE, \
+                bcdtrunc, PPC_NONE, PPC2_ISA300)
 
 static void gen_vsbox(DisasContext *ctx)
 {
diff --git a/target/ppc/translate/vmx-ops.inc.c b/target/ppc/translate/vmx-ops.inc.c
index fa9c996..e6167a4 100644
--- a/target/ppc/translate/vmx-ops.inc.c
+++ b/target/ppc/translate/vmx-ops.inc.c
@@ -143,14 +143,14 @@ GEN_VXFORM(vaddsws, 0, 14),
 GEN_VXFORM_DUAL(vsububs, bcdadd, 0, 24, PPC_ALTIVEC, PPC_NONE),
 GEN_VXFORM_DUAL(vsubuhs, bcdsub, 0, 25, PPC_ALTIVEC, PPC_NONE),
 GEN_VXFORM(vsubuws, 0, 26),
-GEN_VXFORM(vsubsbs, 0, 28),
+GEN_VXFORM_DUAL(vsubsbs, bcdtrunc, 0, 28, PPC_NONE, PPC2_ISA300),
 GEN_VXFORM(vsubshs, 0, 29),
 GEN_VXFORM_DUAL(vsubsws, xpnd04_2, 0, 30, PPC_ALTIVEC, PPC_NONE),
 GEN_VXFORM_207(vadduqm, 0, 4),
 GEN_VXFORM_207(vaddcuq, 0, 5),
 GEN_VXFORM_DUAL(vaddeuqm, vaddecuq, 30, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
-GEN_VXFORM_207(vsubuqm, 0, 20),
 GEN_VXFORM_207(vsubcuq, 0, 21),
+GEN_VXFORM_DUAL(vsubuqm, bcdtrunc, 0, 20, PPC2_ALTIVEC_207, PPC2_ISA300),
 GEN_VXFORM_DUAL(vsubeuqm, vsubecuq, 31, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
 GEN_VXFORM(vrlb, 2, 0),
 GEN_VXFORM(vrlh, 2, 1),
-- 
2.7.4

^ permalink raw reply related	[flat|nested] 4+ messages in thread

* [Qemu-devel] [PATCH v6 2/2] ppc: Implement bcdutrunc. instruction
  2017-01-12 20:08 [Qemu-devel] [PATCH v6 0/2] POWER9 TCG enablements - BCD functions - final part Jose Ricardo Ziviani
  2017-01-12 20:08 ` [Qemu-devel] [PATCH v6 1/2] ppc: Implement bcdtrunc. instruction Jose Ricardo Ziviani
@ 2017-01-12 20:08 ` Jose Ricardo Ziviani
  2017-01-12 23:32 ` [Qemu-devel] [PATCH v6 0/2] POWER9 TCG enablements - BCD functions - final part David Gibson
  2 siblings, 0 replies; 4+ messages in thread
From: Jose Ricardo Ziviani @ 2017-01-12 20:08 UTC (permalink / raw)
  To: qemu-ppc; +Cc: qemu-devel, david, nikunj

bcdutrunc. Decimal unsigned truncate. Works like bcdtrunc. with
unsigned BCD numbers.

Signed-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com>
---
 target/ppc/helper.h                 |  1 +
 target/ppc/int_helper.c             | 51 +++++++++++++++++++++++++++++++++++++
 target/ppc/translate/vmx-impl.inc.c |  4 +++
 target/ppc/translate/vmx-ops.inc.c  |  2 +-
 4 files changed, 57 insertions(+), 1 deletion(-)

diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index db17917..c2e6b42 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -402,6 +402,7 @@ DEF_HELPER_4(bcds, i32, avr, avr, avr, i32)
 DEF_HELPER_4(bcdus, i32, avr, avr, avr, i32)
 DEF_HELPER_4(bcdsr, i32, avr, avr, avr, i32)
 DEF_HELPER_4(bcdtrunc, i32, avr, avr, avr, i32)
+DEF_HELPER_4(bcdutrunc, i32, avr, avr, avr, i32)
 
 DEF_HELPER_2(xsadddp, void, env, i32)
 DEF_HELPER_2(xsaddqp, void, env, i32)
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index 5b75c8a..9138626 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -3260,6 +3260,57 @@ uint32_t helper_bcdtrunc(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t ps)
     return bcd_cmp_zero(&ret) | ox_flag;
 }
 
+uint32_t helper_bcdutrunc(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t ps)
+{
+    int i;
+    uint64_t mask;
+    uint32_t ox_flag = 0;
+    int invalid = 0;
+    ppc_avr_t ret = *b;
+
+    for (i = 0; i < 32; i++) {
+        bcd_get_digit(b, i, &invalid);
+
+        if (unlikely(invalid)) {
+            return CRF_SO;
+        }
+    }
+
+#if defined(HOST_WORDS_BIGENDIAN)
+    i = a->s16[3];
+#else
+    i = a->s16[4];
+#endif
+    if (i > 16 && i < 33) {
+        mask = (uint64_t)-1 >> (128 - i * 4);
+        if (ret.u64[HI_IDX] & ~mask) {
+            ox_flag = CRF_SO;
+        }
+
+        ret.u64[HI_IDX] &= mask;
+    } else if (i > 0 && i <= 16) {
+        mask = (uint64_t)-1 >> (64 - i * 4);
+        if (ret.u64[HI_IDX] || (ret.u64[LO_IDX] & ~mask)) {
+            ox_flag = CRF_SO;
+        }
+
+        ret.u64[LO_IDX] &= mask;
+        ret.u64[HI_IDX] = 0;
+    } else if (i == 0) {
+        if (ret.u64[HI_IDX] || ret.u64[LO_IDX]) {
+            ox_flag = CRF_SO;
+        }
+        ret.u64[HI_IDX] = ret.u64[LO_IDX] = 0;
+    }
+
+    *r = ret;
+    if (r->u64[HI_IDX] == 0 && r->u64[LO_IDX] == 0) {
+        return ox_flag | CRF_EQ;
+    }
+
+    return ox_flag | CRF_GT;
+}
+
 void helper_vsbox(ppc_avr_t *r, ppc_avr_t *a)
 {
     int i;
diff --git a/target/ppc/translate/vmx-impl.inc.c b/target/ppc/translate/vmx-impl.inc.c
index 1683f42..3cb6fc2 100644
--- a/target/ppc/translate/vmx-impl.inc.c
+++ b/target/ppc/translate/vmx-impl.inc.c
@@ -1020,6 +1020,7 @@ GEN_BCD(bcds);
 GEN_BCD(bcdus);
 GEN_BCD(bcdsr);
 GEN_BCD(bcdtrunc);
+GEN_BCD(bcdutrunc);
 
 static void gen_xpnd04_1(DisasContext *ctx)
 {
@@ -1102,6 +1103,9 @@ GEN_VXFORM_DUAL(vsubsbs, PPC_ALTIVEC, PPC_NONE, \
                 bcdtrunc, PPC_NONE, PPC2_ISA300)
 GEN_VXFORM_DUAL(vsubuqm, PPC2_ALTIVEC_207, PPC_NONE, \
                 bcdtrunc, PPC_NONE, PPC2_ISA300)
+GEN_VXFORM_DUAL(vsubcuq, PPC2_ALTIVEC_207, PPC_NONE, \
+                bcdutrunc, PPC_NONE, PPC2_ISA300)
+
 
 static void gen_vsbox(DisasContext *ctx)
 {
diff --git a/target/ppc/translate/vmx-ops.inc.c b/target/ppc/translate/vmx-ops.inc.c
index e6167a4..139f80c 100644
--- a/target/ppc/translate/vmx-ops.inc.c
+++ b/target/ppc/translate/vmx-ops.inc.c
@@ -149,8 +149,8 @@ GEN_VXFORM_DUAL(vsubsws, xpnd04_2, 0, 30, PPC_ALTIVEC, PPC_NONE),
 GEN_VXFORM_207(vadduqm, 0, 4),
 GEN_VXFORM_207(vaddcuq, 0, 5),
 GEN_VXFORM_DUAL(vaddeuqm, vaddecuq, 30, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
-GEN_VXFORM_207(vsubcuq, 0, 21),
 GEN_VXFORM_DUAL(vsubuqm, bcdtrunc, 0, 20, PPC2_ALTIVEC_207, PPC2_ISA300),
+GEN_VXFORM_DUAL(vsubcuq, bcdutrunc, 0, 21, PPC2_ALTIVEC_207, PPC2_ISA300),
 GEN_VXFORM_DUAL(vsubeuqm, vsubecuq, 31, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
 GEN_VXFORM(vrlb, 2, 0),
 GEN_VXFORM(vrlh, 2, 1),
-- 
2.7.4

^ permalink raw reply related	[flat|nested] 4+ messages in thread

* Re: [Qemu-devel] [PATCH v6 0/2] POWER9 TCG enablements - BCD functions - final part
  2017-01-12 20:08 [Qemu-devel] [PATCH v6 0/2] POWER9 TCG enablements - BCD functions - final part Jose Ricardo Ziviani
  2017-01-12 20:08 ` [Qemu-devel] [PATCH v6 1/2] ppc: Implement bcdtrunc. instruction Jose Ricardo Ziviani
  2017-01-12 20:08 ` [Qemu-devel] [PATCH v6 2/2] ppc: Implement bcdutrunc. instruction Jose Ricardo Ziviani
@ 2017-01-12 23:32 ` David Gibson
  2 siblings, 0 replies; 4+ messages in thread
From: David Gibson @ 2017-01-12 23:32 UTC (permalink / raw)
  To: Jose Ricardo Ziviani; +Cc: qemu-ppc, qemu-devel, nikunj

[-- Attachment #1: Type: text/plain, Size: 1864 bytes --]


Applied to ppc-for-2.9.

On Thu, Jan 12, 2017 at 06:08:31PM -0200, Jose Ricardo Ziviani wrote:
> v6:
>  - improves bcdtrunc/bcdutrunc overflow comparison
>  - removes bcds/bcdus/bcdsr applied patches
> 
> v5:
>  - removes 'unlikely' gcc branch pred. hints from not unlikely places
>  - adds comments in host-utils functions
>  - adds more test cases for shift functions
>  - handles "shift backwards" with signed shifts
>  - rebases branch
> 
> v4:
>  - improves functions to behave exactly like the target
> 
> v3:
>  - moves shift functions to host-utils.c and added config_int128 guard
>  - changes Makefile to always compile host-utils.c
>  - redesigns bcd[u]trunc to use bitwise operations
>  - removes "target-ppc: Implement bcd_is_valid function" (merged)
> 
> v2:
>  - bcd[s,sr,us] uses 1 byte for shifting instead of 4 bytes
>  - left/right functions in host-utils are out of CONFIG_INT128
>  - fixes overflowing issue in left shift and added a testcase
> 
> This serie contains 5 new instructions for POWER9 ISA3.0, left/right shifts for 
> unsigned quadwords and a small improvement to check whether a bcd value is 
> valid or not.
> 
> bcdtrunc.: Decimal signed trucate
> bcdutrunc.: Decimal unsigned truncate
> 
> Jose Ricardo Ziviani (2):
>   ppc: Implement bcdtrunc. instruction
>   ppc: Implement bcdutrunc. instruction
> 
>  target/ppc/helper.h                 |  2 +
>  target/ppc/int_helper.c             | 88 +++++++++++++++++++++++++++++++++++++
>  target/ppc/translate/vmx-impl.inc.c |  9 ++++
>  target/ppc/translate/vmx-ops.inc.c  |  6 +--
>  4 files changed, 102 insertions(+), 3 deletions(-)
> 

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 819 bytes --]

^ permalink raw reply	[flat|nested] 4+ messages in thread

end of thread, other threads:[~2017-01-12 23:41 UTC | newest]

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2017-01-12 20:08 [Qemu-devel] [PATCH v6 0/2] POWER9 TCG enablements - BCD functions - final part Jose Ricardo Ziviani
2017-01-12 20:08 ` [Qemu-devel] [PATCH v6 1/2] ppc: Implement bcdtrunc. instruction Jose Ricardo Ziviani
2017-01-12 20:08 ` [Qemu-devel] [PATCH v6 2/2] ppc: Implement bcdutrunc. instruction Jose Ricardo Ziviani
2017-01-12 23:32 ` [Qemu-devel] [PATCH v6 0/2] POWER9 TCG enablements - BCD functions - final part David Gibson

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