From: Laurent Vivier <laurent@vivier.eu>
To: qemu-devel@nongnu.org
Cc: rth@twiddle.net, Laurent Vivier <laurent@vivier.eu>
Subject: [Qemu-devel] [PATCH 0/5] Fixes for target/m68k
Date: Thu, 12 Jan 2017 21:17:59 +0100 [thread overview]
Message-ID: <1484252284-29291-1-git-send-email-laurent@vivier.eu> (raw)
This is a series of fixes for target/m68k found:
- with RISU (bit operation with immediate)
- while debugging package build under chroot
(gen_flush_flags() and CAS address modes)
- while I was working on the softmmu mode
(CAS alignment and SP address modes)
Laurent Vivier (5):
target-m68k: fix bit operation with immediate value
target-m68k: fix gen_flush_flags()
target-m68k: manage pre-dec et post-inc in CAS
target-m68k: CAS doesn't need aligned access
target-m68k: increment/decrement with SP
target/m68k/translate.c | 36 +++++++++++++++++++++++++++++-------
1 file changed, 29 insertions(+), 7 deletions(-)
--
2.7.4
next reply other threads:[~2017-01-12 20:18 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-01-12 20:17 Laurent Vivier [this message]
2017-01-12 20:18 ` [Qemu-devel] [PATCH 1/5] target-m68k: fix bit operation with immediate value Laurent Vivier
2017-01-12 20:18 ` [Qemu-devel] [PATCH 2/5] target-m68k: fix gen_flush_flags() Laurent Vivier
2017-01-12 20:18 ` [Qemu-devel] [PATCH 3/5] target-m68k: manage pre-dec et post-inc in CAS Laurent Vivier
2017-01-12 20:18 ` [Qemu-devel] [PATCH 4/5] target-m68k: CAS doesn't need aligned access Laurent Vivier
2017-01-12 20:18 ` [Qemu-devel] [PATCH 5/5] target-m68k: increment/decrement with SP Laurent Vivier
2017-01-12 21:14 ` Thomas Huth
2017-01-12 21:35 ` Laurent Vivier
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