From: Laurent Vivier <laurent@vivier.eu>
To: qemu-devel@nongnu.org
Cc: rth@twiddle.net, Laurent Vivier <laurent@vivier.eu>
Subject: [Qemu-devel] [PATCH 1/5] target-m68k: fix bit operation with immediate value
Date: Thu, 12 Jan 2017 21:18:00 +0100 [thread overview]
Message-ID: <1484252284-29291-2-git-send-email-laurent@vivier.eu> (raw)
In-Reply-To: <1484252284-29291-1-git-send-email-laurent@vivier.eu>
M680x0 bit operations with an immediate value use 9 bits of the 16bit
value, while coldfire ones use only 8 bits.
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
---
target/m68k/translate.c | 13 ++++++++++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index 5f7357e..410f56a 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -1801,9 +1801,16 @@ DISAS_INSN(bitop_im)
op = (insn >> 6) & 3;
bitnum = read_im16(env, s);
- if (bitnum & 0xff00) {
- disas_undef(env, s, insn);
- return;
+ if (m68k_feature(s->env, M68K_FEATURE_M68000)) {
+ if (bitnum & 0xfe00) {
+ disas_undef(env, s, insn);
+ return;
+ }
+ } else {
+ if (bitnum & 0xff00) {
+ disas_undef(env, s, insn);
+ return;
+ }
}
SRC_EA(env, src1, opsize, 0, op ? &addr: NULL);
--
2.7.4
next prev parent reply other threads:[~2017-01-12 20:18 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-01-12 20:17 [Qemu-devel] [PATCH 0/5] Fixes for target/m68k Laurent Vivier
2017-01-12 20:18 ` Laurent Vivier [this message]
2017-01-12 20:18 ` [Qemu-devel] [PATCH 2/5] target-m68k: fix gen_flush_flags() Laurent Vivier
2017-01-12 20:18 ` [Qemu-devel] [PATCH 3/5] target-m68k: manage pre-dec et post-inc in CAS Laurent Vivier
2017-01-12 20:18 ` [Qemu-devel] [PATCH 4/5] target-m68k: CAS doesn't need aligned access Laurent Vivier
2017-01-12 20:18 ` [Qemu-devel] [PATCH 5/5] target-m68k: increment/decrement with SP Laurent Vivier
2017-01-12 21:14 ` Thomas Huth
2017-01-12 21:35 ` Laurent Vivier
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