From: Laurent Vivier <laurent@vivier.eu>
To: qemu-devel@nongnu.org
Cc: rth@twiddle.net, Laurent Vivier <laurent@vivier.eu>
Subject: [Qemu-devel] [PATCH 5/5] target-m68k: increment/decrement with SP
Date: Thu, 12 Jan 2017 21:18:04 +0100 [thread overview]
Message-ID: <1484252284-29291-6-git-send-email-laurent@vivier.eu> (raw)
In-Reply-To: <1484252284-29291-1-git-send-email-laurent@vivier.eu>
Address Register indirect With postincrement:
When using the stack pointer (A7) with byte size data, the register
is incremented by two.
Address Register indirect With predecrement:
When using the stack pointer (A7) with byte size data, the register
is decremented by two.
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
---
target/m68k/translate.c | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index cf5d8dd..c83d902 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -725,7 +725,10 @@ static TCGv gen_lea_mode(CPUM68KState *env, DisasContext *s,
}
reg = get_areg(s, reg0);
tmp = tcg_temp_new();
- tcg_gen_subi_i32(tmp, reg, opsize_bytes(opsize));
+ tcg_gen_subi_i32(tmp, reg,
+ reg0 == 7 && opsize == OS_BYTE
+ ? 2
+ : opsize_bytes(opsize));
return tmp;
case 5: /* Indirect displacement. */
reg = get_areg(s, reg0);
@@ -801,7 +804,10 @@ static TCGv gen_ea_mode(CPUM68KState *env, DisasContext *s, int mode, int reg0,
result = gen_ldst(s, opsize, reg, val, what);
if (what == EA_STORE || !addrp) {
TCGv tmp = tcg_temp_new();
- tcg_gen_addi_i32(tmp, reg, opsize_bytes(opsize));
+ tcg_gen_addi_i32(tmp, reg,
+ reg0 == 7 && opsize == OS_BYTE
+ ? 2
+ : opsize_bytes(opsize));
delay_set_areg(s, reg0, tmp, true);
}
return result;
--
2.7.4
next prev parent reply other threads:[~2017-01-12 20:18 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-01-12 20:17 [Qemu-devel] [PATCH 0/5] Fixes for target/m68k Laurent Vivier
2017-01-12 20:18 ` [Qemu-devel] [PATCH 1/5] target-m68k: fix bit operation with immediate value Laurent Vivier
2017-01-12 20:18 ` [Qemu-devel] [PATCH 2/5] target-m68k: fix gen_flush_flags() Laurent Vivier
2017-01-12 20:18 ` [Qemu-devel] [PATCH 3/5] target-m68k: manage pre-dec et post-inc in CAS Laurent Vivier
2017-01-12 20:18 ` [Qemu-devel] [PATCH 4/5] target-m68k: CAS doesn't need aligned access Laurent Vivier
2017-01-12 20:18 ` Laurent Vivier [this message]
2017-01-12 21:14 ` [Qemu-devel] [PATCH 5/5] target-m68k: increment/decrement with SP Thomas Huth
2017-01-12 21:35 ` Laurent Vivier
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