[Qemu-devel] [PATCH 12/18] tcg/i386: support remaining vector addition operations

[Kirill Batuzov <batuzovk@ispras.ru>]

Signed-off-by: Kirill Batuzov <batuzovk@ispras.ru>
---
 tcg/i386/tcg-target.h     | 10 ++++++++++
 tcg/i386/tcg-target.inc.c | 37 +++++++++++++++++++++++++++++++++++++
 2 files changed, 47 insertions(+)

diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index 849b339..5deb08e 100644
--- a/tcg/i386/tcg-target.h
+++ b/tcg/i386/tcg-target.h
@@ -151,7 +151,17 @@ extern bool have_bmi1;
 #endif
 
 #ifdef TCG_TARGET_HAS_REG128
+#define TCG_TARGET_HAS_add_i8x16        1
+#define TCG_TARGET_HAS_add_i16x8        1
 #define TCG_TARGET_HAS_add_i32x4        1
+#define TCG_TARGET_HAS_add_i64x2        1
+#endif
+
+#ifdef TCG_TARGET_HAS_REGV64
+#define TCG_TARGET_HAS_add_i8x8         1
+#define TCG_TARGET_HAS_add_i16x4        1
+#define TCG_TARGET_HAS_add_i32x2        1
+#define TCG_TARGET_HAS_add_i64x1        1
 #endif
 
 #define TCG_TARGET_deposit_i32_valid(ofs, len) \
diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c
index a2d5e09..d00bd12 100644
--- a/tcg/i386/tcg-target.inc.c
+++ b/tcg/i386/tcg-target.inc.c
@@ -377,7 +377,10 @@ static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
 #define OPC_MOVQ_M2R    (0x7e | P_SSE_F30F)
 #define OPC_MOVQ_R2M    (0xd6 | P_SSE_660F)
 #define OPC_MOVQ_R2R    (0xd6 | P_SSE_660F)
+#define OPC_PADDB       (0xfc | P_SSE_660F)
+#define OPC_PADDW       (0xfd | P_SSE_660F)
 #define OPC_PADDD       (0xfe | P_SSE_660F)
+#define OPC_PADDQ       (0xd4 | P_SSE_660F)
 
 /* Group 1 opcode extensions for 0x80-0x83.
    These are also used as modifiers for OPC_ARITH.  */
@@ -2251,9 +2254,33 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
         break;
 
 #ifdef TCG_TARGET_HAS_REG128
+    case INDEX_op_add_i8x16:
+        tcg_out_modrm(s, OPC_PADDB, args[0], args[2]);
+        break;
+    case INDEX_op_add_i16x8:
+        tcg_out_modrm(s, OPC_PADDW, args[0], args[2]);
+        break;
     case INDEX_op_add_i32x4:
         tcg_out_modrm(s, OPC_PADDD, args[0], args[2]);
         break;
+    case INDEX_op_add_i64x2:
+        tcg_out_modrm(s, OPC_PADDQ, args[0], args[2]);
+        break;
+#endif
+
+#ifdef TCG_TARGET_HAS_REGV64
+    case INDEX_op_add_i8x8:
+        tcg_out_modrm(s, OPC_PADDB, args[0], args[2]);
+        break;
+    case INDEX_op_add_i16x4:
+        tcg_out_modrm(s, OPC_PADDW, args[0], args[2]);
+        break;
+    case INDEX_op_add_i32x2:
+        tcg_out_modrm(s, OPC_PADDD, args[0], args[2]);
+        break;
+    case INDEX_op_add_i64x1:
+        tcg_out_modrm(s, OPC_PADDQ, args[0], args[2]);
+        break;
 #endif
 
     case INDEX_op_mov_i32:  /* Always emitted via tcg_out_mov.  */
@@ -2411,7 +2438,17 @@ static const TCGTargetOpDef x86_op_defs[] = {
 #endif
 
 #ifdef TCG_TARGET_HAS_REG128
+    { INDEX_op_add_i8x16, { "V", "0", "V" } },
+    { INDEX_op_add_i16x8, { "V", "0", "V" } },
     { INDEX_op_add_i32x4, { "V", "0", "V" } },
+    { INDEX_op_add_i64x2, { "V", "0", "V" } },
+#endif
+
+#ifdef TCG_TARGET_HAS_REGV64
+    { INDEX_op_add_i8x8, { "V", "0", "V" } },
+    { INDEX_op_add_i16x4, { "V", "0", "V" } },
+    { INDEX_op_add_i32x2, { "V", "0", "V" } },
+    { INDEX_op_add_i64x1, { "V", "0", "V" } },
 #endif
     { -1 },
 };
-- 
2.1.4