From: Artyom Tarasenko <atar4qemu@gmail.com>
To: peter.maydell@linaro.org
Cc: qemu-devel@nongnu.org, mark.cave-ayland@ilande.co.uk,
rth@twiddle.net, Artyom Tarasenko <atar4qemu@gmail.com>
Subject: [Qemu-devel] [PULL 10/30] target-sparc: hypervisor mode takes over nucleus mode
Date: Wed, 18 Jan 2017 23:38:23 +0100 [thread overview]
Message-ID: <1484779123-18968-11-git-send-email-atar4qemu@gmail.com> (raw)
In-Reply-To: <1484779123-18968-1-git-send-email-atar4qemu@gmail.com>
Accordinf to UA2005, 9.3.3 "Address Space Identifiers",
"In hyperprivileged mode, all instruction fetches and loads and stores with implicit
ASIs use a physical address, regardless of the value of TL".
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
---
target/sparc/cpu.h | 4 ++--
target/sparc/translate.c | 6 +++++-
2 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index 9307b91..00fbb4e 100644
--- a/target/sparc/cpu.h
+++ b/target/sparc/cpu.h
@@ -719,10 +719,10 @@ static inline int cpu_mmu_index(CPUSPARCState *env, bool ifetch)
? (env->lsu & IMMU_E) == 0 || (env->pstate & PS_RED) != 0
: (env->lsu & DMMU_E) == 0) {
return MMU_PHYS_IDX;
- } else if (env->tl > 0) {
- return MMU_NUCLEUS_IDX;
} else if (cpu_hypervisor_mode(env)) {
return MMU_HYPV_IDX;
+ } else if (env->tl > 0) {
+ return MMU_NUCLEUS_IDX;
} else if (cpu_supervisor_mode(env)) {
return MMU_KERNEL_IDX;
} else {
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 8902e44..009ea3a 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -2142,7 +2142,11 @@ static DisasASI get_asi(DisasContext *dc, int insn, TCGMemOp memop)
case ASI_TWINX_NL:
case ASI_NUCLEUS_QUAD_LDD:
case ASI_NUCLEUS_QUAD_LDD_L:
- mem_idx = MMU_NUCLEUS_IDX;
+ if (hypervisor(dc)) {
+ mem_idx = MMU_HYPV_IDX;
+ } else {
+ mem_idx = MMU_NUCLEUS_IDX;
+ }
break;
case ASI_AIUP: /* As if user primary */
case ASI_AIUPL: /* As if user primary LE */
--
2.7.2
next prev parent reply other threads:[~2017-01-18 22:39 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-01-18 22:38 [Qemu-devel] [PULL 00/30] target-sparc sun4v support Artyom Tarasenko
2017-01-18 22:38 ` [Qemu-devel] [PULL 01/30] target-sparc: ignore MMU-faults if MMU is disabled in hypervisor mode Artyom Tarasenko
2017-01-18 22:38 ` [Qemu-devel] [PULL 02/30] target-sparc: store cpu super- and hypervisor flags in TB Artyom Tarasenko
2017-01-18 22:38 ` [Qemu-devel] [PULL 03/30] target-sparc: use explicit mmu register pointers Artyom Tarasenko
2017-01-18 22:38 ` [Qemu-devel] [PULL 04/30] target-sparc: add UA2005 TTE bit #defines Artyom Tarasenko
2017-01-18 22:38 ` [Qemu-devel] [PULL 05/30] target-sparc: add UltraSPARC T1 TLB #defines Artyom Tarasenko
2017-01-18 22:38 ` [Qemu-devel] [PULL 06/30] target-sparc: on UA2005 don't deliver Interrupt_level_n IRQs in hypervisor mode Artyom Tarasenko
2017-01-18 22:38 ` [Qemu-devel] [PULL 07/30] target-sparc: simplify replace_tlb_entry by using TTE_PGSIZE Artyom Tarasenko
2017-01-18 22:38 ` [Qemu-devel] [PULL 08/30] target-sparc: implement UA2005 scratchpad registers Artyom Tarasenko
2017-01-18 22:38 ` [Qemu-devel] [PULL 09/30] target-sparc: implement UltraSPARC-T1 Strand status ASR Artyom Tarasenko
2017-01-18 22:38 ` Artyom Tarasenko [this message]
2017-01-18 22:38 ` [Qemu-devel] [PULL 11/30] target-sparc: implement UA2005 hypervisor traps Artyom Tarasenko
2017-01-18 22:38 ` [Qemu-devel] [PULL 12/30] target-sparc: implement UA2005 GL register Artyom Tarasenko
2017-01-18 22:38 ` [Qemu-devel] [PULL 13/30] target-sparc: implement UA2005 rdhpstate and wrhpstate instructions Artyom Tarasenko
2017-01-18 22:38 ` [Qemu-devel] [PULL 14/30] target-sparc: fix immediate UA2005 traps Artyom Tarasenko
2017-01-18 22:38 ` [Qemu-devel] [PULL 15/30] target-sparc: use direct address translation in hyperprivileged mode Artyom Tarasenko
2017-01-18 22:38 ` [Qemu-devel] [PULL 16/30] target-sparc: allow priveleged ASIs " Artyom Tarasenko
2017-01-18 22:38 ` [Qemu-devel] [PULL 17/30] target-sparc: ignore writes to UA2005 CPU mondo queue register Artyom Tarasenko
2017-01-18 22:38 ` [Qemu-devel] [PULL 18/30] target-sparc: replace the last tlb entry when no free entries left Artyom Tarasenko
2017-01-18 22:38 ` [Qemu-devel] [PULL 19/30] target-sparc: use SparcV9MMU type for sparc64 I/D-MMUs Artyom Tarasenko
2017-01-18 22:38 ` [Qemu-devel] [PULL 20/30] target-sparc: implement UA2005 TSB Pointers Artyom Tarasenko
2017-01-18 22:38 ` [Qemu-devel] [PULL 21/30] target-sparc: simplify ultrasparc_tsb_pointer Artyom Tarasenko
2017-01-18 22:38 ` [Qemu-devel] [PULL 22/30] target-sparc: allow 256M sized pages Artyom Tarasenko
2017-01-18 22:38 ` [Qemu-devel] [PULL 23/30] target-sparc: implement auto-demapping for UA2005 CPUs Artyom Tarasenko
2017-01-18 22:38 ` [Qemu-devel] [PULL 24/30] target-sparc: add more registers to dump_mmu Artyom Tarasenko
2017-01-18 22:38 ` [Qemu-devel] [PULL 25/30] target-sparc: implement UA2005 ASI_MMU (0x21) Artyom Tarasenko
2017-01-18 22:38 ` [Qemu-devel] [PULL 27/30] target-sparc: add ST_BLKINIT_ ASIs for UA2005+ CPUs Artyom Tarasenko
2017-01-18 22:38 ` [Qemu-devel] [PULL 28/30] target-sparc: implement sun4v RTC Artyom Tarasenko
2017-01-18 22:38 ` [Qemu-devel] [PULL 29/30] target-sparc: move common cpu initialisation routines to sparc64.c Artyom Tarasenko
2017-01-18 22:38 ` [Qemu-devel] [PULL 30/30] target-sparc: fix up niagara machine Artyom Tarasenko
2017-01-23 12:40 ` Peter Maydell
2017-01-23 14:10 ` Artyom Tarasenko
2017-01-23 14:24 ` Peter Maydell
2017-01-23 14:59 ` Artyom Tarasenko
2017-01-23 15:05 ` Peter Maydell
2017-02-24 11:50 ` Peter Maydell
2017-02-24 12:35 ` Artyom Tarasenko
2017-01-27 15:07 ` Jakub Jermář
2017-01-19 19:21 ` [Qemu-devel] [PULL 00/30] target-sparc sun4v support Peter Maydell
-- strict thread matches above, loose matches on Subject: below --
2017-01-12 2:55 Richard Henderson
2017-01-12 2:55 ` [Qemu-devel] [PULL 10/30] target-sparc: hypervisor mode takes over nucleus mode Richard Henderson
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