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From: Artyom Tarasenko <atar4qemu@gmail.com>
To: peter.maydell@linaro.org
Cc: qemu-devel@nongnu.org, mark.cave-ayland@ilande.co.uk,
	rth@twiddle.net, Artyom Tarasenko <atar4qemu@gmail.com>
Subject: [Qemu-devel] [PULL 28/30] target-sparc: implement sun4v RTC
Date: Wed, 18 Jan 2017 23:38:41 +0100	[thread overview]
Message-ID: <1484779123-18968-29-git-send-email-atar4qemu@gmail.com> (raw)
In-Reply-To: <1484779123-18968-1-git-send-email-atar4qemu@gmail.com>

Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
---
 MAINTAINERS                  |   6 +++
 hw/timer/Makefile.objs       |   2 +
 hw/timer/sun4v-rtc.c         | 102 +++++++++++++++++++++++++++++++++++++++++++
 include/hw/timer/sun4v-rtc.h |   1 +
 4 files changed, 111 insertions(+)
 create mode 100644 hw/timer/sun4v-rtc.c
 create mode 100644 include/hw/timer/sun4v-rtc.h

diff --git a/MAINTAINERS b/MAINTAINERS
index 1444b26..54588e5 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1098,6 +1098,12 @@ F: hw/nvram/chrp_nvram.c
 F: include/hw/nvram/chrp_nvram.h
 F: tests/prom-env-test.c
 
+sun4v RTC
+M: Artyom Tarasenko <atar4qemu@gmail.com>
+S: Maintained
+F: hw/timer/sun4v-rtc.c
+F: include/hw/timer/sun4v-rtc.h
+
 Subsystems
 ----------
 Audio
diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs
index 7ba8c23..c1e93a3 100644
--- a/hw/timer/Makefile.objs
+++ b/hw/timer/Makefile.objs
@@ -34,3 +34,5 @@ obj-$(CONFIG_ALLWINNER_A10_PIT) += allwinner-a10-pit.o
 
 common-obj-$(CONFIG_STM32F2XX_TIMER) += stm32f2xx_timer.o
 common-obj-$(CONFIG_ASPEED_SOC) += aspeed_timer.o
+
+common-obj-$(CONFIG_SUN4V_RTC) += sun4v-rtc.o
diff --git a/hw/timer/sun4v-rtc.c b/hw/timer/sun4v-rtc.c
new file mode 100644
index 0000000..82e9e14
--- /dev/null
+++ b/hw/timer/sun4v-rtc.c
@@ -0,0 +1,102 @@
+/*
+ * QEMU sun4v Real Time Clock device
+ *
+ * The sun4v_rtc device (sun4v tod clock)
+ *
+ * Copyright (c) 2016 Artyom Tarasenko
+ *
+ * This code is licensed under the GNU GPL v3 or (at your option) any later
+ * version.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/hw.h"
+#include "hw/sysbus.h"
+#include "qemu/timer.h"
+#include "hw/timer/sun4v-rtc.h"
+
+//#define DEBUG_SUN4V_RTC
+
+#ifdef DEBUG_SUN4V_RTC
+#define DPRINTF(fmt, ...)                                       \
+    do { printf("sun4v_rtc: " fmt , ## __VA_ARGS__); } while (0)
+#else
+#define DPRINTF(fmt, ...) do {} while (0)
+#endif
+
+#define TYPE_SUN4V_RTC "sun4v_rtc"
+#define SUN4V_RTC(obj) OBJECT_CHECK(Sun4vRtc, (obj), TYPE_SUN4V_RTC)
+
+typedef struct Sun4vRtc {
+    SysBusDevice parent_obj;
+
+    MemoryRegion iomem;
+} Sun4vRtc;
+
+static uint64_t sun4v_rtc_read(void *opaque, hwaddr addr,
+                                unsigned size)
+{
+    uint64_t val = qemu_clock_get_ms(QEMU_CLOCK_REALTIME) / 1000;
+    if (!(addr & 4ULL)) {
+        /* accessing the high 32 bits */
+        val >>= 32;
+    }
+    DPRINTF("read from " TARGET_FMT_plx " val %lx\n", addr, val);
+    return val;
+}
+
+static void sun4v_rtc_write(void *opaque, hwaddr addr,
+                             uint64_t val, unsigned size)
+{
+    DPRINTF("write 0x%x to " TARGET_FMT_plx "\n", (unsigned)val, addr);
+}
+
+static const MemoryRegionOps sun4v_rtc_ops = {
+    .read = sun4v_rtc_read,
+    .write = sun4v_rtc_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+void sun4v_rtc_init(hwaddr addr)
+{
+    DeviceState *dev;
+    SysBusDevice *s;
+
+    dev = qdev_create(NULL, TYPE_SUN4V_RTC);
+    s = SYS_BUS_DEVICE(dev);
+
+    qdev_init_nofail(dev);
+
+    sysbus_mmio_map(s, 0, addr);
+}
+
+static int sun4v_rtc_init1(SysBusDevice *dev)
+{
+    Sun4vRtc *s = SUN4V_RTC(dev);
+
+    memory_region_init_io(&s->iomem, OBJECT(s), &sun4v_rtc_ops, s,
+                          "sun4v-rtc", 0x08ULL);
+    sysbus_init_mmio(dev, &s->iomem);
+    return 0;
+}
+
+static void sun4v_rtc_class_init(ObjectClass *klass, void *data)
+{
+    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
+
+    k->init = sun4v_rtc_init1;
+}
+
+static const TypeInfo sun4v_rtc_info = {
+    .name          = TYPE_SUN4V_RTC,
+    .parent        = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(Sun4vRtc),
+    .class_init    = sun4v_rtc_class_init,
+};
+
+static void sun4v_rtc_register_types(void)
+{
+    type_register_static(&sun4v_rtc_info);
+}
+
+type_init(sun4v_rtc_register_types)
diff --git a/include/hw/timer/sun4v-rtc.h b/include/hw/timer/sun4v-rtc.h
new file mode 100644
index 0000000..407278f
--- /dev/null
+++ b/include/hw/timer/sun4v-rtc.h
@@ -0,0 +1 @@
+void sun4v_rtc_init(hwaddr addr);
-- 
2.7.2

  parent reply	other threads:[~2017-01-18 22:40 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-01-18 22:38 [Qemu-devel] [PULL 00/30] target-sparc sun4v support Artyom Tarasenko
2017-01-18 22:38 ` [Qemu-devel] [PULL 01/30] target-sparc: ignore MMU-faults if MMU is disabled in hypervisor mode Artyom Tarasenko
2017-01-18 22:38 ` [Qemu-devel] [PULL 02/30] target-sparc: store cpu super- and hypervisor flags in TB Artyom Tarasenko
2017-01-18 22:38 ` [Qemu-devel] [PULL 03/30] target-sparc: use explicit mmu register pointers Artyom Tarasenko
2017-01-18 22:38 ` [Qemu-devel] [PULL 04/30] target-sparc: add UA2005 TTE bit #defines Artyom Tarasenko
2017-01-18 22:38 ` [Qemu-devel] [PULL 05/30] target-sparc: add UltraSPARC T1 TLB #defines Artyom Tarasenko
2017-01-18 22:38 ` [Qemu-devel] [PULL 06/30] target-sparc: on UA2005 don't deliver Interrupt_level_n IRQs in hypervisor mode Artyom Tarasenko
2017-01-18 22:38 ` [Qemu-devel] [PULL 07/30] target-sparc: simplify replace_tlb_entry by using TTE_PGSIZE Artyom Tarasenko
2017-01-18 22:38 ` [Qemu-devel] [PULL 08/30] target-sparc: implement UA2005 scratchpad registers Artyom Tarasenko
2017-01-18 22:38 ` [Qemu-devel] [PULL 09/30] target-sparc: implement UltraSPARC-T1 Strand status ASR Artyom Tarasenko
2017-01-18 22:38 ` [Qemu-devel] [PULL 10/30] target-sparc: hypervisor mode takes over nucleus mode Artyom Tarasenko
2017-01-18 22:38 ` [Qemu-devel] [PULL 11/30] target-sparc: implement UA2005 hypervisor traps Artyom Tarasenko
2017-01-18 22:38 ` [Qemu-devel] [PULL 12/30] target-sparc: implement UA2005 GL register Artyom Tarasenko
2017-01-18 22:38 ` [Qemu-devel] [PULL 13/30] target-sparc: implement UA2005 rdhpstate and wrhpstate instructions Artyom Tarasenko
2017-01-18 22:38 ` [Qemu-devel] [PULL 14/30] target-sparc: fix immediate UA2005 traps Artyom Tarasenko
2017-01-18 22:38 ` [Qemu-devel] [PULL 15/30] target-sparc: use direct address translation in hyperprivileged mode Artyom Tarasenko
2017-01-18 22:38 ` [Qemu-devel] [PULL 16/30] target-sparc: allow priveleged ASIs " Artyom Tarasenko
2017-01-18 22:38 ` [Qemu-devel] [PULL 17/30] target-sparc: ignore writes to UA2005 CPU mondo queue register Artyom Tarasenko
2017-01-18 22:38 ` [Qemu-devel] [PULL 18/30] target-sparc: replace the last tlb entry when no free entries left Artyom Tarasenko
2017-01-18 22:38 ` [Qemu-devel] [PULL 19/30] target-sparc: use SparcV9MMU type for sparc64 I/D-MMUs Artyom Tarasenko
2017-01-18 22:38 ` [Qemu-devel] [PULL 20/30] target-sparc: implement UA2005 TSB Pointers Artyom Tarasenko
2017-01-18 22:38 ` [Qemu-devel] [PULL 21/30] target-sparc: simplify ultrasparc_tsb_pointer Artyom Tarasenko
2017-01-18 22:38 ` [Qemu-devel] [PULL 22/30] target-sparc: allow 256M sized pages Artyom Tarasenko
2017-01-18 22:38 ` [Qemu-devel] [PULL 23/30] target-sparc: implement auto-demapping for UA2005 CPUs Artyom Tarasenko
2017-01-18 22:38 ` [Qemu-devel] [PULL 24/30] target-sparc: add more registers to dump_mmu Artyom Tarasenko
2017-01-18 22:38 ` [Qemu-devel] [PULL 25/30] target-sparc: implement UA2005 ASI_MMU (0x21) Artyom Tarasenko
2017-01-18 22:38 ` [Qemu-devel] [PULL 27/30] target-sparc: add ST_BLKINIT_ ASIs for UA2005+ CPUs Artyom Tarasenko
2017-01-18 22:38 ` Artyom Tarasenko [this message]
2017-01-18 22:38 ` [Qemu-devel] [PULL 29/30] target-sparc: move common cpu initialisation routines to sparc64.c Artyom Tarasenko
2017-01-18 22:38 ` [Qemu-devel] [PULL 30/30] target-sparc: fix up niagara machine Artyom Tarasenko
2017-01-23 12:40   ` Peter Maydell
2017-01-23 14:10     ` Artyom Tarasenko
2017-01-23 14:24       ` Peter Maydell
2017-01-23 14:59         ` Artyom Tarasenko
2017-01-23 15:05           ` Peter Maydell
2017-02-24 11:50         ` Peter Maydell
2017-02-24 12:35           ` Artyom Tarasenko
2017-01-27 15:07       ` Jakub Jermář
2017-01-19 19:21 ` [Qemu-devel] [PULL 00/30] target-sparc sun4v support Peter Maydell
  -- strict thread matches above, loose matches on Subject: below --
2017-01-12  2:55 Richard Henderson
2017-01-12  2:56 ` [Qemu-devel] [PULL 28/30] target-sparc: implement sun4v RTC Richard Henderson

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