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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 00/36] target-arm queue
Date: Thu, 19 Jan 2017 14:09:19 +0000	[thread overview]
Message-ID: <1484834995-26826-1-git-send-email-peter.maydell@linaro.org> (raw)

ARM queue -- the big bit here is the virtualization
stuff for the GIC and correspondingly enabling it in
the virt board.

thanks
-- PMM

The following changes since commit ab4b92760498e097ff668f0e9c83aa87a2ec1128:

  Merge remote-tracking branch 'remotes/stefanha/tags/tracing-pull-request' into staging (2017-01-17 16:54:09 +0000)

are available in the git repository at:

  git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170119

for you to fetch changes up to 245c8cbc4e4f0f8b6c3dfaab2090d1d55f94d360:

  hw/arm/virt: Add board property to enable EL2 (2017-01-19 13:40:23 +0000)

----------------------------------------------------------------
target-arm queue:
 * support virtualization in GICv3
 * enable EL2 in AArch64 CPU models
 * allow EL2 to be enabled on 'virt' board via -machine virtualization=on
 * aspeed: SMC improvements
 * m25p80: support die erase command
 * m25p80: Add Quad Page Program 4byte
 * m25p80: Improve 1GiB Micron flash definition
 * arm: Uniquely name imx25 I2C buses

----------------------------------------------------------------
Alastair D'Silva (1):
      arm: Uniquely name imx25 I2C buses.

Andrew Jones (1):
      hw/arm/virt-acpi-build: use SMC if booting in EL2

Ard Biesheuvel (1):
      hw/arm/virt-acpi - reserve ECAM space as PNP0C02 device

Cédric Le Goater (10):
      aspeed/smc: remove call to reset in realize function
      aspeed/smc: remove call to aspeed_smc_update_cs() in reset function
      aspeed/smc: rework the prototype of the AspeedSMCFlash helper routines
      aspeed/smc: autostrap CE0/1 configuration
      aspeed/smc: unfold the AspeedSMCController array
      aspeed/smc: adjust the size of the register region
      aspeed/smc: handle SPI flash Command mode
      aspeed/smc: reset flash after each test
      aspeed/smc: extend tests for Command mode
      aspeed: use first FMC flash as a boot ROM

Marcin Krzeminski (3):
      block: m25p80: Add Quad Page Program 4byte
      block: m25p80: Introduce die erase command
      block: m25p80: Improve 1GiB Micron flash definition

Peter Maydell (19):
      target/arm: Handle VIRQ and VFIQ in arm_cpu_do_interrupt_aarch32()
      target/arm: Implement DBGVCR32_EL2 system register
      hw/intc/arm_gicv3: Add external IRQ lines for VIRQ and VFIQ
      hw/intc/arm_gic: Add external IRQ lines for VIRQ and VFIQ
      target-arm: Expose output GPIO line for VCPU maintenance interrupt
      hw/arm/virt: Wire VIRQ, VFIQ, maintenance irq lines from GIC to CPU
      target-arm: Add ARMCPU fields for GIC CPU i/f config
      hw/intc/gicv3: Add defines for ICH system register fields
      hw/intc/gicv3: Add data fields for virtualization support
      hw/intc/arm_gicv3: Add accessors for ICH_ system registers
      hw/intc/arm_gicv3: Implement ICV_ registers which are just accessors
      hw/intc/arm_gicv3: Implement ICV_ HPPIR, DIR and RPR registers
      hw/intc/arm_gicv3: Implement ICV_ registers EOIR and IAR
      hw/intc/arm_gicv3: Implement gicv3_cpuif_virt_update()
      hw/intc/arm_gicv3: Implement EL2 traps for CPU i/f regs
      hw/arm/virt: Support using SMC for PSCI
      target/arm/psci.c: If EL2 implemented, start CPUs in EL2
      target-arm: Enable EL2 feature bit on A53 and A57
      hw/arm/virt: Add board property to enable EL2

Shannon Zhao (1):
      arm: virt: Fix segmentation fault when specifying an unsupported CPU

 hw/intc/gicv3_internal.h           |   79 +++
 include/hw/arm/virt.h              |    5 +-
 include/hw/intc/arm_gic_common.h   |    2 +
 include/hw/intc/arm_gicv3_common.h |   21 +
 include/hw/ssi/aspeed_smc.h        |    4 +-
 target/arm/cpu.h                   |    9 +
 hw/arm/aspeed.c                    |   41 ++
 hw/arm/imx25_pdk.c                 |    2 +-
 hw/arm/virt-acpi-build.c           |   36 +-
 hw/arm/virt.c                      |   88 ++-
 hw/arm/xlnx-zynqmp.c               |    2 +
 hw/block/m25p80.c                  |   51 +-
 hw/i2c/imx_i2c.c                   |    2 +-
 hw/intc/arm_gic_common.c           |    6 +
 hw/intc/arm_gicv3_common.c         |   31 +
 hw/intc/arm_gicv3_cpuif.c          | 1351 +++++++++++++++++++++++++++++++++++-
 hw/ssi/aspeed_smc.c                |  330 +++++++--
 target/arm/cpu.c                   |   15 +
 target/arm/cpu64.c                 |    8 +
 target/arm/helper.c                |   21 +
 target/arm/psci.c                  |   25 +-
 tests/m25p80-test.c                |  133 ++++
 hw/intc/trace-events               |   33 +
 23 files changed, 2154 insertions(+), 141 deletions(-)

             reply	other threads:[~2017-01-19 14:10 UTC|newest]

Thread overview: 51+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-01-19 14:09 Peter Maydell [this message]
2017-01-19 14:09 ` [Qemu-devel] [PULL 01/36] arm: Uniquely name imx25 I2C buses Peter Maydell
2017-01-19 14:09 ` [Qemu-devel] [PULL 02/36] block: m25p80: Add Quad Page Program 4byte Peter Maydell
2017-01-19 14:09 ` [Qemu-devel] [PULL 03/36] block: m25p80: Introduce die erase command Peter Maydell
2017-01-19 14:09 ` [Qemu-devel] [PULL 04/36] block: m25p80: Improve 1GiB Micron flash definition Peter Maydell
2017-01-19 14:09 ` [Qemu-devel] [PULL 05/36] target/arm: Handle VIRQ and VFIQ in arm_cpu_do_interrupt_aarch32() Peter Maydell
2017-01-19 14:09 ` [Qemu-devel] [PULL 06/36] target/arm: Implement DBGVCR32_EL2 system register Peter Maydell
2017-01-19 14:09 ` [Qemu-devel] [PULL 07/36] aspeed/smc: remove call to reset in realize function Peter Maydell
2017-01-19 14:09 ` [Qemu-devel] [PULL 08/36] aspeed/smc: remove call to aspeed_smc_update_cs() in reset function Peter Maydell
2017-01-19 14:09 ` [Qemu-devel] [PULL 09/36] aspeed/smc: rework the prototype of the AspeedSMCFlash helper routines Peter Maydell
2017-01-19 14:09 ` [Qemu-devel] [PULL 10/36] aspeed/smc: autostrap CE0/1 configuration Peter Maydell
2017-01-19 14:09 ` [Qemu-devel] [PULL 11/36] aspeed/smc: unfold the AspeedSMCController array Peter Maydell
2017-01-19 14:09 ` [Qemu-devel] [PULL 12/36] aspeed/smc: adjust the size of the register region Peter Maydell
2017-01-19 14:09 ` [Qemu-devel] [PULL 13/36] aspeed/smc: handle SPI flash Command mode Peter Maydell
2017-01-19 14:09 ` [Qemu-devel] [PULL 14/36] aspeed/smc: reset flash after each test Peter Maydell
2017-01-19 14:09 ` [Qemu-devel] [PULL 15/36] aspeed/smc: extend tests for Command mode Peter Maydell
2017-01-19 14:09 ` [Qemu-devel] [PULL 16/36] aspeed: use first FMC flash as a boot ROM Peter Maydell
2017-01-19 14:09 ` [Qemu-devel] [PULL 17/36] arm: virt: Fix segmentation fault when specifying an unsupported CPU Peter Maydell
2017-01-19 14:09 ` [Qemu-devel] [PULL 18/36] hw/arm/virt-acpi - reserve ECAM space as PNP0C02 device Peter Maydell
2017-01-19 14:09 ` [Qemu-devel] [PULL 19/36] hw/intc/arm_gicv3: Add external IRQ lines for VIRQ and VFIQ Peter Maydell
2017-01-19 14:09 ` [Qemu-devel] [PULL 20/36] hw/intc/arm_gic: " Peter Maydell
2017-01-19 14:09 ` [Qemu-devel] [PULL 21/36] target-arm: Expose output GPIO line for VCPU maintenance interrupt Peter Maydell
2017-01-19 14:09 ` [Qemu-devel] [PULL 22/36] hw/arm/virt: Wire VIRQ, VFIQ, maintenance irq lines from GIC to CPU Peter Maydell
2017-01-19 14:09 ` [Qemu-devel] [PULL 23/36] target-arm: Add ARMCPU fields for GIC CPU i/f config Peter Maydell
2017-01-19 14:09 ` [Qemu-devel] [PULL 24/36] hw/intc/gicv3: Add defines for ICH system register fields Peter Maydell
2017-01-19 14:09 ` [Qemu-devel] [PULL 25/36] hw/intc/gicv3: Add data fields for virtualization support Peter Maydell
2017-01-19 14:09 ` [Qemu-devel] [PULL 26/36] hw/intc/arm_gicv3: Add accessors for ICH_ system registers Peter Maydell
2017-01-26  9:35   ` Paolo Bonzini
2017-01-26  9:42     ` Thomas Huth
2017-01-19 14:09 ` [Qemu-devel] [PULL 27/36] hw/intc/arm_gicv3: Implement ICV_ registers which are just accessors Peter Maydell
2017-01-19 14:09 ` [Qemu-devel] [PULL 28/36] hw/intc/arm_gicv3: Implement ICV_ HPPIR, DIR and RPR registers Peter Maydell
2017-01-19 14:09 ` [Qemu-devel] [PULL 29/36] hw/intc/arm_gicv3: Implement ICV_ registers EOIR and IAR Peter Maydell
2017-01-19 14:09 ` [Qemu-devel] [PULL 30/36] hw/intc/arm_gicv3: Implement gicv3_cpuif_virt_update() Peter Maydell
2017-01-19 14:09 ` [Qemu-devel] [PULL 31/36] hw/intc/arm_gicv3: Implement EL2 traps for CPU i/f regs Peter Maydell
2017-01-19 14:09 ` [Qemu-devel] [PULL 32/36] hw/arm/virt: Support using SMC for PSCI Peter Maydell
2017-01-19 14:09 ` [Qemu-devel] [PULL 33/36] hw/arm/virt-acpi-build: use SMC if booting in EL2 Peter Maydell
2017-01-19 14:09 ` [Qemu-devel] [PULL 34/36] target/arm/psci.c: If EL2 implemented, start CPUs " Peter Maydell
2017-01-19 14:09 ` [Qemu-devel] [PULL 35/36] target-arm: Enable EL2 feature bit on A53 and A57 Peter Maydell
2017-01-19 14:09 ` [Qemu-devel] [PULL 36/36] hw/arm/virt: Add board property to enable EL2 Peter Maydell
  -- strict thread matches above, loose matches on Subject: below --
2017-09-04 14:39 [Qemu-devel] [PULL 00/36] target-arm queue Peter Maydell
2017-09-04 16:20 ` Peter Maydell
2017-09-04 12:25 Peter Maydell
2016-09-22 17:21 Peter Maydell
2016-09-22 19:58 ` no-reply
2016-09-23  9:57 ` Peter Maydell
2016-02-18 15:20 Peter Maydell
2016-02-18 15:50 ` Peter Maydell
2016-02-18 14:34 Peter Maydell
2016-02-18 15:19 ` Peter Maydell
2016-01-21 14:55 Peter Maydell
2016-01-21 15:53 ` Peter Maydell

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