From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 17/22] armv7m: FAULTMASK should be 0 on reset
Date: Fri, 27 Jan 2017 15:32:12 +0000 [thread overview]
Message-ID: <1485531137-2362-18-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1485531137-2362-1-git-send-email-peter.maydell@linaro.org>
From: Michael Davidsaver <mdavidsaver@gmail.com>
For M profile CPUs, FAULTMASK should be 0 on reset, like PRIMASK.
QEMU stores FAULTMASK in the PSTATE F bit, so (as with PRIMASK in the
I bit) we have to clear these to undo the A profile default of 1.
Update the comment accordingly and move it so that it's closer to the
code it's referring to.
Signed-off-by: Michael Davidsaver <mdavidsaver@gmail.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 1485285380-10565-10-git-send-email-peter.maydell@linaro.org
[PMM: rewrote commit message, moved comments]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu.c | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index c804f59..0814f73 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -179,15 +179,16 @@ static void arm_cpu_reset(CPUState *s)
/* SVC mode with interrupts disabled. */
env->uncached_cpsr = ARM_CPU_MODE_SVC;
env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F;
- /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
- * clear at reset. Initial SP and PC are loaded from ROM.
- */
+
if (arm_feature(env, ARM_FEATURE_M)) {
uint32_t initial_msp; /* Loaded from 0x0 */
uint32_t initial_pc; /* Loaded from 0x4 */
uint8_t *rom;
- env->daif &= ~PSTATE_I;
+ /* For M profile we store FAULTMASK and PRIMASK in the
+ * PSTATE F and I bits; these are both clear at reset.
+ */
+ env->daif &= ~(PSTATE_I | PSTATE_F);
/* The reset value of this bit is IMPDEF, but ARM recommends
* that it resets to 1, so QEMU always does that rather than making
@@ -195,6 +196,7 @@ static void arm_cpu_reset(CPUState *s)
*/
env->v7m.ccr = R_V7M_CCR_STKALIGN_MASK;
+ /* Load the initial SP and PC from the vector table at address 0 */
rom = rom_ptr(0);
if (rom) {
/* Address zero is covered by ROM which hasn't yet been
--
2.7.4
next prev parent reply other threads:[~2017-01-27 15:32 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-01-27 15:31 [Qemu-devel] [PULL 00/22] target-arm queue Peter Maydell
2017-01-27 15:31 ` [Qemu-devel] [PULL 01/22] aspeed/smc: handle dummy bytes when doing fast reads in command mode Peter Maydell
2017-01-27 15:31 ` [Qemu-devel] [PULL 02/22] armv7m: MRS/MSR: handle unprivileged access Peter Maydell
2017-01-27 15:31 ` [Qemu-devel] [PULL 03/22] armv7m: Replace armv7m.hack with unassigned_access handler Peter Maydell
2017-01-27 15:31 ` [Qemu-devel] [PULL 04/22] armv7m: Explicit error for bad vector table Peter Maydell
2017-01-27 15:32 ` [Qemu-devel] [PULL 05/22] hw/registerfields.h: Pull FIELD etc macros out of hw/register.h Peter Maydell
2017-01-27 15:32 ` [Qemu-devel] [PULL 06/22] armv7m: Fix reads of CONTROL register bit 1 Peter Maydell
2017-01-27 15:32 ` [Qemu-devel] [PULL 07/22] armv7m: Clear FAULTMASK on return from non-NMI exceptions Peter Maydell
2017-01-27 15:32 ` [Qemu-devel] [PULL 08/22] pflash_cfi01: fix per-device sector length in CFI table Peter Maydell
2017-01-27 15:32 ` [Qemu-devel] [PULL 09/22] target/arm: Drop IS_M() macro Peter Maydell
2017-01-27 15:32 ` [Qemu-devel] [PULL 10/22] armv7m_nvic: keep a pointer to the CPU Peter Maydell
2017-01-27 15:32 ` [Qemu-devel] [PULL 11/22] armv7m: add state for v7M CCR, CFSR, HFSR, DFSR, MMFAR, BFAR Peter Maydell
2017-01-27 15:32 ` [Qemu-devel] [PULL 12/22] armv7m: implement CCR, CFSR, HFSR, DFSR, BFAR, and MMFAR Peter Maydell
2017-01-27 15:32 ` [Qemu-devel] [PULL 13/22] armv7m: honour CCR.STACKALIGN on exception entry Peter Maydell
2017-01-27 15:32 ` [Qemu-devel] [PULL 14/22] armv7m: set CFSR.UNDEFINSTR on undefined instructions Peter Maydell
2017-01-27 15:32 ` [Qemu-devel] [PULL 15/22] armv7m: Report no-coprocessor faults correctly Peter Maydell
2017-01-27 15:32 ` [Qemu-devel] [PULL 16/22] armv7m: Honour CCR.USERSETMPEND Peter Maydell
2017-01-27 15:32 ` Peter Maydell [this message]
2017-01-27 15:32 ` [Qemu-devel] [PULL 18/22] armv7m: R14 should reset to 0xffffffff Peter Maydell
2017-01-27 15:32 ` [Qemu-devel] [PULL 19/22] arm: stellaris: make MII accesses complete immediately Peter Maydell
2017-01-27 15:32 ` [Qemu-devel] [PULL 20/22] hw/char/exynos4210_uart: Drop unused local variable frame_size Peter Maydell
2017-01-27 15:32 ` [Qemu-devel] [PULL 21/22] arm_gicv3: Fix broken logic in ELRSR calculation Peter Maydell
2017-01-27 15:32 ` [Qemu-devel] [PULL 22/22] dma: omap: check dma channel data_type Peter Maydell
2017-01-27 16:12 ` [Qemu-devel] [PULL 00/22] target-arm queue no-reply
2017-01-30 10:23 ` Peter Maydell
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