From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 18/22] armv7m: R14 should reset to 0xffffffff
Date: Fri, 27 Jan 2017 15:32:13 +0000 [thread overview]
Message-ID: <1485531137-2362-19-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1485531137-2362-1-git-send-email-peter.maydell@linaro.org>
For M profile (unlike A profile) the reset value of R14 is specified
as 0xffffffff. (The rationale is that this is an illegal exception
return value, so if guest code tries to return to it it will result
in a helpful exception.)
Registers r0 to r12 and the flags are architecturally UNKNOWN on
reset, so we leave those at zero.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 1485285380-10565-11-git-send-email-peter.maydell@linaro.org
---
target/arm/cpu.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 0814f73..e9f10f7 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -196,6 +196,9 @@ static void arm_cpu_reset(CPUState *s)
*/
env->v7m.ccr = R_V7M_CCR_STKALIGN_MASK;
+ /* Unlike A/R profile, M profile defines the reset LR value */
+ env->regs[14] = 0xffffffff;
+
/* Load the initial SP and PC from the vector table at address 0 */
rom = rom_ptr(0);
if (rom) {
--
2.7.4
next prev parent reply other threads:[~2017-01-27 15:32 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-01-27 15:31 [Qemu-devel] [PULL 00/22] target-arm queue Peter Maydell
2017-01-27 15:31 ` [Qemu-devel] [PULL 01/22] aspeed/smc: handle dummy bytes when doing fast reads in command mode Peter Maydell
2017-01-27 15:31 ` [Qemu-devel] [PULL 02/22] armv7m: MRS/MSR: handle unprivileged access Peter Maydell
2017-01-27 15:31 ` [Qemu-devel] [PULL 03/22] armv7m: Replace armv7m.hack with unassigned_access handler Peter Maydell
2017-01-27 15:31 ` [Qemu-devel] [PULL 04/22] armv7m: Explicit error for bad vector table Peter Maydell
2017-01-27 15:32 ` [Qemu-devel] [PULL 05/22] hw/registerfields.h: Pull FIELD etc macros out of hw/register.h Peter Maydell
2017-01-27 15:32 ` [Qemu-devel] [PULL 06/22] armv7m: Fix reads of CONTROL register bit 1 Peter Maydell
2017-01-27 15:32 ` [Qemu-devel] [PULL 07/22] armv7m: Clear FAULTMASK on return from non-NMI exceptions Peter Maydell
2017-01-27 15:32 ` [Qemu-devel] [PULL 08/22] pflash_cfi01: fix per-device sector length in CFI table Peter Maydell
2017-01-27 15:32 ` [Qemu-devel] [PULL 09/22] target/arm: Drop IS_M() macro Peter Maydell
2017-01-27 15:32 ` [Qemu-devel] [PULL 10/22] armv7m_nvic: keep a pointer to the CPU Peter Maydell
2017-01-27 15:32 ` [Qemu-devel] [PULL 11/22] armv7m: add state for v7M CCR, CFSR, HFSR, DFSR, MMFAR, BFAR Peter Maydell
2017-01-27 15:32 ` [Qemu-devel] [PULL 12/22] armv7m: implement CCR, CFSR, HFSR, DFSR, BFAR, and MMFAR Peter Maydell
2017-01-27 15:32 ` [Qemu-devel] [PULL 13/22] armv7m: honour CCR.STACKALIGN on exception entry Peter Maydell
2017-01-27 15:32 ` [Qemu-devel] [PULL 14/22] armv7m: set CFSR.UNDEFINSTR on undefined instructions Peter Maydell
2017-01-27 15:32 ` [Qemu-devel] [PULL 15/22] armv7m: Report no-coprocessor faults correctly Peter Maydell
2017-01-27 15:32 ` [Qemu-devel] [PULL 16/22] armv7m: Honour CCR.USERSETMPEND Peter Maydell
2017-01-27 15:32 ` [Qemu-devel] [PULL 17/22] armv7m: FAULTMASK should be 0 on reset Peter Maydell
2017-01-27 15:32 ` Peter Maydell [this message]
2017-01-27 15:32 ` [Qemu-devel] [PULL 19/22] arm: stellaris: make MII accesses complete immediately Peter Maydell
2017-01-27 15:32 ` [Qemu-devel] [PULL 20/22] hw/char/exynos4210_uart: Drop unused local variable frame_size Peter Maydell
2017-01-27 15:32 ` [Qemu-devel] [PULL 21/22] arm_gicv3: Fix broken logic in ELRSR calculation Peter Maydell
2017-01-27 15:32 ` [Qemu-devel] [PULL 22/22] dma: omap: check dma channel data_type Peter Maydell
2017-01-27 16:12 ` [Qemu-devel] [PULL 00/22] target-arm queue no-reply
2017-01-30 10:23 ` Peter Maydell
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