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From: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
To: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, rth@twiddle.net
Cc: qemu-devel@nongnu.org, bharata@linux.vnet.ibm.com,
	nikunj@linux.vnet.ibm.com
Subject: [Qemu-devel] [PATCH 1/6] target-ppc: generate exception for copy/paste
Date: Thu,  9 Feb 2017 16:04:00 +0530	[thread overview]
Message-ID: <1486636445-24109-2-git-send-email-nikunj@linux.vnet.ibm.com> (raw)
In-Reply-To: <1486636445-24109-1-git-send-email-nikunj@linux.vnet.ibm.com>

Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
 target/ppc/translate.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 255735a..80f9f15 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -6132,6 +6132,19 @@ static inline void gen_cp_abort(DisasContext *ctx)
     // Do Nothing
 }
 
+#define GEN_CP_PASTE_NOOP(name)                           \
+static inline void gen_##name(DisasContext *ctx)          \
+{                                                         \
+    /* Generate invalid exception until                   \
+     * we have an implementation of the copy              \
+     * paste facility                                     \
+     */                                                   \
+    gen_invalid(ctx);                                     \
+}
+
+GEN_CP_PASTE_NOOP(copy)
+GEN_CP_PASTE_NOOP(paste)
+
 static void gen_tcheck(DisasContext *ctx)
 {
     if (unlikely(!ctx->tm_enabled)) {
@@ -6281,7 +6294,9 @@ GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
 GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300),
+GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300),
 GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300),
+GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300),
 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
-- 
2.7.4

  reply	other threads:[~2017-02-09 10:35 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-02-09 10:33 [Qemu-devel] [PATCH 0/6] POWER9 TCG enablements - part15 Nikunj A Dadhania
2017-02-09 10:34 ` Nikunj A Dadhania [this message]
2017-02-09 10:34 ` [Qemu-devel] [PATCH 2/6] target-ppc: add slbieg instruction Nikunj A Dadhania
2017-02-09 10:34 ` [Qemu-devel] [PATCH 3/6] target-ppc: add slbsync implementation Nikunj A Dadhania
2017-02-09 10:34 ` [Qemu-devel] [PATCH 4/6] target-ppc: add wait instruction Nikunj A Dadhania
2017-02-09 10:34 ` [Qemu-devel] [PATCH 5/6] target-ppc: support for 32-bit carry and overflow Nikunj A Dadhania
2017-02-10  0:10   ` David Gibson
2017-02-10  4:19     ` Nikunj A Dadhania
2017-02-13  1:54       ` David Gibson
2017-02-14  2:43       ` David Gibson
2017-02-14  3:05         ` Nikunj A Dadhania
2017-02-14  3:21           ` Richard Henderson
2017-02-16  5:08             ` Nikunj A Dadhania
2017-02-16 20:52               ` Richard Henderson
2017-02-17  4:47                 ` Nikunj A Dadhania
2017-02-17 19:33                   ` Richard Henderson
2017-02-09 10:34 ` [Qemu-devel] [PATCH 6/6] target-ppc: add mcrxrx instruction Nikunj A Dadhania
2017-02-10  0:28 ` [Qemu-devel] [PATCH 0/6] POWER9 TCG enablements - part15 David Gibson

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