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From: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
To: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, rth@twiddle.net
Cc: qemu-devel@nongnu.org, bharata@linux.vnet.ibm.com,
	nikunj@linux.vnet.ibm.com
Subject: [Qemu-devel] [PATCH 3/6] target-ppc: add slbsync implementation
Date: Thu,  9 Feb 2017 16:04:02 +0530	[thread overview]
Message-ID: <1486636445-24109-4-git-send-email-nikunj@linux.vnet.ibm.com> (raw)
In-Reply-To: <1486636445-24109-1-git-send-email-nikunj@linux.vnet.ibm.com>

slbsync: SLB Synchoronize

The instruction provides an ordering function for the effects of all
slbieg instructions executed by the thread executing the slbsync
instruction.

Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
 target/ppc/translate.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index b0f3c3b..b1a6aee 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -4497,6 +4497,17 @@ static void gen_slbieg(DisasContext *ctx)
 #endif /* defined(CONFIG_USER_ONLY) */
 }
 
+/* slbsync */
+static void gen_slbsync(DisasContext *ctx)
+{
+#if defined(CONFIG_USER_ONLY)
+    GEN_PRIV;
+#else
+    CHK_SV;
+    gen_check_tlb_flush(ctx, true);
+#endif /* defined(CONFIG_USER_ONLY) */
+}
+
 #endif  /* defined(TARGET_PPC64) */
 
 /***                              External control                         ***/
@@ -6453,6 +6464,7 @@ GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI),
 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
 GEN_HANDLER_E(slbieg, 0x1F, 0x12, 0x0E, 0x001F0001, PPC_NONE, PPC2_ISA300),
+GEN_HANDLER_E(slbsync, 0x1F, 0x12, 0x0A, 0x03FFF801, PPC_NONE, PPC2_ISA300),
 #endif
 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
-- 
2.7.4

  parent reply	other threads:[~2017-02-09 10:35 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-02-09 10:33 [Qemu-devel] [PATCH 0/6] POWER9 TCG enablements - part15 Nikunj A Dadhania
2017-02-09 10:34 ` [Qemu-devel] [PATCH 1/6] target-ppc: generate exception for copy/paste Nikunj A Dadhania
2017-02-09 10:34 ` [Qemu-devel] [PATCH 2/6] target-ppc: add slbieg instruction Nikunj A Dadhania
2017-02-09 10:34 ` Nikunj A Dadhania [this message]
2017-02-09 10:34 ` [Qemu-devel] [PATCH 4/6] target-ppc: add wait instruction Nikunj A Dadhania
2017-02-09 10:34 ` [Qemu-devel] [PATCH 5/6] target-ppc: support for 32-bit carry and overflow Nikunj A Dadhania
2017-02-10  0:10   ` David Gibson
2017-02-10  4:19     ` Nikunj A Dadhania
2017-02-13  1:54       ` David Gibson
2017-02-14  2:43       ` David Gibson
2017-02-14  3:05         ` Nikunj A Dadhania
2017-02-14  3:21           ` Richard Henderson
2017-02-16  5:08             ` Nikunj A Dadhania
2017-02-16 20:52               ` Richard Henderson
2017-02-17  4:47                 ` Nikunj A Dadhania
2017-02-17 19:33                   ` Richard Henderson
2017-02-09 10:34 ` [Qemu-devel] [PATCH 6/6] target-ppc: add mcrxrx instruction Nikunj A Dadhania
2017-02-10  0:28 ` [Qemu-devel] [PATCH 0/6] POWER9 TCG enablements - part15 David Gibson

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