From: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
To: qemu-ppc@nongnu.org
Cc: david@gibson.dropbear.id.au, agraf@suse.de,
qemu-devel@nongnu.org, sam.bobroff@au1.ibm.com,
Suraj Jitindar Singh <sjitindarsingh@gmail.com>
Subject: [Qemu-devel] [QEMU-PPC] [PATCH V2 10/10] hw/ppc/spapr: Add POWER9 to pseries cpu models
Date: Fri, 10 Feb 2017 16:26:00 +1100 [thread overview]
Message-ID: <1486704360-27361-11-git-send-email-sjitindarsingh@gmail.com> (raw)
In-Reply-To: <1486704360-27361-1-git-send-email-sjitindarsingh@gmail.com>
Add POWER9 cpu to list of spapr core models which allows it to be specified
as the cpu model for a pseries guest (e.g. -machine pseries -cpu POWER9).
This now allows a POWER9 cpu to boot to userspace in tcg emulation for a
pseries machine with a legacy kernel.
Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
---
hw/ppc/spapr_cpu_core.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c
index 9dddaeb..71253f9 100644
--- a/hw/ppc/spapr_cpu_core.c
+++ b/hw/ppc/spapr_cpu_core.c
@@ -360,6 +360,9 @@ static const char *spapr_core_models[] = {
/* POWER8NVL */
"POWER8NVL_v1.0",
+
+ /* POWER9 */
+ "POWER9_v1.0",
};
void spapr_cpu_core_class_init(ObjectClass *oc, void *data)
--
2.5.5
next prev parent reply other threads:[~2017-02-10 5:26 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-02-10 5:25 [Qemu-devel] [QEMU-PPC] [PATCH V2 00/10] target/ppc: Implement POWER9 pseries tcg Suraj Jitindar Singh
2017-02-10 5:25 ` [Qemu-devel] [QEMU-PPC] [PATCH V2 01/10] target/ppc/POWER9: Add ISAv3.00 MMU definition Suraj Jitindar Singh
2017-02-10 5:25 ` [Qemu-devel] [QEMU-PPC] [PATCH V2 02/10] target/ppc: Fix LPCR DPFD mask define Suraj Jitindar Singh
2017-02-13 1:59 ` David Gibson
2017-02-10 5:25 ` [Qemu-devel] [QEMU-PPC] [PATCH V2 03/10] target/ppc/POWER9: Adapt LPCR handling for POWER9 Suraj Jitindar Singh
2017-02-10 5:25 ` [Qemu-devel] [QEMU-PPC] [PATCH V2 04/10] target/ppc/POWER9: Direct all instr and data storage interrupts to the hypv Suraj Jitindar Singh
2017-02-10 5:25 ` [Qemu-devel] [QEMU-PPC] [PATCH V2 05/10] target/ppc: Add patb_entry to sPAPRMachineState Suraj Jitindar Singh
2017-02-13 2:17 ` David Gibson
2017-02-13 3:40 ` Suraj Jitindar Singh
2017-02-10 5:25 ` [Qemu-devel] [QEMU-PPC] [PATCH V2 06/10] target/ppc: Don't use SDR1 when running under a POWER9 cpu model Suraj Jitindar Singh
2017-02-13 3:44 ` David Gibson
2017-02-10 5:25 ` [Qemu-devel] [QEMU-PPC] [PATCH V2 07/10] target/ppc/POWER9: Add POWER9 mmu fault handler Suraj Jitindar Singh
2017-02-13 4:06 ` David Gibson
2017-02-10 5:25 ` [Qemu-devel] [QEMU-PPC] [PATCH V2 08/10] target/ppc/POWER9: Add POWER9 pa-features definition Suraj Jitindar Singh
2017-02-13 4:33 ` David Gibson
2017-02-10 5:25 ` [Qemu-devel] [QEMU-PPC] [PATCH V2 09/10] target/ppc/POWER9: Add cpu_has_work function for POWER9 Suraj Jitindar Singh
2017-02-13 4:34 ` David Gibson
2017-02-10 5:26 ` Suraj Jitindar Singh [this message]
2017-02-13 4:35 ` [Qemu-devel] [QEMU-PPC] [PATCH V2 10/10] hw/ppc/spapr: Add POWER9 to pseries cpu models David Gibson
2017-02-10 5:28 ` [Qemu-devel] [QEMU-PPC] [PATCH V2 00/10] target/ppc: Implement POWER9 pseries tcg Suraj Jitindar Singh
2017-02-10 5:49 ` Suraj Jitindar Singh
2017-02-10 5:43 ` no-reply
2017-02-13 4:40 ` David Gibson
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