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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 12/12] aspeed/smc: use a modulo to check segment limits
Date: Fri, 10 Feb 2017 18:08:02 +0000	[thread overview]
Message-ID: <1486750082-12324-13-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1486750082-12324-1-git-send-email-peter.maydell@linaro.org>

From: Cédric Le Goater <clg@kaod.org>

The size of a segment is not necessarily a power of 2.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 1486648058-520-5-git-send-email-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/ssi/aspeed_smc.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
index 7017707..cb51573 100644
--- a/hw/ssi/aspeed_smc.c
+++ b/hw/ssi/aspeed_smc.c
@@ -475,15 +475,15 @@ static uint32_t aspeed_smc_check_segment_addr(const AspeedSMCFlash *fl,
     AspeedSegments seg;
 
     aspeed_smc_reg_to_segment(s->regs[R_SEG_ADDR0 + fl->id], &seg);
-    if ((addr & (seg.size - 1)) != addr) {
+    if ((addr % seg.size) != addr) {
         qemu_log_mask(LOG_GUEST_ERROR,
                       "%s: invalid address 0x%08x for CS%d segment : "
                       "[ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]\n",
                       s->ctrl->name, addr, fl->id, seg.addr,
                       seg.addr + seg.size);
+        addr %= seg.size;
     }
 
-    addr &= seg.size - 1;
     return addr;
 }
 
-- 
2.7.4

  parent reply	other threads:[~2017-02-10 18:08 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-02-10 18:07 [Qemu-devel] [PULL 00/12] target-arm queue Peter Maydell
2017-02-10 18:07 ` [Qemu-devel] [PULL 01/12] target-arm: Add support for PMU register PMSELR_EL0 Peter Maydell
2017-02-10 18:07 ` [Qemu-devel] [PULL 02/12] target-arm: Add support for AArch64 PMU register PMXEVTYPER_EL0 Peter Maydell
2017-02-10 18:07 ` [Qemu-devel] [PULL 03/12] target-arm: Add support for PMU register PMINTENSET_EL1 Peter Maydell
2017-02-23 13:58   ` Aaron Lindsay
2017-02-23 14:49     ` Peter Maydell
2017-02-10 18:07 ` [Qemu-devel] [PULL 04/12] target-arm: Enable vPMU support under TCG mode Peter Maydell
2017-02-10 18:07 ` [Qemu-devel] [PULL 05/12] target-arm: Declare virtio-mmio as dma-coherent in dt Peter Maydell
2017-02-10 18:07 ` [Qemu-devel] [PULL 06/12] hw/arm/virt: Declare virtio-mmio as dma cache coherent in ACPI Peter Maydell
2017-02-10 18:07 ` [Qemu-devel] [PULL 07/12] hw/arm/virt: Declare fwcfg " Peter Maydell
2017-02-10 18:07 ` [Qemu-devel] [PULL 08/12] hw/arm/virt: Declare fwcfg as dma cache coherent in dt Peter Maydell
2017-02-10 18:07 ` [Qemu-devel] [PULL 09/12] aspeed: check for negative values returned by blk_getlength() Peter Maydell
2017-02-10 18:08 ` [Qemu-devel] [PULL 10/12] aspeed: remove useless comment on controller segment size Peter Maydell
2017-02-10 18:08 ` [Qemu-devel] [PULL 11/12] aspeed/smc: handle dummies only in fast read mode Peter Maydell
2017-02-10 18:08 ` Peter Maydell [this message]
2017-02-13  9:30 ` [Qemu-devel] [PULL 00/12] target-arm queue Peter Maydell

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